98b0121a9d
loongarch: Use intrinsics::simd for vabsd
2026-05-11 20:31:22 +08:00
1330bfbb28
Merge pull request #2106 from sayantn/cvtf16s16
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Use LLVM intrinsics for `f16` to `{i,u}16` intrinsics
2026-05-11 08:16:06 +00:00
f42d908f99
Merge pull request #2113 from Amanieu/stdarch-maintainers2
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Add davidtwco and adamgemmell as maintainers
2026-05-11 00:39:57 +00:00
46b8878c56
Add davidtwco and adamgemmell as maintainers
2026-05-10 18:56:44 +01:00
5b038a321b
Merge pull request #2111 from sayantn/remove-heuristic
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Remove the `transmute` heuristic from stdarch-gen-arm
2026-05-10 11:11:53 +00:00
9de432f792
Merge pull request #2112 from sayantn/revert-passes
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Revert "Change implementation of `vld1_dup`"
2026-05-10 11:07:56 +00:00
bee0bf631e
Merge pull request #2103 from heiher/vadda
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loongarch: Use `intrinsics::simd` for vadda
2026-05-10 05:33:12 +00:00
611b20079c
Revert "Change implementation of vld1_dup"
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This reverts commit 5f676a53f584e6304985345791525fa06bb9130e.
2026-05-10 07:25:39 +05:30
1d3d92207a
Remove the heuristic for big-endian reversal, reversing only if requested specifically
2026-05-10 05:13:31 +05:30
7012f652b4
gen-arm: split vreinterpret defn into multiple
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This enables the `big_endian_inverse` transformation to apply to some
of these intrinsics only when appropriate.
2026-05-10 05:11:12 +05:30
256c08376a
Merge pull request #2108 from sayantn/cleanup-gen-arm
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A lot of cleanup in stdarch-gen-arm
2026-05-09 08:38:01 +00:00
494200ba48
loongarch: Use intrinsics::simd for vadda
2026-05-09 15:45:57 +08:00
51877654ba
Merge pull request #2097 from heiher/vsadd-sub
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loongarch: Use `intrinsics::simd` for vs{add,sub}
2026-05-09 06:23:59 +00:00
63385588de
Split vcopyq_lane{q}_p64 due to vsetq_lane_p64 requiring aes
2026-05-09 10:01:01 +05:30
95e2c0ff2c
Change implementation of v{us,su,}dot_lane
2026-05-09 09:41:26 +05:30
0d1fd7fa47
Change implementation of vld1_dup
2026-05-09 09:41:25 +05:30
cee8ece450
Change implementation of vmul_lane
2026-05-09 09:41:25 +05:30
3dd1690288
Change implementation of vr{add,sub}hn_high
2026-05-09 09:41:25 +05:30
d4bb7f4fdd
Change implementation of v{q}{r}shr{u}n_high_n
2026-05-09 09:41:25 +05:30
933aa5c3b5
Change implementation of vqrdml{a,s}h_lane
2026-05-09 09:41:24 +05:30
077f63f91e
Change implementation of vqmov{u}n_high
2026-05-09 09:41:24 +05:30
1404a1e5b0
Change implementation of vqdmull{_high}{_lane} and vqrdmulh_lane
2026-05-09 09:41:24 +05:30
63d8cef02f
Change implementation of v{add,sub}{l,w}_high
2026-05-09 09:41:24 +05:30
401582dd27
Change implementation of vmulx_lane
2026-05-09 09:41:24 +05:30
c02a41ccaa
Change implementation of vmull_{high,lane}
2026-05-09 09:41:24 +05:30
ccb273a3c5
Change implementation of vmov{n,l}_high
2026-05-09 09:41:23 +05:30
da1b2021f5
Change implementation of vml{a,s}{l}_lane
2026-05-09 09:41:23 +05:30
4871c490cb
Change implementation of vcvt{x}_f32_f64
2026-05-09 09:41:23 +05:30
8d56c77c04
Change implementation of vab{a,d}l_high
2026-05-09 09:41:23 +05:30
f603c7fb4b
Change implementation of vcopy{q}_lane{q}
2026-05-09 09:41:22 +05:30
229d480cdc
Change implementation of vext
2026-05-09 09:41:22 +05:30
7fb11ae763
Use latest clang versions from kernel.org
2026-05-08 17:35:34 +05:30
7050d69982
gen-arm: use LLVM intrinsics for f16 to {i,u}16
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Instead of doing an `as {i,u}16` cast, we can use the same LLVM
intrinsics as when converting to `{i,u}{32,64}`, which is what Clang does
and ensures the intrinsic result matches.
2026-05-08 17:33:37 +05:30
a2e77970c2
replace uses of simd_extract with vget_lane
2026-05-08 16:11:44 +05:30
0d76cbef9b
Merge pull request #2107 from sayantn/gen-arm-improvements
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gen-arm: Change definitions of some intrinsics
2026-05-08 10:25:19 +00:00
aa37c1b535
gen-arm: fix vfmlal and vfmlsl
2026-05-08 12:47:02 +05:30
a023ebf71f
gen-arm: fix vmlal, vmlsl and vmull
2026-05-08 12:46:59 +05:30
c80d077ffc
loongarch: Use intrinsics::simd for vs{add,sub}
2026-05-08 10:52:55 +08:00
1964b04a31
Merge pull request #2100 from sayantn/gen-arm-ports
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Porting some intrinsics to stdarch-gen-arm
2026-05-08 00:40:07 +00:00
37473be4d0
Merge pull request #2093 from heiher/vbit-clr-rev-set
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loongarch: Use `intrinsics::simd` for vbit{clr,rev,set}
2026-05-07 20:14:46 +00:00
55c9debc59
Merge pull request #2105 from sayantn/gen-arm-improvements
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Some more changes in stdarch-gen-arm
2026-05-07 20:14:02 +00:00
6218201806
gen-arm: write vtbx{1,2,3,4} in terms of vqtbx
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Writing these intrinsics in terms of the `vqtbx_$ty` functions rather
than the `vqtbx` helper function preserves the behaviour while making
them work in big endian.
2026-05-08 01:16:19 +05:30
a5073bcca9
gen-arm: write vtbl{1,2,3,4} in terms of vqtbl
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Writing these intrinsics in terms of the `vqtbl_$ty` functions rather
than the `vqtbl` helper function preserves the behaviour while making
them work in big endian.
2026-05-08 01:16:18 +05:30
1e13d52faf
gen-arm: change defn of vabdl_high_u{8,16,32}
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Changes the definition of `vabdl_high_u{8,16,32}` to match that of
`vabdl_high_s{8,16,32}` so that the `big_endian_inverse` transformation
can apply.
2026-05-08 01:16:18 +05:30
11fd314918
loongarch: Use intrinsics::simd for vbit{clr,rev,set}
2026-05-07 22:34:29 +08:00
1c2d423713
core_arch: remove redundant tests
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Manually written tests for `vcopy_laneq`, `vget{,q}_{high,low,lane}`,
`vcombine` and `vaddw_high` don't account for the expected differences
in output for big endian intrinsics and given that they duplicate the
testing of `intrinsic-test`, can be removed.
2026-05-07 11:15:14 +01:00
4661e734dc
gen-arm: port vcombine_f64 to generator
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This enables the `big_endian_inverse` transform to apply to this
intrinsic.
2026-05-07 11:15:13 +01:00
fe3e89d2d5
gen-arm: port vgetq_lane_f64 to generator
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This enables the `big_endian_inverse` transform to apply to this
intrinsic.
2026-05-07 11:15:06 +01:00
54b56a3d95
gen-arm: port vget_{high,low}_{p,f}64 to generator
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This enables the `big_endian_inverse` transform to apply to these
intrinsics.
2026-05-07 11:14:54 +01:00
cf3ac4997a
gen-arm: port vcopy_laneq_{f,u,s,p}64 to generator
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This enables the `big_endian_inverse` transformation to apply to these
intrinsics.
2026-05-07 11:14:46 +01:00
WANG Rui