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gen-arm: port vgetq_lane_f64 to generator

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This enables the `big_endian_inverse` transform to apply to this
intrinsic.
This commit is contained in:
David Wood
2026-04-20 14:21:22 +01:00
parent 54b56a3d95
commit fe3e89d2d5
3 changed files with 27 additions and 14 deletions
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library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+11
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@@ -11456,6 +11456,17 @@ pub fn vget_high_f64(a: float64x2_t) -> float64x1_t {
pub fn vget_low_f64(a: float64x2_t) -> float64x1_t {
unsafe { float64x1_t([simd_extract!(a, 0)]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[rustc_legacy_const_generics(1)]
#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
pub fn vgetq_lane_f64<const IMM5: i32>(a: float64x2_t) -> f64 {
static_assert_uimm_bits!(IMM5, 1);
unsafe { simd_extract!(a, IMM5 as u32) }
}
#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
#[doc = "## Safety"]
library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs
-14
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@@ -346,20 +346,6 @@ pub fn vget_lane_f64<const IMM5: i32>(v: float64x1_t) -> f64 {
unsafe { simd_extract!(v, IMM5 as u32) }
}
/// Duplicate vector element to vector or scalar
#[inline]
#[target_feature(enable = "neon")]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop, IMM5 = 0)
)]
pub fn vgetq_lane_f64<const IMM5: i32>(v: float64x2_t) -> f64 {
static_assert_uimm_bits!(IMM5, 1);
unsafe { simd_extract!(v, IMM5 as u32) }
}
/// Vector combine
#[inline]
#[target_feature(enable = "neon")]
library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+16
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@@ -14418,3 +14418,19 @@ intrinsics:
- ['vget_low_f64', 'float64x2_t', 'float64x1_t', 'nop', 'float64x1_t([simd_extract!(a, 0)])']
compose:
- Identifier: ['{type[4]}', UnsafeSymbol]
- name: "vgetq_lane_{type[1]}"
doc: "Duplicate vector element to vector or scalar"
arguments: ["a: {type[0]}"]
return_type: "{type[1]}"
attr:
- *neon-stable
- FnCall: [rustc_legacy_const_generics, ['1']]
assert_instr: [['nop', 'IMM5 = 0']]
safety: safe
static_defs: ["const IMM5: i32"]
types:
- ['float64x2_t', 'f64']
compose:
- FnCall: [static_assert_uimm_bits!, [IMM5, "1"]]
- FnCall: ['simd_extract!', [a, 'IMM5 as u32'], [] , true]