Commit Graph

13171 Commits

Author SHA1 Message Date
Andrew Kelley 4d4bb69d7b glibc: update headers to 2.33
This introduces csky support.
2021-04-04 11:54:47 -07:00
Andrew Kelley b25476bf12 glibc: add support for csky architecture 2021-04-04 11:52:40 -07:00
Andrew Kelley 4bab90512d disable failing stack traces test cases due to LLVM12 changes 2021-04-02 16:33:38 -07:00
Andrew Kelley e2a7c01331 disable failing MIPS tests due to LLVM12 regressions
See #8155
2021-04-02 16:33:07 -07:00
Andrew Kelley 09008125e7 Revert back to the old LLVM PassManager
See #8418

This reverts commit ba1bea2fe8.
This reverts commit 94383d14df.
This reverts commit 0d53a2bff0.
2021-04-02 14:35:45 -07:00
Andrew Kelley ba1bea2fe8 zig_llvm.cpp: remove dead code 2021-04-02 12:10:39 -07:00
Andrew Kelley a0e89c9b46 Merge remote-tracking branch 'origin/master' into llvm12 2021-04-02 12:09:38 -07:00
Min-Yih Hsu 94383d14df llvm new-pm: Add missing pipeline option and Passes
- Enable MergeFunctionsPass in non-debug build.
 - Verify input and output IR when the assertion is turned on.
 - Add AlwaysInlinePass in debug build.
 - Add more comments.
2021-04-02 12:04:49 -07:00
Min-Yih Hsu 0d53a2bff0 llvm new-pm: Port LLVM 11.x-based changes to LLVM 12.x
Now zig will use new PM for optimization by default.
2021-04-02 12:04:49 -07:00
joachimschmidt557 228a1ce3e8 stage2 register_manager: Add unit tests for tryAllocReg and allocReg 2021-04-02 12:01:52 -07:00
joachimschmidt557 4efbcad26d stage2 codegen: Extract register management code into separate file 2021-04-02 12:01:52 -07:00
Andrew Kelley fc9c1b4e4a Merge pull request #8028 from mguaypaq/nosuspend-allow
stage1: allow async and resume inside nosuspend blocks
2021-04-02 11:59:34 -07:00
Mathieu Guay-Paquet f270bef9a4 docs: document the nosuspend keyword (#7972)
* docs: document the nosuspend keyword

* Specify that resuming from suspend is allowed in nosuspend

* Fix the description of the requirements of nosuspend

* Make use of nosuspend in some example code.

This is mainly motivated by the incorrect claim that "there would be
no way to collect the return value of amain, if it were something
other than void".
2021-04-02 14:57:42 -04:00
Loris Cro 354c14d6a2 make visited links readable in the stdlib docs warning bar 2021-04-02 20:22:02 +02:00
Loris Cro 4fef1d2982 added warning banner to stdlib docs 2021-04-02 20:13:55 +02:00
Andrew Kelley d780848ae4 Merge pull request #7792 from zanderxyz/zanderxyz/priority-dequeue
std: Add Priority Dequeue
2021-04-02 10:52:23 -07:00
Woze Parrot 833f258297 put async frame in correct addrspace 2021-04-02 10:39:56 -07:00
Frank Denis 45db0e93a9 Merge pull request #8412 from g-w1/fix-docgen-test-release
docgen: fix typo
2021-04-02 18:40:55 +02:00
jacob gw cdc5921073 docgen: fix typo
zig test test.zig-OReleaseFast -> zig test test.zig -OReleaseFast
2021-04-02 12:08:52 -04:00
Michael Dusan cc435dab2f test: fix io_uring timing test to skip on failure 2021-04-02 07:12:09 -04:00
Andrew Kelley 8ebfdc14f6 stage2: implement structs in the frontend
New ZIR instructions:
 * struct_decl_packed
 * struct_decl_extern

New TZIR instruction: struct_field_ptr

Introduce `Module.Struct`. It uses `Value` to store default values and
abi alignments.

Implemented Sema.analyzeStructFieldPtr and zirStructDecl.

Some stuff I changed from `@panic("TODO")` to `log.warn("TODO")`.
It's becoming more clear that we need the lazy value mechanism soon;
Type is becoming unruly, and some of these functions have too much logic
given that they don't have any context for memory management or error
reporting.
2021-04-01 22:39:09 -07:00
Andrew Kelley c66b48194f stage2: AstGen and ZIR printing for struct decls 2021-04-01 19:27:17 -07:00
Andrew Kelley 09000c3f77 zig cc: copy .pdb files from zig-cache/ when appropriate
closes #8407
2021-04-01 16:33:29 -07:00
Andrew Kelley 50bcfb8c90 stage2: implement struct init syntax with ptr result loc 2021-04-01 11:58:55 -07:00
lithdew 59035ae3e9 os: handle ECONNRESET for connect() syscall 2021-04-01 14:18:49 +02:00
Andrew Kelley 070a28e493 Merge pull request #8266 from ziglang/zir-memory-layout
rework ZIR memory layout; overhaul source locations
2021-03-31 23:11:15 -07:00
Andrew Kelley c9e31febf8 stage2: finish implementation of LazySrcLoc 2021-03-31 23:00:00 -07:00
Andrew Kelley b27d052676 stage2: finish source location reworkings in the branch
* remove the LazySrcLoc.todo tag
 * finish updating Sema and AstGen, remove the last of the
   `@panic("TODO")`.
2021-03-31 21:36:32 -07:00
Andrew Kelley e8143f6cbe stage2: compile error for duplicate switch value on sparse 2021-03-31 18:39:34 -07:00
Andrew Kelley cec766f73c stage2: compile error for duplicate switch value on boolean 2021-03-31 18:30:23 -07:00
jacob gw fedc9ebd26 stage2: cbe: restore all previously passing tests! 2021-03-31 18:09:45 -07:00
Andrew Kelley 3cebaaad1c astgen: improved handling of coercion
GenZir struct now has rl_ty_inst field which tracks the result location
type (if any) a block expects all of its results to be coerced to.

Remove a redundant coercion on const local initialization with a
specified type.

Switch expressions, during elision of store_to_block_ptr instructions,
now re-purpose them to be type coercion when the block has a type in the
result location.
2021-03-31 18:05:37 -07:00
Andrew Kelley 08eedc962d Sema: fix else case code generation for switch 2021-03-31 16:17:47 -07:00
Andrew Kelley abd06d8eab stage2: clean up RangeSet and fix swapped Sema switch logic for lhs/rhs 2021-03-31 15:39:04 -07:00
Andrew Kelley e272c29c16 Sema: implement switch validation for ranges 2021-03-31 15:06:03 -07:00
joachimschmidt557 1b657e6e41 stage2 codegen: Make sure function return value is in a callee
preserved register
2021-03-31 23:27:50 +02:00
joachimschmidt557 e088a17f56 stage2 AArch64: implement strb and strh 2021-03-31 23:26:49 +02:00
Andrew Kelley c7b09be8de AstGen: improve switch expressions
* use the proper result location strategy even when there are noreturn
   prongs in the switch expression
 * when using break_operand strategy, actually omit the
   store_to_block_ptr instructions rather than eliding them.
 * for both strategies, properly handle noreturn prongs.
2021-03-31 12:37:20 -07:00
Andrew Kelley 549af582e7 AstGen: switch expressions properly handle result locations 2021-03-30 23:57:22 -07:00
Andrew Kelley 2a1dd174cd stage2: rework AstGen for switch expressions
The switch_br ZIR instructions are now switch_block instructions. This
avoids a pointless block always surrounding a switchbr in emitted ZIR
code.

Introduce typeof_elem ZIR instruction for getting the type of the
element of a pointer value in 1 instruction.

Change typeof to be un_node, not un_tok.

Introduce switch_capture ZIR instructions for obtaining the capture
value of switch prongs.

Introduce Sema.resolveBody for when you want to extract a *Inst out of a
block and you know that there is only going to be 1 break from it.

What's not working yet: AstGen does not correctly elide
store instructions when it turns out that the result location does not
need to be used as a pointer.

Also Sema validation code for duplicate switch items is not yet
implemented.
2021-03-30 21:28:36 -07:00
Andrew Kelley 195ddab2be Sema: implement switch expressions
The logic for putting ranges into the else prong is moved from AstGen to
Sema. However, logic to emit multi-items the same as single-items cannot
be done until TZIR supports mapping multiple items to the same block of
code. This will be simple to represent when we do the upcoming TZIR memory
layout changes.

Not yet implemented in this commit is the validation of duplicate
values. The trick is going to be emitting error messages with accurate
source locations, without adding extra source nodes to the ZIR
switch instruction.

This will be done by computing the respective AST node based on the
switch node (which we do have available), only when a compile error
occurs and we need to know the source location to attach the message to.
2021-03-29 21:59:08 -07:00
Matthew Borkowski 501b4aff99 Add tests for the fill functions of the Isaac64, Pcg, Sfc64, and Xoroshiro128 PRNGs 2021-03-29 09:22:06 +02:00
Matthew Borkowski a5cc5f7854 Fix typo in Pcg.zig's fill function
When filling the last (len % 4) bytes of a buffer, the random number n was only being shifted right by 4 bits for each byte instead of 8. A random u16, for example, would always have its middle two nybbles be equal when generated this way. For comparison, Isaac64.zig, Sfc64.zig, and Xoroshiro128.zig all correctly shift right by 8 bits for each of the last bytes in their nearly identical fill functions.
2021-03-29 09:22:06 +02:00
Andrew Kelley 623d5f442c stage2: guidance on how to implement switch expressions
Here's what I think the ZIR should be. AstGen is not yet implemented to
match this, and the main implementation of analyzeSwitch in Sema is not
yet implemented to match it either.

Here are some example byte size reductions from master branch, with the
ZIR memory layout from this commit:

```
switch (foo) {
  a => 1,
  b => 2,
  c => 3,
  d => 4,
}
```

184 bytes (master) => 40 bytes (this branch)

```
switch (foo) {
  a, b => 1,
  c..d, e, f => 2,
  g => 3,
  else => 4,
}
```

240 bytes (master) => 80 bytes (this branch)
2021-03-28 23:12:26 -07:00
Andrew Kelley b85ef2300f Merge remote-tracking branch 'origin/master' into llvm12 2021-03-28 21:42:56 -07:00
Andrew Kelley 281a7baaea Merge remote-tracking branch 'origin/master' into zir-memory-layout
Wanted to make sure those new test cases still pass.

Also grab that CI fix so we can get those green check marks.
2021-03-28 19:42:43 -07:00
Andrew Kelley 8f469c1127 stage2: fix error sets 2021-03-28 19:40:21 -07:00
jacob gw 0005b34637 stage2: implement sema for @errorToInt and @intToError 2021-03-28 18:22:01 -07:00
Andrew Kelley 175adc0bd7 ci: update msys2 installer 2021-03-28 17:49:28 -07:00
Andrew Kelley bb5cfbcb72 Merge pull request #8305 from jedisct1/base64
std/base64: cleanups & support url-safe and other non-padded variants
2021-03-28 17:11:07 -07:00