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Merge pull request 'add spacemit_x100 + spacemit_x100 RISC-V CPU models; detect more RISC-V CPU models on Linux' (#35392) from alexrp/zig:more-riscv-models into master

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Reviewed-on: https://codeberg.org/ziglang/zig/pulls/35392
This commit is contained in:
Alex Rønne Petersen
2026-05-23 05:43:47 +02:00
parent 3140b375fc d70b56429c
commit 9e3eaa6be7
3 changed files with 198 additions and 0 deletions
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lib/std/Target/riscv.zig
+97
View File
@@ -3370,6 +3370,103 @@ pub const cpu = struct {
.zvl1024b,
}),
};
pub const spacemit_a100: CpuModel = .{
.name = "spacemit_a100",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.b,
.c,
.dlen_factor_2,
.i,
.m,
.optimized_nf2_segment_load_store,
.optimized_nf3_segment_load_store,
.optimized_nf4_segment_load_store,
.smepmp,
.smnpm,
.smstateen,
.ssccptr,
.sscofpmf,
.sscounterenw,
.ssnpm,
.sspm,
.sstc,
.sstvala,
.sstvecd,
.ssu64xl,
.supm,
.svade,
.svbare,
.svinval,
.svnapot,
.svpbmt,
.unaligned_scalar_mem,
.v,
.vxrm_pipeline_flush,
.za64rs,
.zawrs,
.zbc,
.zbkc,
.zcb,
.zcmop,
.zfa,
.zfh,
.zic64b,
.zicbom,
.zicbop,
.zicboz,
.ziccamoa,
.ziccif,
.zicclsm,
.ziccrse,
.zicntr,
.zicond,
.zifencei,
.zihintntl,
.zihintpause,
.zihpm,
.zimop,
.zkt,
.zvbb,
.zvfbfwma,
.zvfh,
.zvkng,
.zvknha,
.zvksc,
.zvksg,
.zvl1024b,
}),
};
pub const spacemit_x100: CpuModel = .{
.name = "spacemit_x100",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.dlen_factor_2,
.optimized_nf2_segment_load_store,
.optimized_nf3_segment_load_store,
.optimized_nf4_segment_load_store,
.rva23s64,
.smepmp,
.smnpm,
.smstateen,
.sspm,
.unaligned_scalar_mem,
.vxrm_pipeline_flush,
.xsmtvdot,
.zbc,
.zbkc,
.zfh,
.zvfbfwma,
.zvfh,
.zvkng,
.zvknha,
.zvksc,
.zvksg,
.zvl256b,
}),
};
pub const spacemit_x60: CpuModel = .{
.name = "spacemit_x60",
.llvm_name = "spacemit-x60",
lib/std/zig/system/linux.zig
+4
View File
@@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct {
model: ?*const Target.Cpu.Model = null,
const cpu_names = .{
.{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
.{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
.{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
.{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
.{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
.{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
.{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
.{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
.{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
.{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 },
};
fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
tools/update_cpu_features.zig
+97
View File
@@ -1548,6 +1548,103 @@ const targets = [_]ArchTarget{
.zig_name = "baseline_rv64",
.features = &.{ "64bit", "a", "c", "d", "f", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "spacemit_a100",
.features = &.{
"64bit",
"a",
"b",
"c",
"dlen_factor_2",
"i",
"m",
"optimized_nf2_segment_load_store",
"optimized_nf3_segment_load_store",
"optimized_nf4_segment_load_store",
"smepmp",
"smnpm",
"smstateen",
"ssccptr",
"sscofpmf",
"sscounterenw",
"ssnpm",
"sspm",
"sstc",
"sstvala",
"sstvecd",
"ssu64xl",
"supm",
"svade",
"svbare",
"svinval",
"svnapot",
"svpbmt",
"unaligned_scalar_mem",
"v",
"vxrm_pipeline_flush",
"za64rs",
"zawrs",
"zbc",
"zbkc",
"zcb",
"zcmop",
"zfa",
"zfh",
"zic64b",
"zicbom",
"zicbop",
"zicboz",
"ziccamoa",
"ziccif",
"zicclsm",
"ziccrse",
"zicntr",
"zicond",
"zifencei",
"zihintntl",
"zihintpause",
"zihpm",
"zimop",
"zkt",
"zvbb",
"zvfbfwma",
"zvfh",
"zvkng",
"zvknha",
"zvksc",
"zvksg",
"zvl1024b",
},
},
.{
.llvm_name = null,
.zig_name = "spacemit_x100",
.features = &.{
"dlen_factor_2",
"optimized_nf2_segment_load_store",
"optimized_nf3_segment_load_store",
"optimized_nf4_segment_load_store",
"rva23s64",
"smepmp",
"smnpm",
"smstateen",
"sspm",
"unaligned_scalar_mem",
"vxrm_pipeline_flush",
"xsmtvdot",
"zbc",
"zbkc",
"zfh",
"zvfbfwma",
"zvfh",
"zvkng",
"zvknha",
"zvksc",
"zvksg",
"zvl256b",
},
},
},
},
.{