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libc: update NetBSD headers to 11.0

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This commit is contained in:
Alex Rønne Petersen
2026-05-26 13:40:20 +02:00
parent 0511b3cc9b
commit 1e2bac6153
697 changed files with 34642 additions and 20475 deletions
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lib/libc/include/aarch64-netbsd-none/aarch64/armreg.h
Vendored
+259 -22
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@@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.63 2022/12/01 00:32:52 ryo Exp $ */
/* $NetBSD: armreg.h,v 1.67 2025/02/27 08:39:54 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -229,7 +229,13 @@ AARCH64REG_READ_INLINE(clidr_el1)
#define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
#define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
AARCH64REG_READ_INLINE(contextidr_el1)
AARCH64REG_WRITE_INLINE(contextidr_el1)
AARCH64REG_READ_INLINE(currentel)
#define CURRENTEL_EL __BITS(3,2) // Current exception Level
AARCH64REG_READ_INLINE(id_aa64afr0_el1)
AARCH64REG_READ_INLINE(id_aa64afr1_el1)
AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
@@ -619,7 +625,7 @@ AARCH64REG_WRITE_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
AARCH64REG_READ_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
AARCH64REG_WRITE_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Register
AARCH64REG_WRITE_INLINE(cpacr_el1)
#define CPACR_TTA __BIT(28) // System Register Access Traps
@@ -661,6 +667,8 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
#define ESR_EC_PAUTH 0x09 // A64: Pointer auth trap (FEAT_PAUTH)
#define ESR_EC_LS64 0x0a // AXX: LD64B/ST64B instruction (FEAT_LS64) // XXXNH
#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
#define ESR_EC_BTE_A64 0x0d // A64: Branch Target Exception (V8.5)
#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
@@ -671,29 +679,54 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
#define ESR_EC_SVE 0x19 // AXX: SVE Instruction Execution (FEAT_SVE)
#define ESR_EC_PAUTH_ERET 0x1a // A64: ERET/ERETAA/ERETAB (FEAT_PAUTH and FEAT_NV)
#define ESR_EC_TME 0x1b // A64: TSTART instruction (FEAT_TME)
#define ESR_EC_FRAC 0x1c // A64: Pointer auth trap (FEAT_FPAC)
#define ESR_EC_SME 0x1d // AXX: Access to SME (FEAT_SME)
#define ESR_EC_RME 0x1e // A64: Granule Protection Check (FEAT_RME)
#define ESR_EC_INSN_ABT_EL_LOW 0x20 // AXX: Instruction Abort from lower level
#define ESR_EC_INSN_ABT_EL_CUR 0x21 // AXX: Instruction Abort from current level
#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
#define ESR_EC_DATA_ABT_EL_LOW 0x24 // AXX: Data Abort from lower level
#define ESR_EC_DATA_ABT_EL_CUR 0x25 // AXX: Data Abort from current level
#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
#define ESR_EC_MOPS 0x27 // A64: Memory Operation Exception (FEAT_MOPS)
#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
#define ESR_EC_BRKPNT_EL_LOW 0x30 // AXX: Breakpoint Exception from lower level
#define ESR_EC_BRKPNT_EL_CUR 0x31 // AXX: Breakpoint Exception from current level
#define ESR_EC_SW_STEP_EL_LOW 0x32 // AXX: Software Step from lower level
#define ESR_EC_SW_STEP_EL_CUR 0x33 // AXX: Software Step from current level
#define ESR_EC_WTCHPNT_EL_LOW 0x34 // AXX: Watchpoint from lower level
#define ESR_EC_WTCHPNT_EL_CUR 0x35 // AXX: Watchpoint from current level
#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
/* alias for EL1 kernel */
#define ESR_EC_INSN_ABT_EL0 ESR_EC_INSN_ABT_EL_LOW
#define ESR_EC_INSN_ABT_EL1 ESR_EC_INSN_ABT_EL_CUR
#define ESR_EC_DATA_ABT_EL0 ESR_EC_DATA_ABT_EL_LOW
#define ESR_EC_DATA_ABT_EL1 ESR_EC_DATA_ABT_EL_CUR
#define ESR_EC_BRKPNT_EL0 ESR_EC_BRKPNT_EL_LOW
#define ESR_EC_BRKPNT_EL1 ESR_EC_BRKPNT_EL_CUR
#define ESR_EC_SW_STEP_EL0 ESR_EC_SW_STEP_EL_LOW
#define ESR_EC_SW_STEP_EL1 ESR_EC_SW_STEP_EL_CUR
#define ESR_EC_WTCHPNT_EL0 ESR_EC_WTCHPNT_EL_LOW
#define ESR_EC_WTCHPNT_EL1 ESR_EC_WTCHPNT_EL_CUR
#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
#define ESR_ISS_CV __BIT(24) // common
#define ESR_ISS_COND __BITS(23,20) // common
#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
#define ESR_ISS_SYSREG_OP0 __BITS(21,20) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_OP2 __BITS(19,17) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_OP1 __BITS(16,14) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_CRN __BITS(13,10) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_RT __BITS(9,5) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_CRM __BITS(4,1) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_DIRECTION __BIT(0) // for ESR_EC_SYS_REG
#define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT
#define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT
#define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT
@@ -713,7 +746,7 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SRT __BITS(20,16) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
@@ -758,6 +791,101 @@ AARCH64REG_WRITE_INLINE(esr_el1)
AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
AARCH64REG_WRITE_INLINE(far_el1)
AARCH64REG_READ_INLINE(far_el2)
AARCH64REG_WRITE_INLINE(far_el2)
AARCH64REG_READ_INLINE(hcr_el2) // Hypervisor Configuration Register
AARCH64REG_WRITE_INLINE(hcr_el2)
#define HCR_EL2_TWEDEL __BITS(63,60) // TWE Delay (FEAT_TWED)
#define HCR_EL2_TWEDEN __BIT(59) // TWE Delay Enable (FEAT_TWED)
#define HCR_EL2_TID5 __BIT(58) // Trap ID group 5 (FEAT_MTE2)
#define HCR_EL2_DCT __BIT(57) // Default Cacheability Tagging (FEAT_MTE2)
#define HCR_EL2_ATA __BIT(56) // Allocation Tag Access (FEAT_MTE2)
#define HCR_EL2_TTLBOS __BIT(55) // Trap TLB maintenance OS (FEAT_EVT)
#define HCR_EL2_TTLBIS __BIT(54) // Trap TLB maintenance IS (FEAT_EVT)
#define HCR_EL2_ENSCXT __BIT(53) // Enable SCXTNUM_EL[01] access (FEAT_CSV2)
#define HCR_EL2_TOCU __BIT(52) // Trap PoU cache maintenance
#define HCR_EL2_AMVOFFEN __BIT(51) // Activity Monitors Virtual Offsets Enable (FEAT_AMUv1p1)
#define HCR_EL2_TICAB __BIT(50) // Trap IC all broadcast maintenance.
#define HCR_EL2_TID4 __BIT(49) // Trap ID group 4 (FEAT_EVT)
#define HCR_EL2_GPF __BIT(48) // Granule Protection Faults (FEAT_RME)
#define HCR_EL2_FIEN __BIT(47) // Fault Injection Enable (FEAT_RASv1p1)
#define HCR_EL2_FWB __BIT(46) // Forced Write-Back (FEAT_S2FWB)
#define HCR_EL2_NV2 __BIT(45) // Nested Virtualization (FEAT_NV2)
#define HCR_EL2_AT __BIT(44) // Address Translation (FEAT_NV)
#define HCR_EL2_NV1 __BIT(43) // Nested Virtualization (FEAT_NV2/FEAT_NV)
#define HCR_EL2_NV __BIT(42) // Nested Virtualization (FEAT_NV2/FEAT_NV)
#define HCR_EL2_API __BIT(41) // Pointer Authentication instruction (FEAT_PAuth)
#define HCR_EL2_APK __BIT(40) // Pointer Authentication key (FEAT_PAuth)
#define HCR_EL2_TME __BIT(39) // TME enable (FEAT_TME)
#define HCR_EL2_MIOCNCE __BIT(38) // Mismatched Inner/Outer Cacheable Non-Coherency Enable,
#define HCR_EL2_TEA __BIT(37) // Route synchronous External abort exceptions to EL2 (FEAT_RAS)
#define HCR_EL2_TERR __BIT(36) // Trap accesses of Error Record registers (FEAT_RAS)
#define HCR_EL2_TLOR __BIT(35) // Trap LOR registers (FEAT_LOR)
#define HCR_EL2_VHE __BIT(34) // EL2 Host (FEAT_VHE)
#define HCR_EL2_ID __BIT(33) // stage2 IC disable
#define HCR_EL2_CD __BIT(32) // stage2 DC disable
#define HCR_EL2_RW __BIT(31) // register width
#define HCR_EL2_TRVM __BIT(30) // trap VM control regs read
#define HCR_EL2_HCD __BIT(29) // HVC disable
#define HCR_EL2_TDZ __BIT(28) // trap DC ZVA
#define HCR_EL2_TGE __BIT(27) // trap general exceptions
#define HCR_EL2_TVM __BIT(26) // trap VM control regs write
#define HCR_EL2_TTLB __BIT(25) // trap TLB maintenance op
#define HCR_EL2_TPU __BIT(24) // trap IC {IVAU,IALLU,IALLUIS},DC CVAU
#define HCR_EL2_TPC __BIT(23) // trap DC {IVAC,CIVAC,CVAC}
#define HCR_EL2_TSW __BIT(22) // trap DC {ISW,CSW,CISW}
#define HCR_EL2_TACR __BIT(21) // trap ACTRL_EL1 access
#define HCR_EL2_TIDCP __BIT(20) // trap IMPLEMENTATION DEFINED system regs
#define HCR_EL2_TSC __BIT(19) // trap SMC
#define HCR_EL2_TID3 __BIT(18) // trap ID group3 regs
#define HCR_EL2_TID2 __BIT(17) // trap ID group2 regs
#define HCR_EL2_TID1 __BIT(16) // trap ID group1 regs
#define HCR_EL2_TID0 __BIT(15) // trap ID group0 regs
#define HCR_EL2_TWE __BIT(14) // trap WFE
#define HCR_EL2_TWI __BIT(13) // trap WFI
#define HCR_EL2_DC __BIT(12) // default cacheablility
#define HCR_EL2_BSU __BITS(11,10) // barrier shareability upgrade
#define HCR_EL2_FB __BIT(9) // force broadcast TLBI and IC
#define HCR_EL2_VSE __BIT(8) // inject Virtual SError
#define HCR_EL2_VI __BIT(7) // inject Virtual IRQ
#define HCR_EL2_VF __BIT(6) // inject Virtual FIQ
#define HCR_EL2_AMO __BIT(5) // trap SError/AsyncAbort
#define HCR_EL2_IMO __BIT(4) // trap IRQ
#define HCR_EL2_FMO __BIT(3) // trap FIQ
#define HCR_EL2_PTW __BIT(2) // Protect table walk
#define HCR_EL2_SWIO __BIT(1) // override DC ISW to DC CISW
#define HCR_EL2_VM __BIT(0) // enable stage2 translation
AARCH64REG_READ_INLINE(hpfar_el2) // Hypervisor IPA Fault Address Register
AARCH64REG_WRITE_INLINE(hpfar_el2)
#define HPFAR_EL2_NS __BIT(63) // Faulting IPA address space (FEAT_SEL2)
#define HPFAR_EL2_FIPA_D128 __BITS(47,4) // Faulting Intermediate Physical Address Bits [55:12]
#define HPFAR_EL2_FIPA __BITS(43,4) // Faulting Intermediate Physical Address Bits [51:12]
#define HPFAR_EL2_FIPA_BITSHIFT 12
AARCH64REG_READ_INLINE(hstr_el2) // Hypervisor System Trap Register
AARCH64REG_WRITE_INLINE(hstr_el2)
#define HSTR_EL2_T15 __BIT(15)
// __BIT(14) Res0
#define HSTR_EL2_T13 __BIT(13)
#define HSTR_EL2_T12 __BIT(12)
#define HSTR_EL2_T11 __BIT(11)
#define HSTR_EL2_T10 __BIT(10)
#define HSTR_EL2_T9 __BIT(9)
#define HSTR_EL2_T8 __BIT(8)
#define HSTR_EL2_T7 __BIT(7)
#define HSTR_EL2_T6 __BIT(6)
#define HSTR_EL2_T5 __BIT(5)
// __BIT(4) Res0
#define HSTR_EL2_T3 __BIT(3)
#define HSTR_EL2_T2 __BIT(2)
#define HSTR_EL2_T1 __BIT(1)
#define HSTR_EL2_T0 __BIT(0)
AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
@@ -770,6 +898,12 @@ AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
AARCH64REG_WRITE_INLINE(mair_el1)
AARCH64REG_READ_INLINE(mair_el2)
AARCH64REG_WRITE_INLINE(mair_el2)
AARCH64REG_READ_INLINE(amair_el1) // Auxiliary MAIR
AARCH64REG_WRITE_INLINE(amair_el1)
AARCH64REG_READ_INLINE(amair_el2)
AARCH64REG_WRITE_INLINE(amair_el2)
#define MAIR_ATTR0 __BITS(7,0)
#define MAIR_ATTR1 __BITS(15,8)
@@ -791,6 +925,7 @@ AARCH64REG_WRITE_INLINE(par_el1)
#define PAR_ATTR __BITS(63,56) // F=0 memory attributes
#define PAR_PA __BITS(51,12) // F=0 physical address
#define PAR_PA_SHIFT 12
#define PAR_PA_LOWMASK __BITS(11,0)
#define PAR_NS __BIT(9) // F=0 non-secure
#define PAR_SH __BITS(8,7) // F=0 shareability attribute
#define PAR_SH_NONE 0
@@ -808,13 +943,19 @@ AARCH64REG_WRITE_INLINE(rmr_el1)
AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
AARCH64REG_WRITE_INLINE(rvbar_el1)
AARCH64REG_ATWRITE_INLINE(s1e0r); // Address Translate Stages 1
AARCH64REG_ATWRITE_INLINE(s1e0w);
AARCH64REG_ATWRITE_INLINE(s1e1r);
AARCH64REG_ATWRITE_INLINE(s1e1w);
AARCH64REG_ATWRITE_INLINE(s1e0r) // Address Translate Stages 1 EL0
AARCH64REG_ATWRITE_INLINE(s1e0w)
AARCH64REG_ATWRITE_INLINE(s1e1r) // Address Translate Stages 1 EL1
AARCH64REG_ATWRITE_INLINE(s1e1w)
AARCH64REG_ATWRITE_INLINE(s12e0r) // Address Translate Stages 1 and 2 EL0
AARCH64REG_ATWRITE_INLINE(s12e0w)
AARCH64REG_ATWRITE_INLINE(s12e1r) // Address Translate Stages 1 and 2 EL1
AARCH64REG_ATWRITE_INLINE(s12e1w)
AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
AARCH64REG_WRITE_INLINE(sctlr_el1)
AARCH64REG_READ_INLINE(sctlr_el2)
AARCH64REG_WRITE_INLINE(sctlr_el2)
#define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
#define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
@@ -869,6 +1010,8 @@ reg_sp_read(void)
AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer
AARCH64REG_WRITE_INLINE(sp_el0)
AARCH64REG_READ_INLINE(sp_el1) // EL1 Stack Pointer
AARCH64REG_WRITE_INLINE(sp_el1)
AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
AARCH64REG_WRITE_INLINE(spsel)
@@ -921,10 +1064,12 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
#define SPSR_M_FIQ32 0x11
#define SPSR_M_USR32 0x10
#define SPSR_USER_P(spsr) (((spsr) & (SPSR_M & ~SPSR_A32)) == 0)
#define SPSR_PRIVILEGED_P(spsr) (!SPSR_USER_P((spsr)))
AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
AARCH64REG_WRITE_INLINE(tcr_el1)
/* TCR_EL1 - Translation Control Register */
#define TCR_TCMA1 __BIT(58) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b11111 */
#define TCR_TCMA0 __BIT(57) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b00000 */
@@ -999,15 +1144,60 @@ AARCH64REG_WRITE_INLINE(tcr_el1)
#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
AARCH64REG_READ_INLINE(tcr_el2) // Translation Control Register EL2
AARCH64REG_WRITE_INLINE(tcr_el2)
/* TCR_EL2 - Translation Control Register */
// __BITS(63, 34) // Res0
#define TCR_EL2_MTX __BIT(33) // Extended memory tag checking
#define TCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
// __BIT(31) // Res1
#define TCR_EL2_TCMA __BIT(30) // Unchecked accesses control (FEAT_MTE2)
#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction address matching (FEAT_PAuth)
#define TCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
#define TCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
#define TCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
#define TCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
#define TCR_EL2_HPD __BIT(24) // Hierarchical Permission Disables (FEAT_HPDS)
// __BIT(23) // Res1
#define TCR_EL2_HD __BIT(22) // Hardware management of dirty state (FEAT_HAFDBS)
#define TCR_EL2_HA __BIT(21) // Hardware Access flag update (FEAT_HAFDBS)
#define TCR_EL2_TBI __BIT(20) // Top Byte Ignored
// __BIT(19) // Res1
#define TCR_EL2_PS __BITS(18,16) // Physical Address Size
#define TCR_EL2_TG0 __BITS(15,14) // TTBR0_EL2 Granule size
#define TCR_EL2_TG0_4KB __SHIFTIN(0,TCR_EL2_TG0) // 4KB page size
#define TCR_EL2_TG0_64KB __SHIFTIN(1,TCR_EL2_TG0) // 64KB page size
#define TCR_EL2_TG0_16KB __SHIFTIN(2,TCR_EL2_TG0) // 16KB page size
#define TCR_EL2_SH0 __BITS(13,12) // TTBR0_EL2 Shareability attribute
#define TCR_EL2_SH0_NONE __SHIFTIN(0,TCR_EL2_SH0) // non-shareable
#define TCR_EL2_SH0_OUTER __SHIFTIN(2,TCR_EL2_SH0) // Outer shareable
#define TCR_EL2_SH0_INNER __SHIFTIN(3,TCR_EL2_SH0) // Inner shareable
#define TCR_EL2_ORGN0 __BITS(11,10) // TTBR0_EL2 Outer cacheability attribute
#define TCR_EL2_ORGN0_NC __SHIFTIN(0,TCR_EL2_ORGN0) // Non Cacheable
#define TCR_EL2_ORGN0_WB_WA __SHIFTIN(1,TCR_EL2_ORGN0) // WriteBack WriteAllocate
#define TCR_EL2_ORGN0_WT __SHIFTIN(2,TCR_EL2_ORGN0) // WriteThrough
#define TCR_EL2_ORGN0_WB __SHIFTIN(3,TCR_EL2_ORGN0) // WriteBack
#define TCR_EL2_IRGN0 __BITS(9,8) // TTBR0_EL2 Inner cacheability attribute
#define TCR_EL2_IRGN0_NC __SHIFTIN(0,TCR_EL2_IRGN0) // Non Cacheable
#define TCR_EL2_IRGN0_WB_WA __SHIFTIN(1,TCR_EL2_IRGN0) // WriteBack WriteAllocate
#define TCR_EL2_IRGN0_WT __SHIFTIN(2,TCR_EL2_IRGN0) // WriteThrough
#define TCR_EL2_IRGN0_WB __SHIFTIN(3,TCR_EL2_IRGN0) // WriteBack
#define TCR_EL2_T0SZ __BITS(5,0) // TTBR0_EL2 Size offset
AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
AARCH64REG_WRITE_INLINE(tpidr_el1)
AARCH64REG_READ_INLINE(tpidr_el2) // Thread ID Register (EL2)
AARCH64REG_WRITE_INLINE(tpidr_el2)
AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
AARCH64REG_WRITE_INLINE(ttbr0_el1)
AARCH64REG_READ_INLINE(ttbr0_el2) // Translation Table Base Register 0 EL2
AARCH64REG_WRITE_INLINE(ttbr0_el2)
AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
AARCH64REG_WRITE_INLINE(ttbr1_el1)
#define TTBR_ASID __BITS(63,48)
@@ -1015,6 +1205,53 @@ AARCH64REG_WRITE_INLINE(ttbr1_el1)
AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
AARCH64REG_WRITE_INLINE(vbar_el1)
AARCH64REG_READ_INLINE(vbar_el2)
AARCH64REG_WRITE_INLINE(vbar_el2)
AARCH64REG_READ_INLINE(vpidr_el2) // Virtualization Processor ID Register
AARCH64REG_WRITE_INLINE(vpidr_el2)
AARCH64REG_READ_INLINE(vmpidr_el2) // Virtualization Multiprocessor ID Register
AARCH64REG_WRITE_INLINE(vmpidr_el2)
AARCH64REG_READ_INLINE(vtcr_el2) // Virtualization Translation Control Register
AARCH64REG_WRITE_INLINE(vtcr_el2)
#define VTCR_EL2_HAFT __BIT(44) // Hardware managed Access Flag (FEAT_HAFT)
// __BITS(43, 42) // Res0
#define VTCR_EL2_TL0 __BIT(41) // TopLevel0 permission attribute control (FEAT_THE)
#define VTCR_EL2_GCSH __BIT(40) // Assured translations for guarded control stacks (FEAT_THE+FEAT_GCS)
// __BIT(39) // Res0
#define VTCR_EL2_D128 __BIT(38) // VMSAv9-128 (FEAT_D128)
#define VTCR_EL2_S2POE __BIT(37) // Enable stage 2 Permission Overlay (FEAT_S2POE)
#define VTCR_EL2_S2PIE __BIT(36) // Select Permission Model. (FEAT_S2PIE)
#define VTCR_EL2_TL1 __BIT(35) // TopLevel1 permission attribute control (FEAT_THE)
#define VTCR_EL2_AO __BIT(34) // AssuredOnly attribute enable (FEAT_THE)
#define VTCR_EL2_SL2 __BIT(33) // Stage 2 starting level (FEAT_LPA2)
#define VTCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
// __BIT(31) // Res1
#define VTCR_EL2_NSA __BIT(30) // Non-secure S2 translation output address space (FEAT_SEL2)
#define VTCR_EL2_NSW __BIT(29) // Non-secure S2 translation table address space (FEAT_SEL2)
#define VTCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
#define VTCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
#define VTCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
#define VTCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
// __BITS(24, 23) // Res0
#define VTCR_EL2_HD __BIT(22) // Hardware Dirty state management (FEAT_HAFDBS)
#define VTCR_EL2_HA __BIT(21) // Hardware Access flag management (FEAT_HAFDBS)
#define VTCR_EL2_VS __BIT(19) // VMID size (FEAT_VMID16)
#define VTCR_EL2_PS __BITS(18,16) // Physical address Size
#define VTCR_EL2_TG0 __BITS(15,14) // VTTBR_EL2 Granule size
#define VTCR_EL2_SH0 __BITS(13,12) // V{,S}TTBR_EL2 shareability attribute
#define VTCR_EL2_ORGN0 __BITS(11,10) // V{,S}TTBR_EL2 outer cacheability
#define VTCR_EL2_IRGN0 __BITS(9,8) // V{,S}TTBR_EL2 inner cacheability
#define VTCR_EL2_SL0 __BITS(7,6) // Start Level of S2 translation lookup.
#define VTCR_EL2_T0SZ __BITS(5,0) // VTTBR_EL2 Size offset
AARCH64REG_READ_INLINE(vttbr_el2) // Virtualization Translation Table Base Register
AARCH64REG_WRITE_INLINE(vttbr_el2)
#define VTTBR_VIMD __BITS(55,48)
#define VTTBR_BADDR __BITS(47,0)
/*
* From here on, these are DEBUG registers
lib/libc/include/aarch64-netbsd-none/aarch64/byte_swap.h
Vendored
+3 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.4 2017/01/17 11:09:36 rin Exp $ */
/* $NetBSD: byte_swap.h,v 1.4.52.1 2025/12/18 19:57:53 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,7 +46,8 @@
#else
#ifdef __GNUC__
#include <sys/types.h>
#include <sys/stdint.h>
__BEGIN_DECLS
#define __BYTE_SWAP_U64_VARIABLE __byte_swap_u64_variable
lib/libc/include/aarch64-netbsd-none/aarch64/cpu.h
Vendored
+26 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.48.2.1 2024/10/13 10:43:11 martin Exp $ */
/* $NetBSD: cpu.h,v 1.53 2024/12/30 19:17:21 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -99,6 +99,21 @@ struct aarch64_cache_info {
struct aarch64_cache_unit dcache;
};
struct aarch64_low_power_idle {
uint32_t min_res; /* minimum residency */
uint32_t wakeup_latency; /* worst case */
uint32_t save_restore_flags;
#define LPI_SAVE_RESTORE_CORE __BIT(0)
#define LPI_SAVE_RESTORE_TRACE __BIT(1)
#define LPI_SAVE_RESTORE_GICR __BIT(2)
#define LPI_SAVE_RESTORE_GICD __BIT(3)
uint32_t reg_addr;
#define LPI_REG_ADDR_WFI 0xffffffff
char *name;
struct evcnt events;
};
struct cpu_info {
struct cpu_data ci_data;
device_t ci_dev;
@@ -166,12 +181,18 @@ struct cpu_info {
/* ACPI */
uint32_t ci_acpiid; /* ACPI Processor Unique ID */
/* ACPI low power idle */
uint32_t ci_nlpi;
struct aarch64_low_power_idle *ci_lpi;
uint64_t ci_last_idle;
/* cached system registers */
uint64_t ci_sctlr_el1;
uint64_t ci_sctlr_el2;
/* sysctl(9) exposed system registers */
struct aarch64_sysctl_cpu_id ci_id;
#define ci_midr ci_id.ac_midr
/* cache information and function pointers */
struct aarch64_cache_info ci_cacheinfo[MAX_CACHE_LEVEL];
@@ -243,10 +264,14 @@ static inline void
cpu_dosoftints(void)
{
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
KDASSERT(kpreempt_disabled());
cpu_dosoftints_ci(curcpu());
#endif
}
struct cpufeature_attach_args {
struct cpu_info *ci;
};
#endif /* _KERNEL */
lib/libc/include/aarch64-netbsd-none/aarch64/lwp_private.h
Vendored
+3
View File
@@ -0,0 +1,3 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:05 christos Exp $ */
#include <arm/lwp_private.h>
lib/libc/include/aarch64-netbsd-none/aarch64/pmap.h
Vendored
+7 -33
View File
@@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.57 2022/11/03 09:04:56 skrll Exp $ */
/* $NetBSD: pmap.h,v 1.59 2023/08/02 15:57:21 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -59,12 +59,6 @@
/* Maximum number of ASIDs. Some CPUs have less.*/
#define PMAP_TLB_NUM_PIDS 65536
#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
#define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
#if PMAP_TLB_MAX > 1
#define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
#else
#define cpu_tlb_info(ci) (&pmap_tlb0_info)
#endif
static inline tlb_asid_t
pmap_md_tlb_asid_max(void)
@@ -80,6 +74,7 @@ pmap_md_tlb_asid_max(void)
}
#include <uvm/pmap/tlb.h>
#include <uvm/pmap/pmap_devmap.h>
#include <uvm/pmap/pmap_tlb.h>
#define KERNEL_PID 0 /* The kernel uses ASID 0 */
@@ -161,22 +156,6 @@ pmap_kvattr(pt_entry_t *ptep, vm_prot_t prot)
return opte;
}
/* devmap */
struct pmap_devmap {
vaddr_t pd_va; /* virtual address */
paddr_t pd_pa; /* physical address */
psize_t pd_size; /* size of region */
vm_prot_t pd_prot; /* protection code */
u_int pd_flags; /* flags for pmap_kenter_pa() */
};
void pmap_devmap_register(const struct pmap_devmap *);
void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
vaddr_t pmap_devmap_phystov(paddr_t);
paddr_t pmap_devmap_vtophys(paddr_t);
#define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
#define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
#define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
@@ -186,16 +165,7 @@ paddr_t pmap_devmap_vtophys(paddr_t);
#define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x))
#define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x))
#define DEVMAP_ENTRY(va, pa, sz) \
{ \
.pd_va = DEVMAP_ALIGN(va), \
.pd_pa = DEVMAP_ALIGN(pa), \
.pd_size = DEVMAP_SIZE(sz), \
.pd_prot = VM_PROT_READ | VM_PROT_WRITE, \
.pd_flags = PMAP_DEV \
}
#define DEVMAP_ENTRY_END { 0 }
#define DEVMAP_FLAGS PMAP_DEV
/* Hooks for the pool allocator */
paddr_t vtophys(vaddr_t);
@@ -268,6 +238,8 @@ void pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t,
void (*)(const char *, ...) __printflike(1, 2));
int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
#if defined(DDB)
void pmap_db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2));
void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
@@ -415,6 +387,8 @@ void pmap_pv_track(paddr_t, psize_t);
void pmap_pv_untrack(paddr_t, psize_t);
void pmap_pv_protect(paddr_t, vm_prot_t);
vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
#define PMAP_MAPSIZE1 L2_SIZE
/* for ddb */
lib/libc/include/aarch64-netbsd-none/aarch64/sljit_machdep.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: sljit_machdep.h,v 1.3.18.2 2024/05/11 14:08:32 martin Exp $ */
/* $NetBSD: sljit_machdep.h,v 1.5 2024/05/05 15:18:10 riastradh Exp $ */
/*-
* Copyright (c) 2014 Alexander Nasonov.
lib/libc/include/aarch64-netbsd-none/aarch64/vmparam.h
Vendored
+4 -4
View File
@@ -1,4 +1,4 @@
/* $NetBSD: vmparam.h,v 1.19.4.1 2024/07/03 19:13:20 martin Exp $ */
/* $NetBSD: vmparam.h,v 1.21 2024/06/30 09:36:43 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -151,11 +151,11 @@
* last 254MB of kernel vm area (0xfffffffff0000000-0xffffffffffe00000)
* may be used for devmap. see aarch64/pmap.c:pmap_devmap_*
*/
#define VM_KERNEL_IO_ADDRESS 0xfffffffff0000000L
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_ADDRESS)
#define VM_KERNEL_IO_BASE 0xfffffffff0000000L
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_BASE)
#define VM_KERNEL_VM_BASE (0xffffc00040000000L)
#define VM_KERNEL_VM_SIZE (VM_KERNEL_IO_ADDRESS - VM_KERNEL_VM_BASE)
#define VM_KERNEL_VM_SIZE (VM_KERNEL_IO_BASE - VM_KERNEL_VM_BASE)
/* virtual sizes (bytes) for various kernel submaps */
#define USRIOSIZE (PAGE_SIZE / 8)
lib/libc/include/aarch64-netbsd-none/machine/armreg.h
Vendored
+259 -22
View File
@@ -1,4 +1,4 @@
/* $NetBSD: armreg.h,v 1.63 2022/12/01 00:32:52 ryo Exp $ */
/* $NetBSD: armreg.h,v 1.67 2025/02/27 08:39:54 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -229,7 +229,13 @@ AARCH64REG_READ_INLINE(clidr_el1)
#define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
#define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
AARCH64REG_READ_INLINE(contextidr_el1)
AARCH64REG_WRITE_INLINE(contextidr_el1)
AARCH64REG_READ_INLINE(currentel)
#define CURRENTEL_EL __BITS(3,2) // Current exception Level
AARCH64REG_READ_INLINE(id_aa64afr0_el1)
AARCH64REG_READ_INLINE(id_aa64afr1_el1)
AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
@@ -619,7 +625,7 @@ AARCH64REG_WRITE_INLINE3(APGAKeyHi_EL1, apgakeyhi_el1, ATTR_ARCH("armv8.3-a"))
AARCH64REG_READ_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
AARCH64REG_WRITE_INLINE3(pan, pan, ATTR_ARCH("armv8.1-a"))
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser
AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Register
AARCH64REG_WRITE_INLINE(cpacr_el1)
#define CPACR_TTA __BIT(28) // System Register Access Traps
@@ -661,6 +667,8 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14
#define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers
#define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7
#define ESR_EC_PAUTH 0x09 // A64: Pointer auth trap (FEAT_PAUTH)
#define ESR_EC_LS64 0x0a // AXX: LD64B/ST64B instruction (FEAT_LS64) // XXXNH
#define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14
#define ESR_EC_BTE_A64 0x0d // A64: Branch Target Exception (V8.5)
#define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State
@@ -671,29 +679,54 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution
#define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution
#define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7)
#define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0)
#define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1)
#define ESR_EC_SVE 0x19 // AXX: SVE Instruction Execution (FEAT_SVE)
#define ESR_EC_PAUTH_ERET 0x1a // A64: ERET/ERETAA/ERETAB (FEAT_PAUTH and FEAT_NV)
#define ESR_EC_TME 0x1b // A64: TSTART instruction (FEAT_TME)
#define ESR_EC_FRAC 0x1c // A64: Pointer auth trap (FEAT_FPAC)
#define ESR_EC_SME 0x1d // AXX: Access to SME (FEAT_SME)
#define ESR_EC_RME 0x1e // A64: Granule Protection Check (FEAT_RME)
#define ESR_EC_INSN_ABT_EL_LOW 0x20 // AXX: Instruction Abort from lower level
#define ESR_EC_INSN_ABT_EL_CUR 0x21 // AXX: Instruction Abort from current level
#define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC
#define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0)
#define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1)
#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
#define ESR_EC_DATA_ABT_EL_LOW 0x24 // AXX: Data Abort from lower level
#define ESR_EC_DATA_ABT_EL_CUR 0x25 // AXX: Data Abort from current level
#define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP
#define ESR_EC_MOPS 0x27 // A64: Memory Operation Exception (FEAT_MOPS)
#define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception
#define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception
#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
#define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0)
#define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1)
#define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0)
#define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1)
#define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0)
#define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1)
#define ESR_EC_SERROR 0x2f // AXX: SError Interrupt
#define ESR_EC_BRKPNT_EL_LOW 0x30 // AXX: Breakpoint Exception from lower level
#define ESR_EC_BRKPNT_EL_CUR 0x31 // AXX: Breakpoint Exception from current level
#define ESR_EC_SW_STEP_EL_LOW 0x32 // AXX: Software Step from lower level
#define ESR_EC_SW_STEP_EL_CUR 0x33 // AXX: Software Step from current level
#define ESR_EC_WTCHPNT_EL_LOW 0x34 // AXX: Watchpoint from lower level
#define ESR_EC_WTCHPNT_EL_CUR 0x35 // AXX: Watchpoint from current level
#define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution
#define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception
#define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution
/* alias for EL1 kernel */
#define ESR_EC_INSN_ABT_EL0 ESR_EC_INSN_ABT_EL_LOW
#define ESR_EC_INSN_ABT_EL1 ESR_EC_INSN_ABT_EL_CUR
#define ESR_EC_DATA_ABT_EL0 ESR_EC_DATA_ABT_EL_LOW
#define ESR_EC_DATA_ABT_EL1 ESR_EC_DATA_ABT_EL_CUR
#define ESR_EC_BRKPNT_EL0 ESR_EC_BRKPNT_EL_LOW
#define ESR_EC_BRKPNT_EL1 ESR_EC_BRKPNT_EL_CUR
#define ESR_EC_SW_STEP_EL0 ESR_EC_SW_STEP_EL_LOW
#define ESR_EC_SW_STEP_EL1 ESR_EC_SW_STEP_EL_CUR
#define ESR_EC_WTCHPNT_EL0 ESR_EC_WTCHPNT_EL_LOW
#define ESR_EC_WTCHPNT_EL1 ESR_EC_WTCHPNT_EL_CUR
#define ESR_IL __BIT(25) // Instruction Length (1=32-bit)
#define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome
#define ESR_ISS_CV __BIT(24) // common
#define ESR_ISS_COND __BITS(23,20) // common
#define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX
#define ESR_ISS_SYSREG_OP0 __BITS(21,20) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_OP2 __BITS(19,17) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_OP1 __BITS(16,14) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_CRN __BITS(13,10) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_RT __BITS(9,5) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_CRM __BITS(4,1) // for ESR_EC_SYS_REG
#define ESR_ISS_SYSREG_DIRECTION __BIT(0) // for ESR_EC_SYS_REG
#define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT
#define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT
#define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT
@@ -713,7 +746,7 @@ AARCH64REG_WRITE_INLINE(esr_el1)
#define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SRT __BITS(20,16) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01]
#define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01]
@@ -758,6 +791,101 @@ AARCH64REG_WRITE_INLINE(esr_el1)
AARCH64REG_READ_INLINE(far_el1) // Fault Address Register
AARCH64REG_WRITE_INLINE(far_el1)
AARCH64REG_READ_INLINE(far_el2)
AARCH64REG_WRITE_INLINE(far_el2)
AARCH64REG_READ_INLINE(hcr_el2) // Hypervisor Configuration Register
AARCH64REG_WRITE_INLINE(hcr_el2)
#define HCR_EL2_TWEDEL __BITS(63,60) // TWE Delay (FEAT_TWED)
#define HCR_EL2_TWEDEN __BIT(59) // TWE Delay Enable (FEAT_TWED)
#define HCR_EL2_TID5 __BIT(58) // Trap ID group 5 (FEAT_MTE2)
#define HCR_EL2_DCT __BIT(57) // Default Cacheability Tagging (FEAT_MTE2)
#define HCR_EL2_ATA __BIT(56) // Allocation Tag Access (FEAT_MTE2)
#define HCR_EL2_TTLBOS __BIT(55) // Trap TLB maintenance OS (FEAT_EVT)
#define HCR_EL2_TTLBIS __BIT(54) // Trap TLB maintenance IS (FEAT_EVT)
#define HCR_EL2_ENSCXT __BIT(53) // Enable SCXTNUM_EL[01] access (FEAT_CSV2)
#define HCR_EL2_TOCU __BIT(52) // Trap PoU cache maintenance
#define HCR_EL2_AMVOFFEN __BIT(51) // Activity Monitors Virtual Offsets Enable (FEAT_AMUv1p1)
#define HCR_EL2_TICAB __BIT(50) // Trap IC all broadcast maintenance.
#define HCR_EL2_TID4 __BIT(49) // Trap ID group 4 (FEAT_EVT)
#define HCR_EL2_GPF __BIT(48) // Granule Protection Faults (FEAT_RME)
#define HCR_EL2_FIEN __BIT(47) // Fault Injection Enable (FEAT_RASv1p1)
#define HCR_EL2_FWB __BIT(46) // Forced Write-Back (FEAT_S2FWB)
#define HCR_EL2_NV2 __BIT(45) // Nested Virtualization (FEAT_NV2)
#define HCR_EL2_AT __BIT(44) // Address Translation (FEAT_NV)
#define HCR_EL2_NV1 __BIT(43) // Nested Virtualization (FEAT_NV2/FEAT_NV)
#define HCR_EL2_NV __BIT(42) // Nested Virtualization (FEAT_NV2/FEAT_NV)
#define HCR_EL2_API __BIT(41) // Pointer Authentication instruction (FEAT_PAuth)
#define HCR_EL2_APK __BIT(40) // Pointer Authentication key (FEAT_PAuth)
#define HCR_EL2_TME __BIT(39) // TME enable (FEAT_TME)
#define HCR_EL2_MIOCNCE __BIT(38) // Mismatched Inner/Outer Cacheable Non-Coherency Enable,
#define HCR_EL2_TEA __BIT(37) // Route synchronous External abort exceptions to EL2 (FEAT_RAS)
#define HCR_EL2_TERR __BIT(36) // Trap accesses of Error Record registers (FEAT_RAS)
#define HCR_EL2_TLOR __BIT(35) // Trap LOR registers (FEAT_LOR)
#define HCR_EL2_VHE __BIT(34) // EL2 Host (FEAT_VHE)
#define HCR_EL2_ID __BIT(33) // stage2 IC disable
#define HCR_EL2_CD __BIT(32) // stage2 DC disable
#define HCR_EL2_RW __BIT(31) // register width
#define HCR_EL2_TRVM __BIT(30) // trap VM control regs read
#define HCR_EL2_HCD __BIT(29) // HVC disable
#define HCR_EL2_TDZ __BIT(28) // trap DC ZVA
#define HCR_EL2_TGE __BIT(27) // trap general exceptions
#define HCR_EL2_TVM __BIT(26) // trap VM control regs write
#define HCR_EL2_TTLB __BIT(25) // trap TLB maintenance op
#define HCR_EL2_TPU __BIT(24) // trap IC {IVAU,IALLU,IALLUIS},DC CVAU
#define HCR_EL2_TPC __BIT(23) // trap DC {IVAC,CIVAC,CVAC}
#define HCR_EL2_TSW __BIT(22) // trap DC {ISW,CSW,CISW}
#define HCR_EL2_TACR __BIT(21) // trap ACTRL_EL1 access
#define HCR_EL2_TIDCP __BIT(20) // trap IMPLEMENTATION DEFINED system regs
#define HCR_EL2_TSC __BIT(19) // trap SMC
#define HCR_EL2_TID3 __BIT(18) // trap ID group3 regs
#define HCR_EL2_TID2 __BIT(17) // trap ID group2 regs
#define HCR_EL2_TID1 __BIT(16) // trap ID group1 regs
#define HCR_EL2_TID0 __BIT(15) // trap ID group0 regs
#define HCR_EL2_TWE __BIT(14) // trap WFE
#define HCR_EL2_TWI __BIT(13) // trap WFI
#define HCR_EL2_DC __BIT(12) // default cacheablility
#define HCR_EL2_BSU __BITS(11,10) // barrier shareability upgrade
#define HCR_EL2_FB __BIT(9) // force broadcast TLBI and IC
#define HCR_EL2_VSE __BIT(8) // inject Virtual SError
#define HCR_EL2_VI __BIT(7) // inject Virtual IRQ
#define HCR_EL2_VF __BIT(6) // inject Virtual FIQ
#define HCR_EL2_AMO __BIT(5) // trap SError/AsyncAbort
#define HCR_EL2_IMO __BIT(4) // trap IRQ
#define HCR_EL2_FMO __BIT(3) // trap FIQ
#define HCR_EL2_PTW __BIT(2) // Protect table walk
#define HCR_EL2_SWIO __BIT(1) // override DC ISW to DC CISW
#define HCR_EL2_VM __BIT(0) // enable stage2 translation
AARCH64REG_READ_INLINE(hpfar_el2) // Hypervisor IPA Fault Address Register
AARCH64REG_WRITE_INLINE(hpfar_el2)
#define HPFAR_EL2_NS __BIT(63) // Faulting IPA address space (FEAT_SEL2)
#define HPFAR_EL2_FIPA_D128 __BITS(47,4) // Faulting Intermediate Physical Address Bits [55:12]
#define HPFAR_EL2_FIPA __BITS(43,4) // Faulting Intermediate Physical Address Bits [51:12]
#define HPFAR_EL2_FIPA_BITSHIFT 12
AARCH64REG_READ_INLINE(hstr_el2) // Hypervisor System Trap Register
AARCH64REG_WRITE_INLINE(hstr_el2)
#define HSTR_EL2_T15 __BIT(15)
// __BIT(14) Res0
#define HSTR_EL2_T13 __BIT(13)
#define HSTR_EL2_T12 __BIT(12)
#define HSTR_EL2_T11 __BIT(11)
#define HSTR_EL2_T10 __BIT(10)
#define HSTR_EL2_T9 __BIT(9)
#define HSTR_EL2_T8 __BIT(8)
#define HSTR_EL2_T7 __BIT(7)
#define HSTR_EL2_T6 __BIT(6)
#define HSTR_EL2_T5 __BIT(5)
// __BIT(4) Res0
#define HSTR_EL2_T3 __BIT(3)
#define HSTR_EL2_T2 __BIT(2)
#define HSTR_EL2_T1 __BIT(1)
#define HSTR_EL2_T0 __BIT(0)
AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
@@ -770,6 +898,12 @@ AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73
AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register
AARCH64REG_WRITE_INLINE(mair_el1)
AARCH64REG_READ_INLINE(mair_el2)
AARCH64REG_WRITE_INLINE(mair_el2)
AARCH64REG_READ_INLINE(amair_el1) // Auxiliary MAIR
AARCH64REG_WRITE_INLINE(amair_el1)
AARCH64REG_READ_INLINE(amair_el2)
AARCH64REG_WRITE_INLINE(amair_el2)
#define MAIR_ATTR0 __BITS(7,0)
#define MAIR_ATTR1 __BITS(15,8)
@@ -791,6 +925,7 @@ AARCH64REG_WRITE_INLINE(par_el1)
#define PAR_ATTR __BITS(63,56) // F=0 memory attributes
#define PAR_PA __BITS(51,12) // F=0 physical address
#define PAR_PA_SHIFT 12
#define PAR_PA_LOWMASK __BITS(11,0)
#define PAR_NS __BIT(9) // F=0 non-secure
#define PAR_SH __BITS(8,7) // F=0 shareability attribute
#define PAR_SH_NONE 0
@@ -808,13 +943,19 @@ AARCH64REG_WRITE_INLINE(rmr_el1)
AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register
AARCH64REG_WRITE_INLINE(rvbar_el1)
AARCH64REG_ATWRITE_INLINE(s1e0r); // Address Translate Stages 1
AARCH64REG_ATWRITE_INLINE(s1e0w);
AARCH64REG_ATWRITE_INLINE(s1e1r);
AARCH64REG_ATWRITE_INLINE(s1e1w);
AARCH64REG_ATWRITE_INLINE(s1e0r) // Address Translate Stages 1 EL0
AARCH64REG_ATWRITE_INLINE(s1e0w)
AARCH64REG_ATWRITE_INLINE(s1e1r) // Address Translate Stages 1 EL1
AARCH64REG_ATWRITE_INLINE(s1e1w)
AARCH64REG_ATWRITE_INLINE(s12e0r) // Address Translate Stages 1 and 2 EL0
AARCH64REG_ATWRITE_INLINE(s12e0w)
AARCH64REG_ATWRITE_INLINE(s12e1r) // Address Translate Stages 1 and 2 EL1
AARCH64REG_ATWRITE_INLINE(s12e1w)
AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register
AARCH64REG_WRITE_INLINE(sctlr_el1)
AARCH64REG_READ_INLINE(sctlr_el2)
AARCH64REG_WRITE_INLINE(sctlr_el2)
#define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0
#define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1
@@ -869,6 +1010,8 @@ reg_sp_read(void)
AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer
AARCH64REG_WRITE_INLINE(sp_el0)
AARCH64REG_READ_INLINE(sp_el1) // EL1 Stack Pointer
AARCH64REG_WRITE_INLINE(sp_el1)
AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select
AARCH64REG_WRITE_INLINE(spsel)
@@ -921,10 +1064,12 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
#define SPSR_M_FIQ32 0x11
#define SPSR_M_USR32 0x10
#define SPSR_USER_P(spsr) (((spsr) & (SPSR_M & ~SPSR_A32)) == 0)
#define SPSR_PRIVILEGED_P(spsr) (!SPSR_USER_P((spsr)))
AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register
AARCH64REG_WRITE_INLINE(tcr_el1)
/* TCR_EL1 - Translation Control Register */
#define TCR_TCMA1 __BIT(58) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b11111 */
#define TCR_TCMA0 __BIT(57) /* ARMv8.5-MemTag control when ADDR[59:55] = 0b00000 */
@@ -999,15 +1144,60 @@ AARCH64REG_WRITE_INLINE(tcr_el1)
#define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */
#define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */
AARCH64REG_READ_INLINE(tcr_el2) // Translation Control Register EL2
AARCH64REG_WRITE_INLINE(tcr_el2)
/* TCR_EL2 - Translation Control Register */
// __BITS(63, 34) // Res0
#define TCR_EL2_MTX __BIT(33) // Extended memory tag checking
#define TCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
// __BIT(31) // Res1
#define TCR_EL2_TCMA __BIT(30) // Unchecked accesses control (FEAT_MTE2)
#define TCR_EL2_TBID __BIT(29) // Top Byte Instruction address matching (FEAT_PAuth)
#define TCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
#define TCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
#define TCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
#define TCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
#define TCR_EL2_HPD __BIT(24) // Hierarchical Permission Disables (FEAT_HPDS)
// __BIT(23) // Res1
#define TCR_EL2_HD __BIT(22) // Hardware management of dirty state (FEAT_HAFDBS)
#define TCR_EL2_HA __BIT(21) // Hardware Access flag update (FEAT_HAFDBS)
#define TCR_EL2_TBI __BIT(20) // Top Byte Ignored
// __BIT(19) // Res1
#define TCR_EL2_PS __BITS(18,16) // Physical Address Size
#define TCR_EL2_TG0 __BITS(15,14) // TTBR0_EL2 Granule size
#define TCR_EL2_TG0_4KB __SHIFTIN(0,TCR_EL2_TG0) // 4KB page size
#define TCR_EL2_TG0_64KB __SHIFTIN(1,TCR_EL2_TG0) // 64KB page size
#define TCR_EL2_TG0_16KB __SHIFTIN(2,TCR_EL2_TG0) // 16KB page size
#define TCR_EL2_SH0 __BITS(13,12) // TTBR0_EL2 Shareability attribute
#define TCR_EL2_SH0_NONE __SHIFTIN(0,TCR_EL2_SH0) // non-shareable
#define TCR_EL2_SH0_OUTER __SHIFTIN(2,TCR_EL2_SH0) // Outer shareable
#define TCR_EL2_SH0_INNER __SHIFTIN(3,TCR_EL2_SH0) // Inner shareable
#define TCR_EL2_ORGN0 __BITS(11,10) // TTBR0_EL2 Outer cacheability attribute
#define TCR_EL2_ORGN0_NC __SHIFTIN(0,TCR_EL2_ORGN0) // Non Cacheable
#define TCR_EL2_ORGN0_WB_WA __SHIFTIN(1,TCR_EL2_ORGN0) // WriteBack WriteAllocate
#define TCR_EL2_ORGN0_WT __SHIFTIN(2,TCR_EL2_ORGN0) // WriteThrough
#define TCR_EL2_ORGN0_WB __SHIFTIN(3,TCR_EL2_ORGN0) // WriteBack
#define TCR_EL2_IRGN0 __BITS(9,8) // TTBR0_EL2 Inner cacheability attribute
#define TCR_EL2_IRGN0_NC __SHIFTIN(0,TCR_EL2_IRGN0) // Non Cacheable
#define TCR_EL2_IRGN0_WB_WA __SHIFTIN(1,TCR_EL2_IRGN0) // WriteBack WriteAllocate
#define TCR_EL2_IRGN0_WT __SHIFTIN(2,TCR_EL2_IRGN0) // WriteThrough
#define TCR_EL2_IRGN0_WB __SHIFTIN(3,TCR_EL2_IRGN0) // WriteBack
#define TCR_EL2_T0SZ __BITS(5,0) // TTBR0_EL2 Size offset
AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1)
AARCH64REG_WRITE_INLINE(tpidr_el1)
AARCH64REG_READ_INLINE(tpidr_el2) // Thread ID Register (EL2)
AARCH64REG_WRITE_INLINE(tpidr_el2)
AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0)
AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1
AARCH64REG_WRITE_INLINE(ttbr0_el1)
AARCH64REG_READ_INLINE(ttbr0_el2) // Translation Table Base Register 0 EL2
AARCH64REG_WRITE_INLINE(ttbr0_el2)
AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1
AARCH64REG_WRITE_INLINE(ttbr1_el1)
#define TTBR_ASID __BITS(63,48)
@@ -1015,6 +1205,53 @@ AARCH64REG_WRITE_INLINE(ttbr1_el1)
AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register
AARCH64REG_WRITE_INLINE(vbar_el1)
AARCH64REG_READ_INLINE(vbar_el2)
AARCH64REG_WRITE_INLINE(vbar_el2)
AARCH64REG_READ_INLINE(vpidr_el2) // Virtualization Processor ID Register
AARCH64REG_WRITE_INLINE(vpidr_el2)
AARCH64REG_READ_INLINE(vmpidr_el2) // Virtualization Multiprocessor ID Register
AARCH64REG_WRITE_INLINE(vmpidr_el2)
AARCH64REG_READ_INLINE(vtcr_el2) // Virtualization Translation Control Register
AARCH64REG_WRITE_INLINE(vtcr_el2)
#define VTCR_EL2_HAFT __BIT(44) // Hardware managed Access Flag (FEAT_HAFT)
// __BITS(43, 42) // Res0
#define VTCR_EL2_TL0 __BIT(41) // TopLevel0 permission attribute control (FEAT_THE)
#define VTCR_EL2_GCSH __BIT(40) // Assured translations for guarded control stacks (FEAT_THE+FEAT_GCS)
// __BIT(39) // Res0
#define VTCR_EL2_D128 __BIT(38) // VMSAv9-128 (FEAT_D128)
#define VTCR_EL2_S2POE __BIT(37) // Enable stage 2 Permission Overlay (FEAT_S2POE)
#define VTCR_EL2_S2PIE __BIT(36) // Select Permission Model. (FEAT_S2PIE)
#define VTCR_EL2_TL1 __BIT(35) // TopLevel1 permission attribute control (FEAT_THE)
#define VTCR_EL2_AO __BIT(34) // AssuredOnly attribute enable (FEAT_THE)
#define VTCR_EL2_SL2 __BIT(33) // Stage 2 starting level (FEAT_LPA2)
#define VTCR_EL2_DS __BIT(32) // 52-bit output address (FEAT_LPA2)
// __BIT(31) // Res1
#define VTCR_EL2_NSA __BIT(30) // Non-secure S2 translation output address space (FEAT_SEL2)
#define VTCR_EL2_NSW __BIT(29) // Non-secure S2 translation table address space (FEAT_SEL2)
#define VTCR_EL2_HWU62 __BIT(28) // Hardware use bit 62 (FEAT_HPDS2)
#define VTCR_EL2_HWU61 __BIT(27) // Hardware use bit 61 (FEAT_HPDS2)
#define VTCR_EL2_HWU60 __BIT(26) // Hardware use bit 60 (FEAT_HPDS2)
#define VTCR_EL2_HWU59 __BIT(25) // Hardware use bit 59 (FEAT_HPDS2)
// __BITS(24, 23) // Res0
#define VTCR_EL2_HD __BIT(22) // Hardware Dirty state management (FEAT_HAFDBS)
#define VTCR_EL2_HA __BIT(21) // Hardware Access flag management (FEAT_HAFDBS)
#define VTCR_EL2_VS __BIT(19) // VMID size (FEAT_VMID16)
#define VTCR_EL2_PS __BITS(18,16) // Physical address Size
#define VTCR_EL2_TG0 __BITS(15,14) // VTTBR_EL2 Granule size
#define VTCR_EL2_SH0 __BITS(13,12) // V{,S}TTBR_EL2 shareability attribute
#define VTCR_EL2_ORGN0 __BITS(11,10) // V{,S}TTBR_EL2 outer cacheability
#define VTCR_EL2_IRGN0 __BITS(9,8) // V{,S}TTBR_EL2 inner cacheability
#define VTCR_EL2_SL0 __BITS(7,6) // Start Level of S2 translation lookup.
#define VTCR_EL2_T0SZ __BITS(5,0) // VTTBR_EL2 Size offset
AARCH64REG_READ_INLINE(vttbr_el2) // Virtualization Translation Table Base Register
AARCH64REG_WRITE_INLINE(vttbr_el2)
#define VTTBR_VIMD __BITS(55,48)
#define VTTBR_BADDR __BITS(47,0)
/*
* From here on, these are DEBUG registers
lib/libc/include/aarch64-netbsd-none/machine/byte_swap.h
Vendored
+3 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.4 2017/01/17 11:09:36 rin Exp $ */
/* $NetBSD: byte_swap.h,v 1.4.52.1 2025/12/18 19:57:53 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -46,7 +46,8 @@
#else
#ifdef __GNUC__
#include <sys/types.h>
#include <sys/stdint.h>
__BEGIN_DECLS
#define __BYTE_SWAP_U64_VARIABLE __byte_swap_u64_variable
lib/libc/include/aarch64-netbsd-none/machine/cpu.h
Vendored
+26 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.48.2.1 2024/10/13 10:43:11 martin Exp $ */
/* $NetBSD: cpu.h,v 1.53 2024/12/30 19:17:21 jmcneill Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -99,6 +99,21 @@ struct aarch64_cache_info {
struct aarch64_cache_unit dcache;
};
struct aarch64_low_power_idle {
uint32_t min_res; /* minimum residency */
uint32_t wakeup_latency; /* worst case */
uint32_t save_restore_flags;
#define LPI_SAVE_RESTORE_CORE __BIT(0)
#define LPI_SAVE_RESTORE_TRACE __BIT(1)
#define LPI_SAVE_RESTORE_GICR __BIT(2)
#define LPI_SAVE_RESTORE_GICD __BIT(3)
uint32_t reg_addr;
#define LPI_REG_ADDR_WFI 0xffffffff
char *name;
struct evcnt events;
};
struct cpu_info {
struct cpu_data ci_data;
device_t ci_dev;
@@ -166,12 +181,18 @@ struct cpu_info {
/* ACPI */
uint32_t ci_acpiid; /* ACPI Processor Unique ID */
/* ACPI low power idle */
uint32_t ci_nlpi;
struct aarch64_low_power_idle *ci_lpi;
uint64_t ci_last_idle;
/* cached system registers */
uint64_t ci_sctlr_el1;
uint64_t ci_sctlr_el2;
/* sysctl(9) exposed system registers */
struct aarch64_sysctl_cpu_id ci_id;
#define ci_midr ci_id.ac_midr
/* cache information and function pointers */
struct aarch64_cache_info ci_cacheinfo[MAX_CACHE_LEVEL];
@@ -243,10 +264,14 @@ static inline void
cpu_dosoftints(void)
{
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
KDASSERT(kpreempt_disabled());
cpu_dosoftints_ci(curcpu());
#endif
}
struct cpufeature_attach_args {
struct cpu_info *ci;
};
#endif /* _KERNEL */
lib/libc/include/aarch64-netbsd-none/machine/lwp_private.h
Vendored
+3
View File
@@ -0,0 +1,3 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:05 christos Exp $ */
#include <arm/lwp_private.h>
lib/libc/include/aarch64-netbsd-none/machine/pmap.h
Vendored
+7 -33
View File
@@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.57 2022/11/03 09:04:56 skrll Exp $ */
/* $NetBSD: pmap.h,v 1.59 2023/08/02 15:57:21 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -59,12 +59,6 @@
/* Maximum number of ASIDs. Some CPUs have less.*/
#define PMAP_TLB_NUM_PIDS 65536
#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
#define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
#if PMAP_TLB_MAX > 1
#define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
#else
#define cpu_tlb_info(ci) (&pmap_tlb0_info)
#endif
static inline tlb_asid_t
pmap_md_tlb_asid_max(void)
@@ -80,6 +74,7 @@ pmap_md_tlb_asid_max(void)
}
#include <uvm/pmap/tlb.h>
#include <uvm/pmap/pmap_devmap.h>
#include <uvm/pmap/pmap_tlb.h>
#define KERNEL_PID 0 /* The kernel uses ASID 0 */
@@ -161,22 +156,6 @@ pmap_kvattr(pt_entry_t *ptep, vm_prot_t prot)
return opte;
}
/* devmap */
struct pmap_devmap {
vaddr_t pd_va; /* virtual address */
paddr_t pd_pa; /* physical address */
psize_t pd_size; /* size of region */
vm_prot_t pd_prot; /* protection code */
u_int pd_flags; /* flags for pmap_kenter_pa() */
};
void pmap_devmap_register(const struct pmap_devmap *);
void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
vaddr_t pmap_devmap_phystov(paddr_t);
paddr_t pmap_devmap_vtophys(paddr_t);
#define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
#define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
#define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
@@ -186,16 +165,7 @@ paddr_t pmap_devmap_vtophys(paddr_t);
#define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x))
#define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x))
#define DEVMAP_ENTRY(va, pa, sz) \
{ \
.pd_va = DEVMAP_ALIGN(va), \
.pd_pa = DEVMAP_ALIGN(pa), \
.pd_size = DEVMAP_SIZE(sz), \
.pd_prot = VM_PROT_READ | VM_PROT_WRITE, \
.pd_flags = PMAP_DEV \
}
#define DEVMAP_ENTRY_END { 0 }
#define DEVMAP_FLAGS PMAP_DEV
/* Hooks for the pool allocator */
paddr_t vtophys(vaddr_t);
@@ -268,6 +238,8 @@ void pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t,
void (*)(const char *, ...) __printflike(1, 2));
int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
#if defined(DDB)
void pmap_db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2));
void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
@@ -415,6 +387,8 @@ void pmap_pv_track(paddr_t, psize_t);
void pmap_pv_untrack(paddr_t, psize_t);
void pmap_pv_protect(paddr_t, vm_prot_t);
vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
#define PMAP_MAPSIZE1 L2_SIZE
/* for ddb */
lib/libc/include/aarch64-netbsd-none/machine/sljit_machdep.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: sljit_machdep.h,v 1.3.18.2 2024/05/11 14:08:32 martin Exp $ */
/* $NetBSD: sljit_machdep.h,v 1.5 2024/05/05 15:18:10 riastradh Exp $ */
/*-
* Copyright (c) 2014 Alexander Nasonov.
lib/libc/include/aarch64-netbsd-none/machine/vmparam.h
Vendored
+4 -4
View File
@@ -1,4 +1,4 @@
/* $NetBSD: vmparam.h,v 1.19.4.1 2024/07/03 19:13:20 martin Exp $ */
/* $NetBSD: vmparam.h,v 1.21 2024/06/30 09:36:43 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -151,11 +151,11 @@
* last 254MB of kernel vm area (0xfffffffff0000000-0xffffffffffe00000)
* may be used for devmap. see aarch64/pmap.c:pmap_devmap_*
*/
#define VM_KERNEL_IO_ADDRESS 0xfffffffff0000000L
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_ADDRESS)
#define VM_KERNEL_IO_BASE 0xfffffffff0000000L
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_BASE)
#define VM_KERNEL_VM_BASE (0xffffc00040000000L)
#define VM_KERNEL_VM_SIZE (VM_KERNEL_IO_ADDRESS - VM_KERNEL_VM_BASE)
#define VM_KERNEL_VM_SIZE (VM_KERNEL_IO_BASE - VM_KERNEL_VM_BASE)
/* virtual sizes (bytes) for various kernel submaps */
#define USRIOSIZE (PAGE_SIZE / 8)
lib/libc/include/arm-netbsd-eabi/float.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: float.h,v 1.8 2014/01/29 01:10:36 matt Exp $ */
/* $NetBSD: float.h,v 1.9 2024/10/30 15:56:11 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -33,6 +33,7 @@
#define _ARM_FLOAT_H_
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#ifdef __ARM_PCS_AAPCS64
lib/libc/include/arm-netbsd-eabi/machine/asm.h
Vendored
+48 -19
View File
@@ -1,4 +1,4 @@
/* $NetBSD: asm.h,v 1.34 2020/04/23 23:22:41 jakllsch Exp $ */
/* $NetBSD: asm.h,v 1.39.2.1 2026/04/02 19:12:03 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -73,8 +73,10 @@
#ifdef __thumb__
#define THUMB_INSN(n) n
#define _INSN_SIZE (2)
#else
#define THUMB_INSN(n)
#define _INSN_SIZE (4)
#endif
#define __BIT(n) (1 << (n))
@@ -130,7 +132,7 @@
#ifdef GPROF
# define _PROF_PROLOGUE \
mov ip, lr; bl __mcount
push {lr}; bl __gnu_mcount_nc
#else
# define _PROF_PROLOGUE
#endif
@@ -194,21 +196,25 @@
#define GOT_GET(x,got,sym) \
ldr x, sym; \
ldr x, [x, got]
#define GOT_INIT(got,gotsym,pclabel) \
ldr got, gotsym; \
pclabel: add got, got, pc
#ifdef __thumb__
#define GOT_INITSYM(gotsym,pclabel) \
/*
* Load _GLOBAL_OFFSET_TABLE_ address into register:
*
* 0: GOT_INIT(rX, .Lgot)
* ...
*
* // and in the data after the function
* GOT_INITSYM(.Lgot, 0b)
*/
#define GOT_INIT(Rgot, gotsym) \
ldr Rgot, gotsym ; \
add Rgot, Rgot, pc
#define GOT_INITSYM(gotsym, initlabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4)
#else
#define GOT_INITSYM(gotsym,pclabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8)
#endif
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (initlabel+(1+2)*_INSN_SIZE)
#ifdef __STDC__
#define PIC_SYM(x,y) x ## ( ## y ## )
#define PIC_SYM(x,y) x(y)
#else
#define PIC_SYM(x,y) x/**/(/**/y/**/)
#endif
@@ -219,15 +225,38 @@
#define GOT_SYM(x) x
#define GOT_GET(x,got,sym) \
ldr x, sym;
#define GOT_INIT(got,gotsym,pclabel)
#define GOT_INITSYM(gotsym,pclabel)
#define GOT_INIT(Rgot, gotsym)
#define GOT_INITSYM(gotsym, initlabel)
#define PIC_SYM(x,y) x
#endif /* __PIC__ */
#define RCSID(x) .pushsection ".ident","MS",%progbits,1; \
.asciz x; \
/*
* Annoyingly, gas on arm seems to generate _two_ NUL-terminated
* strings for
*
* .asciz "foo" "bar"
*
* instead of concatenating it into a single NUL-terminated string as
* on other architectures.
*
* To work around this, we concatenate into a single NUL-terminated by:
*
* .ascii "foo"
* .asciz "bar"
*/
#define _IDENTSTR(x) .pushsection ".ident","MS",%progbits,1; \
x; \
.popsection
#ifdef _NETBSD_REVISIONID
#define RCSID(_s) \
_IDENTSTR(.asciz _s); \
_IDENTSTR(.ascii "$"; .ascii "NetBSD: "; .ascii __FILE__; \
.ascii " "; .ascii _NETBSD_REVISIONID; .asciz " $")
#else
#define RCSID(_s) _IDENTSTR(.asciz _s)
#endif
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
@@ -241,7 +270,7 @@
#ifdef __STDC__
#define WARN_REFERENCES(sym,msg) \
.pushsection .gnu.warning. ## sym; \
.pushsection .gnu.warning.sym; \
.ascii msg; \
.popsection
#else
lib/libc/include/arm-netbsd-eabi/machine/byte_swap.h
Vendored
+121
View File
@@ -0,0 +1,121 @@
/* $NetBSD: byte_swap.h,v 1.16.52.1 2025/12/18 19:57:52 martin Exp $ */
/*-
* Copyright (c) 1997, 1999, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, Neil A. Carson, and Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_BYTE_SWAP_H_
#define _ARM_BYTE_SWAP_H_
#ifdef _LOCORE
#if defined(_ARM_ARCH_6) || defined(_ARM_ARCH_7)
#define BSWAP16(_src, _dst, _tmp) \
rev16 _dst, _src
#define BSWAP32(_src, _dst, _tmp) \
rev _dst, _src
#else
#define BSWAP16(_src, _dst, _tmp) \
mov _tmp, _src, ror #8 ;\
orr _tmp, _tmp, _tmp, lsr #16 ;\
bic _dst, _tmp, _tmp, lsl #16
#define BSWAP32(_src, _dst, _tmp) \
eor _tmp, _src, _src, ror #16 ;\
bic _tmp, _tmp, #0x00FF0000 ;\
mov _dst, _src, ror #8 ;\
eor _dst, _dst, _tmp, lsr #8
#endif
#else
#ifdef __GNUC__
#include <sys/stdint.h>
__BEGIN_DECLS
#define __BYTE_SWAP_U32_VARIABLE __byte_swap_u32_variable
static __inline uint32_t
__byte_swap_u32_variable(uint32_t v)
{
uint32_t t1;
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(v)) {
__asm("rev\t%0, %1" : "=r" (v) : "0" (v));
return v;
}
#endif
t1 = v ^ ((v << 16) | (v >> 16));
t1 &= 0xff00ffffU;
v = (v >> 8) | (v << 24);
v ^= (t1 >> 8);
return v;
}
#define __BYTE_SWAP_U16_VARIABLE __byte_swap_u16_variable
static __inline uint16_t
__byte_swap_u16_variable(uint16_t v)
{
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(v)) {
uint32_t v32 = v;
__asm("rev16\t%0, %1" : "=r" (v32) : "0" (v32));
return (uint16_t)v32;
}
#elif !defined(__thumb__) && 0 /* gcc produces decent code for this */
if (!__builtin_constant_p(v)) {
uint32_t v0 = v;
__asm volatile(
"mov %0, %1, ror #8\n"
"orr %0, %0, %0, lsr #16\n"
"bic %0, %0, %0, lsl #16"
: "=&r" (v0)
: "0" (v0));
return (uint16_t)v0;
}
#endif
v &= 0xffff;
v = (uint16_t)((v >> 8) | (v << 8));
return v;
}
__END_DECLS
#endif
#endif /* _LOCORE */
#endif /* _ARM_BYTE_SWAP_H_ */
lib/libc/include/arm-netbsd-eabi/machine/cpu.h
Vendored
+1 -3
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.123.4.1 2023/08/09 17:42:01 martin Exp $ */
/* $NetBSD: cpu.h,v 1.125 2023/07/11 11:01:18 riastradh Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -236,8 +236,6 @@ struct cpu_info {
uint32_t ci_vfp_id;
uint64_t ci_lastintr;
struct pmap_tlb_info *
ci_tlb_info;
struct pmap * ci_pmap_lastuser;
struct pmap * ci_pmap_cur;
tlb_asid_t ci_pmap_asid_cur;
lib/libc/include/arm-netbsd-eabi/machine/float.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: float.h,v 1.8 2014/01/29 01:10:36 matt Exp $ */
/* $NetBSD: float.h,v 1.9 2024/10/30 15:56:11 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -33,6 +33,7 @@
#define _ARM_FLOAT_H_
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#ifdef __ARM_PCS_AAPCS64
lib/libc/include/arm-netbsd-eabi/machine/frame.h
Vendored
-130
View File
@@ -1,130 +0,0 @@
/* $NetBSD: frame.h,v 1.23 2022/04/02 11:16:07 skrll Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* arm/frame.h - Stack frames structures
*/
#ifndef _ARM_FRAME_H_
#define _ARM_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
#include <sys/ucontext.h>
/*
* Trap frame. Pushed onto the kernel stack on a trap (synchronous exception).
*/
typedef struct trapframe {
register_t tf_spsr;
register_t tf_fill; /* fill here so r0 will be dword aligned */
register_t tf_r0;
register_t tf_r1;
register_t tf_r2;
register_t tf_r3;
register_t tf_r4;
register_t tf_r5;
register_t tf_r6;
register_t tf_r7;
register_t tf_r8;
register_t tf_r9;
register_t tf_r10;
register_t tf_r11;
register_t tf_r12;
register_t tf_usr_sp;
register_t tf_usr_lr;
register_t tf_svc_sp;
register_t tf_svc_lr;
register_t tf_pc;
} trapframe_t;
/* Register numbers */
#define tf_ip tf_r12
#define tf_r13 tf_usr_sp
#define tf_r14 tf_usr_lr
#define tf_r15 tf_pc
#define TRAP_USERMODE(tf) (((tf)->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#define FB_R4 0
#define FB_R5 1
#define FB_R6 2
#define FB_R7 3
#define FB_R8 4
#define FB_R9 5
#define FB_R10 6
#define FB_R11 7
#define FB_R12 8
#define FB_R13 9
#define FB_R14 10
#define FB_MAX 11
struct faultbuf {
register_t fb_reg[FB_MAX];
};
/*
* Signal frame. Pushed onto user stack before calling sigcode.
*/
#ifdef COMPAT_16
struct sigframe_sigcontext {
struct sigcontext sf_sc;
};
#endif
/* the pointers are use in the trampoline code to locate the ucontext */
struct sigframe_siginfo {
siginfo_t sf_si; /* actual saved siginfo */
ucontext_t sf_uc; /* actual saved ucontext */
};
#if defined(_KERNEL) || defined(_KMEMUSER)
#ifdef _KERNEL
__BEGIN_DECLS
void sendsig_sigcontext(const ksiginfo_t *, const sigset_t *);
void *getframe(struct lwp *, int, int *);
__END_DECLS
#define lwp_settrapframe(l, tf) ((l)->l_md.md_tf = (tf))
#endif
#define lwp_trapframe(l) ((l)->l_md.md_tf)
#endif /* _KERNEL || _KMEMUSER */
#endif /* _LOCORE */
#endif /* _ARM_FRAME_H_ */
/* End of frame.h */
lib/libc/include/arm-netbsd-eabi/machine/lwp_private.h
Vendored
+81
View File
@@ -0,0 +1,81 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:07 christos Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_LWP_PRIVATE_H_
#define _ARM_LWP_PRIVATE_H_
#include <sys/cdefs.h>
#include <sys/tls.h>
#include <lwp.h>
#if defined(__aarch64__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
void *__tpidr;
__asm __volatile("mrs\t%0, tpidr_el0" : "=r"(__tpidr));
return __tpidr;
}
__END_DECLS
#elif defined(__arm__)
#if defined(__thumb__) && !defined(_ARM_ARCH_T2)
#include <arm/eabi.h>
#endif
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
if (__predict_true(rv))
return rv;
/*
* Some ARM cores are broken and don't raise an undefined fault when an
* unrecogized mrc instruction is encountered, but just return zero.
* To do deal with that, if we get a zero we (re-)fetch the value using
* syscall.
*/
return _lwp_getprivate();
#else
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
__END_DECLS
#endif
#endif /* !_ARM_LWP_PRIVATE_H_ */
lib/libc/include/arm-netbsd-eabi/machine/mcontext.h
Vendored
+5 -51
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mcontext.h,v 1.23 2021/10/06 05:33:15 skrll Exp $ */
/* $NetBSD: mcontext.h,v 1.27 2024/11/30 01:04:07 christos Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -210,61 +210,15 @@ typedef struct {
#endif
#if defined(_RTLD_SOURCE) || defined(_LIBC_SOURCE) || \
defined(__LIBPTHREAD_SOURCE__)
#include <sys/tls.h>
#if defined(__aarch64__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
void *__tpidr;
__asm __volatile("mrs\t%0, tpidr_el0" : "=r"(__tpidr));
return __tpidr;
}
__END_DECLS
#elif defined(__arm__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
extern void *_lwp_getprivate(void);
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
if (__predict_true(rv))
return rv;
/*
* Some ARM cores are broken and don't raise an undefined fault when an
* unrecogized mrc instruction is encountered, but just return zero.
* To do deal with that, if we get a zero we (re-)fetch the value using
* syscall.
*/
return _lwp_getprivate();
#else
extern void *__aeabi_read_tp(void);
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
__END_DECLS
#endif
#endif /* _RTLD_SOURCE || _LIBC_SOURCE || __LIBPTHREAD_SOURCE__ */
/* Machine-dependent uc_flags */
#define _UC_TLSBASE 0x00080000 /* see <sys/ucontext.h> */
#define _UC_TLSBASE _UC_MD_BIT19 /* see <sys/ucontext.h> */
/* Machine-dependent uc_flags for arm */
#define _UC_ARM_VFP 0x00010000 /* FPU field is VFP */
#define _UC_ARM_VFP _UC_MD_BIT16 /* FPU field is VFP */
/* used by signal delivery to indicate status of signal stack */
#define _UC_SETSTACK 0x00020000
#define _UC_CLRSTACK 0x00040000
#define _UC_SETSTACK _UC_MD_BIT17
#define _UC_CLRSTACK _UC_MD_BIT18
#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_FP])
lib/libc/include/arm-netbsd-eabi/machine/mutex.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mutex.h,v 1.27.4.1 2023/08/09 17:42:01 martin Exp $ */
/* $NetBSD: mutex.h,v 1.29 2023/07/12 12:50:12 riastradh Exp $ */
/*-
* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
lib/libc/include/arm-netbsd-eabi/machine/proc.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: proc.h,v 1.19 2020/08/14 16:18:36 skrll Exp $ */
/* $NetBSD: proc.h,v 1.20 2024/02/10 18:43:51 andvar Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@@ -48,7 +48,7 @@ struct mdlwp {
volatile uint32_t md_astpending;
};
/* Flags setttings for md_flags */
/* Flags settings for md_flags */
#define MDLWP_NOALIGNFLT 0x00000002 /* For EXEC_AOUT */
#define MDLWP_VFPINTR 0x00000004 /* VFP used in intr */
lib/libc/include/arm-netbsd-eabi/machine/profile.h
Vendored
+28 -96
View File
@@ -1,4 +1,4 @@
/* $NetBSD: profile.h,v 1.18 2018/01/24 09:04:45 skrll Exp $ */
/* $NetBSD: profile.h,v 1.18.42.1 2026/04/02 19:12:03 martin Exp $ */
/*
* Copyright (c) 2001 Ben Harris
@@ -38,90 +38,25 @@
* prologue.
*/
#define MCOUNT_ASM_NAME "__mcount"
#define PLTSYM
#if !defined(__ARM_EABI__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
/* Check what mode we're in. EQ => 32, NE => 26 */ \
__asm("teq r0, r0"); \
__asm("teq pc, r15"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("moveq r0, ip"); \
__asm("bicne r0, ip, #0xfc000003"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("moveq r1, lr"); \
__asm("bicne r1, lr, #0xfc000003"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#elif defined(__ARM_DWARF_EH__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".cfi_endproc"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#if defined (_ARM_ARCH_4T)
# define RET "bx ip"
#else
# define RET "mov pc, ip"
#endif
#if defined(__ARM_DWARF_EH__)
#define _PROF_UNWINDER_SAVE ""
#define _PROF_UNWINDER_START ""
#define _PROF_UNWINDER_END ""
#else
#define _PROF_UNWINDER_SAVE ".save {r0-r3, lr}\n"
#define _PROF_UNWINDER_START ".fnstart\n"
#define _PROF_UNWINDER_END ".fnend\n"
#endif
#define MCOUNT_ASM_NAME "__gnu_mcount_nc"
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
@@ -129,27 +64,26 @@
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".fnstart"); \
__asm(_PROF_UNWINDER_START); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".save {r0-r3, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm("push {r0-r3, lr}"); \
__asm(_PROF_UNWINDER_SAVE); \
__asm(".cfi_def_cfa_offset 20"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
__asm(".cfi_offset 3, -8"); \
__asm(".cfi_offset 2, -12"); \
__asm(".cfi_offset 1, -16"); \
__asm(".cfi_offset 0, -20"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
__asm("ldr r0, [sp, #20]"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
@@ -161,12 +95,10 @@
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm("pop {r0-r3, ip, lr}"); \
__asm(RET); \
__asm(".cfi_endproc"); \
__asm(".fnend"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#endif
#ifdef _KERNEL
#include <arm/cpufunc.h>
lib/libc/include/arm-netbsd-eabi/machine/setjmp.h
Vendored
+7 -6
View File
@@ -1,4 +1,4 @@
/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */
/* $NetBSD: setjmp.h,v 1.6 2024/05/06 07:29:30 skrll Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
@@ -10,11 +10,12 @@
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and its commercial !).
* (yes really ! and it's commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependent on creator)
* Word Field Comment
* 0 magic number (dependent on creator)
* 13 fpscr vfp status control register
* 14 r4 register 4
* 15 r5 register 5
@@ -47,13 +48,13 @@
* A side note I should mention - Please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be garenteed especially if the compiler happens
* be guaranteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* Whilst this can be seen as encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* is for the best then, if changes occur, compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
lib/libc/include/arm-netbsd-eabi/machine/sysarch.h
Vendored
+85
View File
@@ -0,0 +1,85 @@
/* $NetBSD: sysarch.h,v 1.15 2021/10/06 05:33:15 skrll Exp $ */
/*
* Copyright (c) 1996-1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_SYSARCH_H_
#define _ARM_SYSARCH_H_
#include <sys/cdefs.h>
/*
* Pickup definition of size_t and uintptr_t
*/
#include <machine/ansi.h>
#include <sys/stdint.h>
#ifndef _KERNEL
#include <stdbool.h>
#endif
#ifdef _BSD_SIZE_T_
typedef _BSD_SIZE_T_ size_t;
#undef _BSD_SIZE_T_
#endif
/*
* Architecture specific syscalls (arm)
*/
#define ARM_SYNC_ICACHE 0
#define ARM_DRAIN_WRITEBUF 1
#define ARM_VFP_FPSCR 2
#define ARM_FPU_USED 3
struct arm_sync_icache_args {
uintptr_t addr; /* Virtual start address */
size_t len; /* Region size */
};
struct arm_vfp_fpscr_args {
uint32_t fpscr_clear; /* bits to clear */
uint32_t fpscr_set; /* bits to set */
};
struct arm_unaligned_faults_args {
bool enabled; /* unaligned faults are enabled */
};
#ifndef _KERNEL
__BEGIN_DECLS
int arm_sync_icache(uintptr_t, size_t);
int arm_drain_writebuf(void);
int sysarch(int, void *);
__END_DECLS
#endif
#endif /* !_ARM_SYSARCH_H_ */
lib/libc/include/generic-netbsd/altq/altq.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: altq.h,v 1.4 2006/10/12 19:59:08 peter Exp $ */
/* $NetBSD: altq.h,v 1.5 2024/12/24 08:35:28 ozaki-r Exp $ */
/* $KAME: altq.h,v 1.10 2003/07/10 12:07:47 kjc Exp $ */
/*
@@ -74,7 +74,7 @@ struct altqreq {
/* simple token backet meter profile */
struct tb_profile {
u_int rate; /* rate in bit-per-sec */
uint64_t rate; /* rate in bit-per-sec */
u_int depth; /* depth in bytes */
};
lib/libc/include/generic-netbsd/altq/altq_afmap.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: altq_afmap.h,v 1.3 2006/10/12 19:59:08 peter Exp $ */
/* $NetBSD: altq_afmap.h,v 1.4 2025/01/14 13:49:17 joe Exp $ */
/* $KAME: altq_afmap.h,v 1.6 2002/04/03 05:38:50 kjc Exp $ */
/*
@@ -98,6 +98,7 @@ int afm_remove(struct afm *);
int afm_removeall(struct ifnet *);
struct afm *afm_lookup(struct ifnet *, int, int);
struct afm *afm_match(struct ifnet *, struct flowinfo *);
struct afm_head *afmhead_if(struct ifnet *);
#endif /* _KERNEL */
lib/libc/include/generic-netbsd/altq/altq_classq.h
Vendored
+8 -6
View File
@@ -1,4 +1,4 @@
/* $NetBSD: altq_classq.h,v 1.8 2018/04/19 21:50:06 christos Exp $ */
/* $NetBSD: altq_classq.h,v 1.12 2025/01/22 22:41:38 joe Exp $ */
/* $KAME: altq_classq.h,v 1.6 2003/01/07 07:33:38 kjc Exp $ */
/*
@@ -53,6 +53,8 @@ extern "C" {
#ifdef _KERNEL
#include <sys/cprng.h>
/*
* Packet Queue structures and macros to manipulate them.
*/
@@ -109,14 +111,14 @@ _getq(class_queue_t *q)
struct mbuf *m, *m0;
if ((m = qtail(q)) == NULL)
return (NULL);
return NULL;
if ((m0 = m->m_nextpkt) != m)
m->m_nextpkt = m0->m_nextpkt;
else
qtail(q) = NULL;
qlen(q)--;
m0->m_nextpkt = NULL;
return (m0);
return m0;
}
/* drop a packet at the tail of the queue */
@@ -138,7 +140,7 @@ _getq_tail(class_queue_t *q)
qtail(q) = prev;
qlen(q)--;
m->m_nextpkt = NULL;
return (m);
return m;
}
/* randomly select a packet in the queue */
@@ -155,7 +157,7 @@ _getq_random(class_queue_t *q)
else {
struct mbuf *prev = NULL;
n = random() % qlen(q) + 1;
n = cprng_fast32() % qlen(q) + 1;
for (i = 0; i < n; i++) {
prev = m;
m = m->m_nextpkt;
@@ -166,7 +168,7 @@ _getq_random(class_queue_t *q)
}
qlen(q)--;
m->m_nextpkt = NULL;
return (m);
return m;
}
static __inline void
lib/libc/include/generic-netbsd/altq/altq_jobs.h
Vendored
+37 -37
View File
@@ -1,58 +1,58 @@
/* $NetBSD: altq_jobs.h,v 1.5 2010/04/09 19:32:45 plunky Exp $ */
/* $NetBSD: altq_jobs.h,v 1.6 2025/02/10 19:12:49 joe Exp $ */
/* $KAME: altq_jobs.h,v 1.6 2003/07/10 12:07:48 kjc Exp $ */
/*
* Copyright (c) 2001, Rector and Visitors of the University of
* Copyright (c) 2001, Rector and Visitors of the University of
* Virginia.
* All rights reserved.
*
* Redistribution and use in source and binary forms,
* with or without modification, are permitted provided
* Redistribution and use in source and binary forms,
* with or without modification, are permitted provided
* that the following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* Neither the name of the University of Virginia nor the names
* of its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
* Neither the name of the University of Virginia nor the names
* of its contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* JoBS - altq prototype implementation
*
/*
* JoBS - altq prototype implementation
*
* Author: Nicolas Christin <nicolas@cs.virginia.edu>
*
* JoBS algorithms originally devised and proposed by
* JoBS algorithms originally devised and proposed by
* Nicolas Christin and Jorg Liebeherr.
* Grateful Acknowledgments to Tarek Abdelzaher for his help and
* Grateful Acknowledgments to Tarek Abdelzaher for his help and
* comments, and to Kenjiro Cho for some helpful advice.
* Contributed by the Multimedia Networks Group at the University
* of Virginia.
* of Virginia.
*
* Papers and additional info can be found at
* Papers and additional info can be found at
* http://qosbox.cs.virginia.edu
*
*/
*
*/
#ifndef _ALTQ_ALTQ_JOBS_H_
#define _ALTQ_ALTQ_JOBS_H_
@@ -73,7 +73,7 @@ extern "C" {
/* list of packet arrival times */
struct _tsentry;
typedef TAILQ_HEAD(_timestamps, _tsentry) TSLIST;
typedef TAILQ_HEAD(_timestamps, _tsentry) TSLIST;
typedef struct _tsentry {
TAILQ_ENTRY(_tsentry) ts_list;
uint64_t timestamp;
lib/libc/include/generic-netbsd/altq/altq_rmclass.h
Vendored
+8 -8
View File
@@ -1,4 +1,4 @@
/* $NetBSD: altq_rmclass.h,v 1.13 2022/05/24 20:50:18 andvar Exp $ */
/* $NetBSD: altq_rmclass.h,v 1.14 2025/02/03 07:40:24 ozaki-r Exp $ */
/* $KAME: altq_rmclass.h,v 1.10 2003/08/20 23:30:23 itojun Exp $ */
/*
@@ -82,14 +82,14 @@ struct red;
} while (0)
#define TS_ADD_DELTA(a, delta, res) do { \
register long xxns = (a)->tv_nsec + (long)(delta); \
\
(res)->tv_sec = (a)->tv_sec; \
while (xxns >= 1000000000) { \
++((res)->tv_sec); \
xxns -= 1000000000; \
KASSERT(delta >= 0); \
(res)->tv_sec = (a)->tv_sec + (delta) / 1000000000L; \
(res)->tv_nsec = (a)->tv_nsec + (long)((delta) % 1000000000L); \
if ((res)->tv_nsec >= 1000000000L) { \
(res)->tv_nsec -= 1000000000L; \
(res)->tv_sec++; \
} \
(res)->tv_nsec = xxns; \
KASSERT((res)->tv_nsec >= 0); \
} while (0)
#define RM_TIMEOUT 2 /* 1 Clock tick. */
lib/libc/include/generic-netbsd/altq/altq_var.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: altq_var.h,v 1.12 2008/11/25 15:59:10 tsutsui Exp $ */
/* $NetBSD: altq_var.h,v 1.13 2024/12/07 07:45:43 andvar Exp $ */
/* $KAME: altq_var.h,v 1.18 2005/04/13 03:44:25 suz Exp $ */
/*
@@ -191,7 +191,7 @@ struct callout {
/* dummy callout structure */
struct callout {
void *c_arg; /* function argument */
void (*c_func)(void *); /* functiuon to call */
void (*c_func)(void *); /* function to call */
};
#define CALLOUT_INIT(c) do { (void)memset((c), 0, sizeof(*(c))); } while (/*CONSTCOND*/ 0)
#define CALLOUT_RESET(c,t,f,a) do { (c)->c_arg = (a); \
lib/libc/include/generic-netbsd/arm/arm32/pmap.h
Vendored
+8 -32
View File
@@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.173.4.1 2023/10/14 06:52:17 martin Exp $ */
/* $NetBSD: pmap.h,v 1.177 2023/10/12 11:33:37 skrll Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -79,7 +79,10 @@
#endif
#include <arm/cpufunc.h>
#include <arm/locore.h>
#include <uvm/uvm_object.h>
#include <uvm/pmap/pmap_devmap.h>
#include <uvm/pmap/pmap_pvt.h>
#endif
@@ -91,12 +94,7 @@
#endif
#define PMAP_TLB_FLUSH_ASID_ON_RESET arm_has_tlbiasid_p
#define PMAP_TLB_NUM_PIDS 256
#define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
#if PMAP_TLB_MAX > 1
#define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
#else
#define cpu_tlb_info(ci) (&pmap_tlb0_info)
#endif
#define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1)
#include <uvm/pmap/tlb.h>
#include <uvm/pmap/pmap_tlb.h>
@@ -201,29 +199,10 @@ union pmap_cache_state {
#define PMAP_CACHE_STATE_ALL 0xffffffffu
#endif /* !ARM_MMU_EXTENDED */
/*
* This structure is used by machine-dependent code to describe
* static mappings of devices, created at bootstrap time.
*/
struct pmap_devmap {
vaddr_t pd_va; /* virtual address */
paddr_t pd_pa; /* physical address */
psize_t pd_size; /* size of region */
vm_prot_t pd_prot; /* protection code */
int pd_cache; /* cache attributes */
};
#define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET)
#define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE)
#define DEVMAP_ENTRY(va, pa, sz) \
{ \
.pd_va = DEVMAP_ALIGN(va), \
.pd_pa = DEVMAP_ALIGN(pa), \
.pd_size = DEVMAP_SIZE(sz), \
.pd_prot = VM_PROT_READ|VM_PROT_WRITE, \
.pd_cache = PTE_DEV \
}
#define DEVMAP_ENTRY_END { 0 }
#define DEVMAP_FLAGS PMAP_DEV
/*
* The pmap structure itself
@@ -419,17 +398,14 @@ void pmap_postinit(void);
void vector_page_setprot(int);
const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
/* Bootstrapping routines. */
void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
void pmap_unmap_chunk(vaddr_t, vaddr_t, vsize_t);
void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
void pmap_devmap_register(const struct pmap_devmap *);
vsize_t pmap_kenter_range(vaddr_t, paddr_t, vsize_t, vm_prot_t, u_int);
/*
* Special page zero routine for use by the idle loop (no cache cleans).
lib/libc/include/generic-netbsd/arm/arm32/vmparam.h
Vendored
+5 -5
View File
@@ -1,4 +1,4 @@
/* $NetBSD: vmparam.h,v 1.56 2020/10/08 12:49:06 he Exp $ */
/* $NetBSD: vmparam.h,v 1.58 2024/09/07 06:17:37 andvar Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -54,7 +54,7 @@
#define USRSTACK VM_MAXUSER_ADDRESS
/*
* ARMv4 systems are normaly configured for 256MB KVA only, so restrict
* ARMv4 systems are normally configured for 256MB KVA only, so restrict
* the size of the pager map to 4MB.
*/
#ifndef _ARM_ARCH_5
@@ -131,7 +131,7 @@
#define VM_KERNEL_KASAN_END (VM_KERNEL_KASAN_BASE + VM_KERNEL_KASAN_SIZE)
#define VM_KERNEL_VM_END VM_KERNEL_KASAN_BASE
#else
#define VM_KERNEL_VM_END VM_KERNEL_IO_ADDRESS
#define VM_KERNEL_VM_END VM_KERNEL_IO_BASE
#endif
#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
@@ -146,8 +146,8 @@
#define VM_KERNEL_ADDR_SIZE (VM_KERNEL_VM_END - KERNEL_BASE)
#define VM_KERNEL_VM_SIZE (VM_KERNEL_VM_END - VM_KERNEL_VM_BASE)
#define VM_KERNEL_IO_ADDRESS 0xf0000000
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_ADDRESS)
#define VM_KERNEL_IO_BASE 0xf0000000
#define VM_KERNEL_IO_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_IO_BASE)
#endif
#endif /* _ARM_ARM32_VMPARAM_H_ */
lib/libc/include/generic-netbsd/arm/asm.h
Vendored
+48 -19
View File
@@ -1,4 +1,4 @@
/* $NetBSD: asm.h,v 1.34 2020/04/23 23:22:41 jakllsch Exp $ */
/* $NetBSD: asm.h,v 1.39.2.1 2026/04/02 19:12:03 martin Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -73,8 +73,10 @@
#ifdef __thumb__
#define THUMB_INSN(n) n
#define _INSN_SIZE (2)
#else
#define THUMB_INSN(n)
#define _INSN_SIZE (4)
#endif
#define __BIT(n) (1 << (n))
@@ -130,7 +132,7 @@
#ifdef GPROF
# define _PROF_PROLOGUE \
mov ip, lr; bl __mcount
push {lr}; bl __gnu_mcount_nc
#else
# define _PROF_PROLOGUE
#endif
@@ -194,21 +196,25 @@
#define GOT_GET(x,got,sym) \
ldr x, sym; \
ldr x, [x, got]
#define GOT_INIT(got,gotsym,pclabel) \
ldr got, gotsym; \
pclabel: add got, got, pc
#ifdef __thumb__
#define GOT_INITSYM(gotsym,pclabel) \
/*
* Load _GLOBAL_OFFSET_TABLE_ address into register:
*
* 0: GOT_INIT(rX, .Lgot)
* ...
*
* // and in the data after the function
* GOT_INITSYM(.Lgot, 0b)
*/
#define GOT_INIT(Rgot, gotsym) \
ldr Rgot, gotsym ; \
add Rgot, Rgot, pc
#define GOT_INITSYM(gotsym, initlabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4)
#else
#define GOT_INITSYM(gotsym,pclabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8)
#endif
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (initlabel+(1+2)*_INSN_SIZE)
#ifdef __STDC__
#define PIC_SYM(x,y) x ## ( ## y ## )
#define PIC_SYM(x,y) x(y)
#else
#define PIC_SYM(x,y) x/**/(/**/y/**/)
#endif
@@ -219,15 +225,38 @@
#define GOT_SYM(x) x
#define GOT_GET(x,got,sym) \
ldr x, sym;
#define GOT_INIT(got,gotsym,pclabel)
#define GOT_INITSYM(gotsym,pclabel)
#define GOT_INIT(Rgot, gotsym)
#define GOT_INITSYM(gotsym, initlabel)
#define PIC_SYM(x,y) x
#endif /* __PIC__ */
#define RCSID(x) .pushsection ".ident","MS",%progbits,1; \
.asciz x; \
/*
* Annoyingly, gas on arm seems to generate _two_ NUL-terminated
* strings for
*
* .asciz "foo" "bar"
*
* instead of concatenating it into a single NUL-terminated string as
* on other architectures.
*
* To work around this, we concatenate into a single NUL-terminated by:
*
* .ascii "foo"
* .asciz "bar"
*/
#define _IDENTSTR(x) .pushsection ".ident","MS",%progbits,1; \
x; \
.popsection
#ifdef _NETBSD_REVISIONID
#define RCSID(_s) \
_IDENTSTR(.asciz _s); \
_IDENTSTR(.ascii "$"; .ascii "NetBSD: "; .ascii __FILE__; \
.ascii " "; .ascii _NETBSD_REVISIONID; .asciz " $")
#else
#define RCSID(_s) _IDENTSTR(.asciz _s)
#endif
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
@@ -241,7 +270,7 @@
#ifdef __STDC__
#define WARN_REFERENCES(sym,msg) \
.pushsection .gnu.warning. ## sym; \
.pushsection .gnu.warning.sym; \
.ascii msg; \
.popsection
#else
lib/libc/include/generic-netbsd/arm/byte_swap.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.16 2017/01/17 11:08:50 rin Exp $ */
/* $NetBSD: byte_swap.h,v 1.16.52.1 2025/12/18 19:57:52 martin Exp $ */
/*-
* Copyright (c) 1997, 1999, 2002 The NetBSD Foundation, Inc.
@@ -60,7 +60,7 @@
#else
#ifdef __GNUC__
#include <sys/types.h>
#include <sys/stdint.h>
__BEGIN_DECLS
#define __BYTE_SWAP_U32_VARIABLE __byte_swap_u32_variable
lib/libc/include/generic-netbsd/arm/cpu.h
Vendored
+1 -3
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.123.4.1 2023/08/09 17:42:01 martin Exp $ */
/* $NetBSD: cpu.h,v 1.125 2023/07/11 11:01:18 riastradh Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -236,8 +236,6 @@ struct cpu_info {
uint32_t ci_vfp_id;
uint64_t ci_lastintr;
struct pmap_tlb_info *
ci_tlb_info;
struct pmap * ci_pmap_lastuser;
struct pmap * ci_pmap_cur;
tlb_asid_t ci_pmap_asid_cur;
lib/libc/include/generic-netbsd/arm/cputypes.h
Vendored
+12 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cputypes.h,v 1.16.4.1 2024/10/03 16:11:36 martin Exp $ */
/* $NetBSD: cputypes.h,v 1.20 2025/01/31 11:47:34 jmcneill Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -50,6 +50,7 @@
#define CPU_ID_BROADCOM 0x42000000 /* 'B' */
#define CPU_ID_CAVIUM 0x43000000 /* 'C' */
#define CPU_ID_DEC 0x44000000 /* 'D' */
#define CPU_ID_FUJITSU 0x46000000 /* 'F' */
#define CPU_ID_INFINEON 0x49000000 /* 'I' */
#define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */
#define CPU_ID_NVIDIA 0x4e000000 /* 'N' */
@@ -177,6 +178,11 @@
#define CPU_ID_NEOVERSEN1R3 0x413fd0c0
#define CPU_ID_NEOVERSEE1R1 0x411fd4a0
#define CPU_ID_CORTEXA77R0 0x410fd0d0
#define CPU_ID_NEOVERSEV1R1 0x411fd400
#define CPU_ID_CORTEXA710R2 0x412fd470
#define CPU_ID_NEOVERSEN2R0 0x410fd490
#define CPU_ID_CORTEXA520R0 0x410fd800
#define CPU_ID_CORTEXA720R0 0x410fd810
#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
@@ -209,9 +215,14 @@
#define CPU_ID_THUNDERX83XXRX 0x43000a30
#define CPU_ID_THUNDERX2RX 0x43000af0
#define CPU_ID_A64FX 0x460f0010
#define CPU_ID_AMPERE1 0xc00fac30
#define CPU_ID_AMPERE1A 0xc00fac40
#define CPU_ID_ORYON 0x510f0010
#define CPU_ID_ORYON_P(n) ((n & 0xff0ffff0) == CPU_ID_ORYON)
/*
* Chip-specific errata. These defines are intended to be
* booleans used within if statements. When an appropriate
lib/libc/include/generic-netbsd/arm/float.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: float.h,v 1.8 2014/01/29 01:10:36 matt Exp $ */
/* $NetBSD: float.h,v 1.9 2024/10/30 15:56:11 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -33,6 +33,7 @@
#define _ARM_FLOAT_H_
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#ifdef __ARM_PCS_AAPCS64
lib/libc/include/generic-netbsd/arm/lwp_private.h
Vendored
+81
View File
@@ -0,0 +1,81 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:07 christos Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_LWP_PRIVATE_H_
#define _ARM_LWP_PRIVATE_H_
#include <sys/cdefs.h>
#include <sys/tls.h>
#include <lwp.h>
#if defined(__aarch64__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
void *__tpidr;
__asm __volatile("mrs\t%0, tpidr_el0" : "=r"(__tpidr));
return __tpidr;
}
__END_DECLS
#elif defined(__arm__)
#if defined(__thumb__) && !defined(_ARM_ARCH_T2)
#include <arm/eabi.h>
#endif
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
if (__predict_true(rv))
return rv;
/*
* Some ARM cores are broken and don't raise an undefined fault when an
* unrecogized mrc instruction is encountered, but just return zero.
* To do deal with that, if we get a zero we (re-)fetch the value using
* syscall.
*/
return _lwp_getprivate();
#else
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
__END_DECLS
#endif
#endif /* !_ARM_LWP_PRIVATE_H_ */
lib/libc/include/generic-netbsd/arm/mcontext.h
Vendored
+5 -51
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mcontext.h,v 1.23 2021/10/06 05:33:15 skrll Exp $ */
/* $NetBSD: mcontext.h,v 1.27 2024/11/30 01:04:07 christos Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -210,61 +210,15 @@ typedef struct {
#endif
#if defined(_RTLD_SOURCE) || defined(_LIBC_SOURCE) || \
defined(__LIBPTHREAD_SOURCE__)
#include <sys/tls.h>
#if defined(__aarch64__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
void *__tpidr;
__asm __volatile("mrs\t%0, tpidr_el0" : "=r"(__tpidr));
return __tpidr;
}
__END_DECLS
#elif defined(__arm__)
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
extern void *_lwp_getprivate(void);
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
if (__predict_true(rv))
return rv;
/*
* Some ARM cores are broken and don't raise an undefined fault when an
* unrecogized mrc instruction is encountered, but just return zero.
* To do deal with that, if we get a zero we (re-)fetch the value using
* syscall.
*/
return _lwp_getprivate();
#else
extern void *__aeabi_read_tp(void);
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
__END_DECLS
#endif
#endif /* _RTLD_SOURCE || _LIBC_SOURCE || __LIBPTHREAD_SOURCE__ */
/* Machine-dependent uc_flags */
#define _UC_TLSBASE 0x00080000 /* see <sys/ucontext.h> */
#define _UC_TLSBASE _UC_MD_BIT19 /* see <sys/ucontext.h> */
/* Machine-dependent uc_flags for arm */
#define _UC_ARM_VFP 0x00010000 /* FPU field is VFP */
#define _UC_ARM_VFP _UC_MD_BIT16 /* FPU field is VFP */
/* used by signal delivery to indicate status of signal stack */
#define _UC_SETSTACK 0x00020000
#define _UC_CLRSTACK 0x00040000
#define _UC_SETSTACK _UC_MD_BIT17
#define _UC_CLRSTACK _UC_MD_BIT18
#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_FP])
lib/libc/include/generic-netbsd/arm/mutex.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mutex.h,v 1.27.4.1 2023/08/09 17:42:01 martin Exp $ */
/* $NetBSD: mutex.h,v 1.29 2023/07/12 12:50:12 riastradh Exp $ */
/*-
* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
lib/libc/include/generic-netbsd/arm/proc.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: proc.h,v 1.19 2020/08/14 16:18:36 skrll Exp $ */
/* $NetBSD: proc.h,v 1.20 2024/02/10 18:43:51 andvar Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
@@ -48,7 +48,7 @@ struct mdlwp {
volatile uint32_t md_astpending;
};
/* Flags setttings for md_flags */
/* Flags settings for md_flags */
#define MDLWP_NOALIGNFLT 0x00000002 /* For EXEC_AOUT */
#define MDLWP_VFPINTR 0x00000004 /* VFP used in intr */
lib/libc/include/generic-netbsd/arm/profile.h
Vendored
+28 -96
View File
@@ -1,4 +1,4 @@
/* $NetBSD: profile.h,v 1.18 2018/01/24 09:04:45 skrll Exp $ */
/* $NetBSD: profile.h,v 1.18.42.1 2026/04/02 19:12:03 martin Exp $ */
/*
* Copyright (c) 2001 Ben Harris
@@ -38,90 +38,25 @@
* prologue.
*/
#define MCOUNT_ASM_NAME "__mcount"
#define PLTSYM
#if !defined(__ARM_EABI__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
/* Check what mode we're in. EQ => 32, NE => 26 */ \
__asm("teq r0, r0"); \
__asm("teq pc, r15"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("moveq r0, ip"); \
__asm("bicne r0, ip, #0xfc000003"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("moveq r1, lr"); \
__asm("bicne r1, lr, #0xfc000003"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#elif defined(__ARM_DWARF_EH__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".cfi_endproc"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#if defined (_ARM_ARCH_4T)
# define RET "bx ip"
#else
# define RET "mov pc, ip"
#endif
#if defined(__ARM_DWARF_EH__)
#define _PROF_UNWINDER_SAVE ""
#define _PROF_UNWINDER_START ""
#define _PROF_UNWINDER_END ""
#else
#define _PROF_UNWINDER_SAVE ".save {r0-r3, lr}\n"
#define _PROF_UNWINDER_START ".fnstart\n"
#define _PROF_UNWINDER_END ".fnend\n"
#endif
#define MCOUNT_ASM_NAME "__gnu_mcount_nc"
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
@@ -129,27 +64,26 @@
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".fnstart"); \
__asm(_PROF_UNWINDER_START); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".save {r0-r3, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm("push {r0-r3, lr}"); \
__asm(_PROF_UNWINDER_SAVE); \
__asm(".cfi_def_cfa_offset 20"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
__asm(".cfi_offset 3, -8"); \
__asm(".cfi_offset 2, -12"); \
__asm(".cfi_offset 1, -16"); \
__asm(".cfi_offset 0, -20"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
__asm("ldr r0, [sp, #20]"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
@@ -161,12 +95,10 @@
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm("pop {r0-r3, ip, lr}"); \
__asm(RET); \
__asm(".cfi_endproc"); \
__asm(".fnend"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#endif
#ifdef _KERNEL
#include <arm/cpufunc.h>
lib/libc/include/generic-netbsd/arm/setjmp.h
Vendored
+7 -6
View File
@@ -1,4 +1,4 @@
/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */
/* $NetBSD: setjmp.h,v 1.6 2024/05/06 07:29:30 skrll Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
@@ -10,11 +10,12 @@
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and its commercial !).
* (yes really ! and it's commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependent on creator)
* Word Field Comment
* 0 magic number (dependent on creator)
* 13 fpscr vfp status control register
* 14 r4 register 4
* 15 r5 register 5
@@ -47,13 +48,13 @@
* A side note I should mention - Please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be garenteed especially if the compiler happens
* be guaranteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* Whilst this can be seen as encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* is for the best then, if changes occur, compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
lib/libc/include/generic-netbsd/arpa/nameser.h
Vendored
+3 -3
View File
@@ -1,4 +1,4 @@
/* $NetBSD: nameser.h,v 1.27 2021/12/08 20:50:01 andvar Exp $ */
/* $NetBSD: nameser.h,v 1.29 2025/07/15 22:15:04 andvar Exp $ */
/*
* Portions Copyright (C) 2004, 2005, 2008, 2009 Internet Systems Consortium, Inc. ("ISC")
@@ -343,7 +343,7 @@ typedef enum __ns_type {
ns_t_rrsig = 46, /*%< RRset Signature */
ns_t_nsec = 47, /*%< Negative security */
ns_t_dnskey = 48, /*%< DNS Key */
ns_t_dhcid = 49, /*%< Dynamic host configuratin identifier */
ns_t_dhcid = 49, /*%< Dynamic host configuration identifier */
ns_t_nsec3 = 50, /*%< Negative security type 3 */
ns_t_nsec3param = 51, /*%< Negative security type 3 parameters */
ns_t_hip = 55, /*%< Host Identity Protocol */
@@ -356,7 +356,7 @@ typedef enum __ns_type {
ns_t_maila = 254, /*%< Transfer mail agent records. */
ns_t_any = 255, /*%< Wildcard match. */
ns_t_zxfr = 256, /*%< BIND-specific, nonstandard. */
ns_t_dlv = 32769, /*%< DNSSEC look-aside validatation. */
ns_t_dlv = 32769, /*%< DNSSEC look-aside validation. */
ns_t_max = 65536
} ns_type;
lib/libc/include/generic-netbsd/arpa/nameser_compat.h
Vendored
+3 -3
View File
@@ -1,4 +1,4 @@
/* $NetBSD: nameser_compat.h,v 1.9 2022/04/21 04:03:54 gutteridge Exp $ */
/* $NetBSD: nameser_compat.h,v 1.10 2024/02/05 21:46:05 andvar Exp $ */
/* Copyright (c) 1983, 1989
* The Regents of the University of California. All rights reserved.
@@ -64,7 +64,7 @@ typedef struct {
/* fields in third byte */
unsigned qr: 1; /*%< response flag */
unsigned opcode: 4; /*%< purpose of message */
unsigned aa: 1; /*%< authoritive answer */
unsigned aa: 1; /*%< authoritative answer */
unsigned tc: 1; /*%< truncated message */
unsigned rd: 1; /*%< recursion desired */
/* fields in fourth byte */
@@ -78,7 +78,7 @@ typedef struct {
/* fields in third byte */
unsigned rd :1; /*%< recursion desired */
unsigned tc :1; /*%< truncated message */
unsigned aa :1; /*%< authoritive answer */
unsigned aa :1; /*%< authoritative answer */
unsigned opcode :4; /*%< purpose of message */
unsigned qr :1; /*%< response flag */
/* fields in fourth byte */
lib/libc/include/generic-netbsd/assert.h
Vendored
+12 -22
View File
@@ -1,4 +1,4 @@
/* $NetBSD: assert.h,v 1.25 2020/04/17 15:22:34 kamil Exp $ */
/* $NetBSD: assert.h,v 1.27 2025/03/29 01:43:38 riastradh Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -48,46 +48,36 @@
#undef assert
#ifdef NDEBUG
# ifndef __lint__
# define assert(e) (__static_cast(void,0))
# else /* !__lint__ */
# define assert(e)
# endif /* __lint__ */
# define assert(e) (__static_cast(void,0))
#else /* !NDEBUG */
# if __STDC__
# define assert(e) \
((e) ? __static_cast(void,0) : __assert13(__FILE__, __LINE__, \
__assert_function__, #e))
(__predict_true(e) ? __static_cast(void,0) \
: __assert13(__FILE__, __LINE__, __assert_function__, #e))
# else /* PCC */
# define assert(e) \
((e) ? __static_cast(void,0) : __assert13(__FILE__, __LINE__, \
__assert_function__, "e"))
(__predict_true(e) ? __static_cast(void,0) \
: __assert13(__FILE__, __LINE__, __assert_function__, "e"))
# endif /* !__STDC__ */
#endif /* NDEBUG */
#undef _DIAGASSERT
#if !defined(_DIAGNOSTIC)
# if !defined(__lint__)
# define _DIAGASSERT(e) (__static_cast(void,0))
# else /* !__lint__ */
# define _DIAGASSERT(e)
# endif /* __lint__ */
# define _DIAGASSERT(e) (__static_cast(void,0))
#else /* _DIAGNOSTIC */
# if __STDC__
# define _DIAGASSERT(e) \
((e) ? __static_cast(void,0) : __diagassert13(__FILE__, __LINE__, \
__assert_function__, #e))
(__predict_true(e) ? __static_cast(void,0) \
: __diagassert13(__FILE__, __LINE__, __assert_function__, #e))
# else /* !__STDC__ */
# define _DIAGASSERT(e) \
((e) ? __static_cast(void,0) : __diagassert13(__FILE__, __LINE__, \
__assert_function__, "e"))
(__predict_true(e) ? __static_cast(void,0) \
: __diagassert13(__FILE__, __LINE__, __assert_function__, "e"))
# endif
#endif /* _DIAGNOSTIC */
#if defined(__lint__)
#define __assert_function__ (__static_cast(const void *,0))
#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#define __assert_function__ __func__
#elif __GNUC_PREREQ__(2, 6)
#define __assert_function__ __PRETTY_FUNCTION__
lib/libc/include/generic-netbsd/bitstring.h
Vendored
+5 -5
View File
@@ -1,4 +1,4 @@
/* $NetBSD: bitstring.h,v 1.14 2016/03/17 02:25:32 christos Exp $ */
/* $NetBSD: bitstring.h,v 1.15 2024/05/12 10:41:23 rillig Exp $ */
/*
* Copyright (c) 1989, 1993
@@ -98,7 +98,7 @@ typedef unsigned char bitstr_t;
bit_clear(_name, _start); \
_start++; \
} \
} while(/*CONSTCOND*/0)
} while (0)
/* set bits start ... stop in bitstring */
#define bit_nset(name, start, stop) do { \
@@ -108,7 +108,7 @@ typedef unsigned char bitstr_t;
bit_set(_name, _start); \
_start++; \
} \
} while(/*CONSTCOND*/0)
} while (0)
/* find first bit clear in name */
#define bit_ffc(name, nbits, value) do { \
@@ -121,7 +121,7 @@ typedef unsigned char bitstr_t;
break; \
} \
*(value) = _value; \
} while(/*CONSTCOND*/0)
} while (0)
/* find first bit set in name */
#define bit_ffs(name, nbits, value) do { \
@@ -134,6 +134,6 @@ typedef unsigned char bitstr_t;
break; \
} \
*(value) = _value; \
} while(/*CONSTCOND*/0)
} while (0)
#endif /* !_BITSTRING_H_ */
lib/libc/include/generic-netbsd/cdbw.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cdbw.h,v 1.2 2012/06/03 21:21:45 joerg Exp $ */
/* $NetBSD: cdbw.h,v 1.3 2023/08/08 10:34:08 riastradh Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -50,7 +50,7 @@ int cdbw_put_data(struct cdbw *, const void *, size_t,
int cdbw_put_key(struct cdbw *, const void *, size_t,
uint32_t);
uint32_t cdbw_stable_seeder(void);
int cdbw_output(struct cdbw *, int, const char[16],
int cdbw_output(struct cdbw *, int, const char *,
uint32_t (*)(void));
void cdbw_close(struct cdbw *);
lib/libc/include/generic-netbsd/crypto/cryptodev.h
Vendored
+99 -92
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cryptodev.h,v 1.50.4.1 2023/08/09 17:42:03 martin Exp $ */
/* $NetBSD: cryptodev.h,v 1.51.8.1 2026/05/07 14:40:13 martin Exp $ */
/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.2.2.6 2003/07/02 17:04:50 sam Exp $ */
/* $OpenBSD: cryptodev.h,v 1.33 2002/07/17 23:52:39 art Exp $ */
@@ -159,48 +159,48 @@
#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */
struct session_op {
u_int32_t cipher; /* ie. CRYPTO_DES_CBC */
u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */
u_int32_t comp_alg; /* ie. CRYPTO_GZIP_COMP */
uint32_t cipher; /* ie. CRYPTO_DES_CBC */
uint32_t mac; /* ie. CRYPTO_MD5_HMAC */
uint32_t comp_alg; /* ie. CRYPTO_GZIP_COMP */
u_int32_t keylen; /* cipher key */
uint32_t keylen; /* cipher key */
void * key;
int mackeylen; /* mac key */
uint32_t mackeylen; /* mac key */
void * mackey;
u_int32_t ses; /* returns: session # */
uint32_t ses; /* returns: session # */
};
/* to support multiple session creation */
struct session_n_op {
u_int32_t cipher; /* ie. CRYPTO_DES_CBC */
u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */
u_int32_t comp_alg; /* ie. CRYPTO_GZIP_COMP */
uint32_t cipher; /* ie. CRYPTO_DES_CBC */
uint32_t mac; /* ie. CRYPTO_MD5_HMAC */
uint32_t comp_alg; /* ie. CRYPTO_GZIP_COMP */
u_int32_t keylen; /* cipher key */
uint32_t keylen; /* cipher key */
void * key;
int mackeylen; /* mac key */
uint32_t mackeylen; /* mac key */
void * mackey;
u_int32_t ses; /* returns: session # */
uint32_t ses; /* returns: session # */
int status;
};
struct crypt_op {
u_int32_t ses;
u_int16_t op; /* i.e. COP_ENCRYPT */
uint32_t ses;
uint16_t op; /* i.e. COP_ENCRYPT */
#define COP_ENCRYPT 1
#define COP_DECRYPT 2
#define COP_COMP 3
#define COP_DECOMP 4
u_int16_t flags;
uint16_t flags;
#define COP_F_BATCH 0x0008 /* Dispatch as quickly as possible */
u_int len; /* src len */
uint32_t len; /* src len */
void * src, *dst; /* become iov[] inside kernel */
void * mac; /* must be big enough for chosen MAC */
void * iv;
u_int dst_len; /* dst len if not 0 */
uint32_t dst_len; /* dst len if not 0 */
};
/* to support multiple session creation */
@@ -219,27 +219,27 @@ struct crypt_op {
*/
struct crypt_n_op {
u_int32_t ses;
u_int16_t op; /* i.e. COP_ENCRYPT */
uint32_t ses;
uint16_t op; /* i.e. COP_ENCRYPT */
#define COP_ENCRYPT 1
#define COP_DECRYPT 2
u_int16_t flags;
uint16_t flags;
#define COP_F_BATCH 0x0008 /* Dispatch as quickly as possible */
#define COP_F_MORE 0x0010 /* more data to follow */
u_int len; /* src len */
uint32_t len; /* src len */
u_int32_t reqid; /* request id */
uint32_t reqid; /* request id */
int status; /* status of request -accepted or not */
void *opaque; /* opaque pointer returned to user */
u_int32_t keylen; /* cipher key - optional */
uint32_t keylen; /* cipher key - optional */
void * key;
u_int32_t mackeylen; /* also optional */
uint32_t mackeylen; /* also optional */
void * mackey;
void * src, *dst; /* become iov[] inside kernel */
void * mac; /* must be big enough for chosen MAC */
void * iv;
u_int dst_len; /* dst len if not 0 */
uint32_t dst_len; /* dst len if not 0 */
};
/* CIOCNCRYPTM ioctl argument, supporting one or more asynchronous
@@ -255,7 +255,7 @@ struct crypt_mop {
struct crypt_sfop {
size_t count;
u_int32_t *sesid;
uint32_t *sesid;
};
struct crypt_sgop {
@@ -268,17 +268,17 @@ struct crypt_sgop {
/* bignum parameter, in packed bytes, ... */
struct crparam {
void * crp_p;
u_int crp_nbits;
uint32_t crp_nbits;
};
#define CRK_MAXPARAM 8
struct crypt_kop {
u_int crk_op; /* ie. CRK_MOD_EXP or other */
u_int crk_status; /* return status */
u_short crk_iparams; /* # of input parameters */
u_short crk_oparams; /* # of output parameters */
u_int crk_pad1;
uint32_t crk_op; /* ie. CRK_MOD_EXP or other */
uint32_t crk_status; /* return status */
uint16_t crk_iparams; /* # of input parameters */
uint16_t crk_oparams; /* # of output parameters */
uint32_t crk_pad1;
struct crparam crk_param[CRK_MAXPARAM];
};
@@ -295,11 +295,11 @@ struct crypt_kop {
* user application.
*/
struct crypt_n_kop {
u_int crk_op; /* ie. CRK_MOD_EXP or other */
u_int crk_status; /* return status */
u_short crk_iparams; /* # of input parameters */
u_short crk_oparams; /* # of output parameters */
u_int32_t crk_reqid; /* request id */
uint32_t crk_op; /* ie. CRK_MOD_EXP or other */
uint32_t crk_status; /* return status */
uint16_t crk_iparams; /* # of input parameters */
uint16_t crk_oparams; /* # of output parameters */
uint32_t crk_reqid; /* request id */
struct crparam crk_param[CRK_MAXPARAM];
void *crk_opaque; /* opaque pointer returned to user */
};
@@ -314,8 +314,8 @@ struct crypt_mkop {
* not in the original crypt_kop structure (crk_status).
*/
struct crypt_result {
u_int32_t reqid; /* request id */
u_int32_t status; /* status of request: 0 if successful */
uint32_t reqid; /* request id */
uint32_t status; /* status of request: 0 if successful */
void * opaque; /* Opaque pointer from the user, passed along */
};
@@ -364,10 +364,10 @@ struct cryptret {
* Please use F_SETFD against the cloned descriptor. But this ioctl
* is obsolete (the device now clones): please, just don't use it.
*/
#define CRIOGET _IOWR('c', 100, u_int32_t)
#define CRIOGET _IOWR('c', 100, uint32_t)
/* the following are done against the cloned descriptor */
#define CIOCFSESSION _IOW('c', 102, u_int32_t)
#define CIOCFSESSION _IOW('c', 102, uint32_t)
#define CIOCKEY _IOWR('c', 104, struct crypt_kop)
#define CIOCNFKEYM _IOWR('c', 108, struct crypt_mkop)
#define CIOCNFSESSION _IOW('c', 109, struct crypt_sfop)
@@ -379,24 +379,24 @@ struct cryptret {
#define CIOCCRYPT _IOWR('c', 114, struct crypt_op)
#define CIOCNCRYPTM _IOWR('c', 115, struct crypt_mop)
#define CIOCASYMFEAT _IOR('c', 105, u_int32_t)
#define CIOCASYMFEAT _IOR('c', 105, uint32_t)
struct cryptotstat {
struct timespec acc; /* total accumulated time */
struct timespec min; /* max time */
struct timespec max; /* max time */
u_int32_t count; /* number of observations */
uint32_t count; /* number of observations */
};
struct cryptostats {
u_int32_t cs_ops; /* symmetric crypto ops submitted */
u_int32_t cs_errs; /* symmetric crypto ops that failed */
u_int32_t cs_kops; /* asymmetric/key ops submitted */
u_int32_t cs_kerrs; /* asymmetric/key ops that failed */
u_int32_t cs_intrs; /* crypto swi thread activations */
u_int32_t cs_rets; /* crypto return thread activations */
u_int32_t cs_blocks; /* symmetric op driver block */
u_int32_t cs_kblocks; /* symmetric op driver block */
uint32_t cs_ops; /* symmetric crypto ops submitted */
uint32_t cs_errs; /* symmetric crypto ops that failed */
uint32_t cs_kops; /* asymmetric/key ops submitted */
uint32_t cs_kerrs; /* asymmetric/key ops that failed */
uint32_t cs_intrs; /* crypto swi thread activations */
uint32_t cs_rets; /* crypto return thread activations */
uint32_t cs_blocks; /* symmetric op driver block */
uint32_t cs_kblocks; /* symmetric op driver block */
/*
* When CRYPTO_TIMING is defined at compile time and the
* sysctl debug.crypto is set to 1, the crypto system will
@@ -423,18 +423,18 @@ struct uio;
/* Standard initialization structure beginning */
struct cryptoini {
int cri_alg; /* Algorithm to use */
int cri_klen; /* Key length, in bits */
int cri_rnd; /* Algorithm rounds, where relevant */
uint32_t cri_klen; /* Key length, in bits */
uint32_t cri_rnd; /* Algorithm rounds, where relevant */
char *cri_key; /* key to use */
u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */
uint8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */
struct cryptoini *cri_next;
};
/* Describe boundaries of a single crypto operation */
struct cryptodesc {
int crd_skip; /* How many bytes to ignore from start */
int crd_len; /* How many bytes to process */
int crd_inject; /* Where to inject results, if applicable */
uint32_t crd_skip; /* How many bytes to ignore from start */
uint32_t crd_len; /* How many bytes to process */
uint32_t crd_inject; /* Where to inject results, if applicable */
int crd_flags;
#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */
@@ -454,13 +454,20 @@ struct cryptodesc {
struct cryptodesc *crd_next;
};
struct cryptop_data {
struct csession *cse;
struct iovec iovec[1]; /* user requests never have more */
struct uio uio;
size_t iov_len;
};
/* Structure describing complete operation */
struct cryptop {
TAILQ_ENTRY(cryptop) crp_next;
u_int64_t crp_sid; /* Session ID */
uint64_t crp_sid; /* Session ID */
int crp_ilen; /* Input data total length */
int crp_olen; /* Result total length */
uint32_t crp_ilen; /* Input data total length */
uint32_t crp_olen; /* Result total length */
int crp_etype; /*
* Error type (zero means no error).
@@ -505,19 +512,18 @@ struct cryptop {
/*
* everything below is private to crypto(4)
*/
u_int32_t crp_reqid; /* request id */
uint32_t crp_reqid; /* request id */
void * crp_usropaque; /* Opaque pointer from user, passed along */
struct timespec crp_tstamp; /* performance time stamp */
kcondvar_t crp_cv;
struct fcrypt *fcrp;
void * dst;
void * mac;
u_int len;
uint32_t len;
u_char tmp_iv[EALG_MAX_BLOCK_LEN];
u_char tmp_mac[CRYPTO_MAX_MAC_LEN];
struct iovec iovec[1];
struct uio uio;
struct cryptop_data cod;
uint32_t magic;
struct cpu_info *reqcpu; /*
* save requested CPU to do cryptoret
@@ -540,14 +546,15 @@ struct cryptop {
struct cryptkop {
TAILQ_ENTRY(cryptkop) krp_next;
u_int32_t krp_reqid; /* request id */
uint32_t krp_reqid; /* request id */
void * krp_usropaque; /* Opaque pointer from user, passed along */
u_int krp_op; /* ie. CRK_MOD_EXP or other */
u_int krp_status; /* return status */
u_short krp_iparams; /* # of input parameters */
u_short krp_oparams; /* # of output parameters */
u_int32_t krp_hid;
uint32_t krp_op; /* ie. CRK_MOD_EXP or other */
uint32_t krp_status; /* return status */
uint16_t krp_iparams; /* # of input parameters */
uint16_t krp_oparams; /* # of output parameters */
uint32_t krp_hid;
kmutex_t krp_lock;
struct crparam krp_param[CRK_MAXPARAM]; /* kvm */
void (*krp_callback)(struct cryptkop *); /*
* Callback function.
@@ -564,29 +571,29 @@ struct cryptkop {
/* Crypto capabilities structure */
struct cryptocap {
u_int32_t cc_sessions;
uint32_t cc_sessions;
/*
* Largest possible operator length (in bits) for each type of
* encryption algorithm.
*/
u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1];
uint16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1];
u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1];
uint8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1];
u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1];
uint8_t cc_kalg[CRK_ALGORITHM_MAX + 1];
u_int8_t cc_flags;
u_int8_t cc_qblocked; /* symmetric q blocked */
u_int8_t cc_kqblocked; /* asymmetric q blocked */
uint8_t cc_flags;
uint8_t cc_qblocked; /* symmetric q blocked */
uint8_t cc_kqblocked; /* asymmetric q blocked */
#define CRYPTOCAP_F_CLEANUP 0x01 /* needs resource cleanup */
#define CRYPTOCAP_F_SOFTWARE 0x02 /* software implementation */
#define CRYPTOCAP_F_SYNC 0x04 /* operates synchronously */
void *cc_arg; /* callback argument */
int (*cc_newsession)(void*, u_int32_t*, struct cryptoini*);
int (*cc_newsession)(void*, uint32_t*, struct cryptoini*);
int (*cc_process) (void*, struct cryptop *, int);
void (*cc_freesession) (void *, u_int64_t);
void (*cc_freesession) (void *, uint64_t);
void *cc_karg; /* callback argument */
int (*cc_kprocess) (void*, struct cryptkop *, int);
@@ -602,29 +609,29 @@ struct cryptocap {
*/
#define CRYPTO_SESID2HID(_sid) ((((_sid) >> 32) & 0xffffff) - 1)
#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 56) & 0xff)
#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff)
#define CRYPTO_SESID2LID(_sid) (((uint32_t) (_sid)) & 0xffffffff)
MALLOC_DECLARE(M_CRYPTO_DATA);
extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard);
extern void crypto_freesession(u_int64_t sid);
extern int32_t crypto_get_driverid(u_int32_t flags);
extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen,
u_int32_t flags,
int (*newses)(void*, u_int32_t*, struct cryptoini*),
void (*freeses)(void *, u_int64_t),
extern int crypto_newsession(uint64_t *sid, struct cryptoini *cri, int hard);
extern void crypto_freesession(uint64_t sid);
extern int32_t crypto_get_driverid(uint32_t flags);
extern int crypto_register(uint32_t driverid, int alg, uint16_t maxoplen,
uint32_t flags,
int (*newses)(void*, uint32_t*, struct cryptoini*),
void (*freeses)(void *, uint64_t),
int (*process)(void*, struct cryptop *, int),
void *arg);
extern int crypto_kregister(u_int32_t, int, u_int32_t,
extern int crypto_kregister(uint32_t, int, uint32_t,
int (*)(void*, struct cryptkop *, int),
void *arg);
extern int crypto_unregister(u_int32_t driverid, int alg);
extern int crypto_unregister_all(u_int32_t driverid);
extern int crypto_unregister(uint32_t driverid, int alg);
extern int crypto_unregister_all(uint32_t driverid);
extern void crypto_dispatch(struct cryptop *crp);
extern void crypto_kdispatch(struct cryptkop *);
#define CRYPTO_SYMQ 0x1
#define CRYPTO_ASYMQ 0x2
extern int crypto_unblock(u_int32_t, int);
extern int crypto_unblock(uint32_t, int);
extern void crypto_done(struct cryptop *crp);
extern void crypto_kdone(struct cryptkop *);
extern int crypto_getfeat(int *);
lib/libc/include/generic-netbsd/dev/i2c/emcfaninfo.h
Vendored
+234
View File
@@ -0,0 +1,234 @@
/* $NetBSD: emcfaninfo.h,v 1.1 2025/03/11 13:56:46 brad Exp $ */
/*
* Copyright (c) 2025 Brad Spencer <brad@anduin.eldar.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _DEV_I2C_EMCFANINFO_H_
#define _DEV_I2C_EMCFANINFO_H_
#include <sys/gpio.h>
struct emcfan_chip_info {
const int family; /* The EMC chipset family, 210X or 230X */
const uint8_t product_id; /* The product ID as read from the chip */
const char *name; /* What we are calling this chip */
const int num_tachs; /* The number of tachometers */
const int num_fans; /* The number of fans. This may be different than the number of tachometers. */
const uint8_t fan_drive_registers[5]; /* The registers used to drive the fans, one for each */
const uint8_t fan_divider_registers[5]; /* The divider registers, one for each possible fan */
const bool internal_temp_zone; /* Does the chip have an internal temperature zone */
const int num_external_temp_zones; /* The number of external temperature zones except for ones that are VIN4 */
const bool vin4_temp_zone; /* Does the chip have a VIN4 temperature zone */
const int num_gpio_pins; /* The number of gpio pins that this chip has */
const int gpio_pin_ability[6]; /* The abilities for each gpio pin */
const char *gpio_names[6]; /* The default names of the gpio pins */
const uint64_t register_void[4]; /* 4 64 bit values that specify if a particular register is valid */
};
static struct emcfan_chip_info emcfan_chip_infos[] = {
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2101,
.name = "EMC2101",
.num_tachs = 1,
.num_fans = 1,
.fan_drive_registers = { EMCFAN_2101_FAN_DRIVE },
.fan_divider_registers = { EMCFAN_2101_FAN_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 1,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b0000000000000000000000000000001000000011110111111111111110111111,
.register_void[1] = 0b0000000000000000000000000000000011111111111111111111111111000000,
.register_void[2] = 0b1000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1110000000000000000000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2101R,
.name = "EMC2101-R",
.num_tachs = 1,
.num_fans = 1,
.fan_drive_registers = { EMCFAN_2101_FAN_DRIVE },
.fan_divider_registers = { EMCFAN_2101_FAN_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 1,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b0000000000000000000000000000001000000011110111111111111110111111,
.register_void[1] = 0b0000000000000000000000000000000011111111111111111111111111000000,
.register_void[2] = 0b1000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1110000000000000000000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2103_1,
.name = "EMC2103-1",
.num_tachs = 1,
.num_fans = 1,
.fan_drive_registers = { EMCFAN_210_346_FAN_1_DRIVE },
.fan_divider_registers = { EMCFAN_210_346_FAN_1_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 1,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b0001000100010001000011111111101110100010100100110011010000001111,
.register_void[1] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1111000000000000100000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2103_24,
.name = "EMC2103-2/4",
.num_tachs = 1,
.num_fans = 1,
.fan_drive_registers = { EMCFAN_210_346_FAN_1_DRIVE },
.fan_divider_registers = { EMCFAN_210_346_FAN_1_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 3,
.vin4_temp_zone = false,
.num_gpio_pins = 2,
.gpio_pin_ability = {
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL
},
.gpio_names = { "GPIO1", "GPIO2" },
.register_void[0] = 0b0001011100010111000011111111101110101110101101110011010011111111,
.register_void[1] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1111000000000000100000000111111000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2104,
.name = "EMC2104",
.num_tachs = 2,
.num_fans = 2,
.fan_drive_registers = { EMCFAN_210_346_FAN_1_DRIVE, EMCFAN_210_346_FAN_2_DRIVE },
.fan_divider_registers = { EMCFAN_210_346_FAN_1_DIVIDE, EMCFAN_210_346_FAN_1_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 4,
.vin4_temp_zone = true,
.num_gpio_pins = 3,
.gpio_pin_ability = {
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0
},
.gpio_names = { "CLK_IN / GPIO1", "TACH2 / GPIO2", "PWM2 / GPIO3" },
.register_void[0] = 0b0011111100111111000011111111111110111111111100011111011111111111,
.register_void[1] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[2] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[3] = 0b1111000000000000100000000111111100000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_210X,
.product_id = EMCFAN_PRODUCT_2106,
.name = "EMC2106",
.num_tachs = 2,
.num_fans = 4,
.fan_drive_registers = { EMCFAN_210_346_FAN_1_DRIVE, EMCFAN_210_346_FAN_2_DRIVE, EMCFAN_2106_FAN_3_DRIVE, EMCFAN_2106_FAN_4_DRIVE },
.fan_divider_registers = { EMCFAN_210_346_FAN_1_DIVIDE, EMCFAN_210_346_FAN_1_DIVIDE, EMCFAN_2106_FAN_3_DIVIDE, EMCFAN_2106_FAN_4_DIVIDE },
.internal_temp_zone = true,
.num_external_temp_zones = 4,
.vin4_temp_zone = true,
.num_gpio_pins = 6,
.gpio_pin_ability = {
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0 | GPIO_PIN_ALT1,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | GPIO_PIN_ALT0 | GPIO_PIN_ALT1,
GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL
},
.gpio_names = { "CLK_IN / GPIO1", "TACH2 / GPIO2", "PWM2 / GPIO3", "OVERT2 / GPIO4 / PWM3", "OVERT3 / GPIO5 / PWM4", "GPIO6" },
.register_void[0] = 0b0011111100111111111111111111111110111111111100011111011111111111,
.register_void[1] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[2] = 0b0000001111111111111111111111111111111111111111111111111111101111,
.register_void[3] = 0b1111000000000000100000000111111100000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_230X,
.product_id = EMCFAN_PRODUCT_2301,
.name = "EMC2301",
.num_tachs = 1,
.num_fans = 1,
.fan_drive_registers = { EMCFAN_230X_FAN_1_DRIVE },
.fan_divider_registers = { EMCFAN_230X_FAN_1_DIVIDE },
.internal_temp_zone = false,
.num_external_temp_zones = 0,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b1111111111101111001111101111000100000000000000000000000000000000,
.register_void[1] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1110000000000000100000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_230X,
.product_id = EMCFAN_PRODUCT_2302,
.name = "EMC2302",
.num_tachs = 2,
.num_fans = 2,
.fan_drive_registers = { EMCFAN_230X_FAN_1_DRIVE, EMCFAN_230X_FAN_2_DRIVE },
.fan_divider_registers = { EMCFAN_230X_FAN_1_DIVIDE, EMCFAN_230X_FAN_2_DIVIDE },
.internal_temp_zone = false,
.num_external_temp_zones = 0,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b1111111111101111001111101111000100000000000000000000000000000000,
.register_void[1] = 0b0000000000000000000000000000000000000000000000001111111111101111,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1110000000000000100000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_230X,
.product_id = EMCFAN_PRODUCT_2303,
.name = "EMC2303",
.num_tachs = 3,
.num_fans = 3,
.fan_drive_registers = { EMCFAN_230X_FAN_1_DRIVE, EMCFAN_230X_FAN_2_DRIVE, EMCFAN_230X_FAN_3_DRIVE },
.fan_divider_registers = { EMCFAN_230X_FAN_1_DIVIDE, EMCFAN_230X_FAN_2_DIVIDE, EMCFAN_230X_FAN_3_DIVIDE },
.internal_temp_zone = false,
.num_external_temp_zones = 0,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b1111111111101111001111101111000100000000000000000000000000000000,
.register_void[1] = 0b0000000000000000000000000000000011111111111011111111111111101111,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1111000000000000100000000000000000000000000000000000000000000000,
},
{
.family = EMCFAN_FAMILY_230X,
.product_id = EMCFAN_PRODUCT_2305,
.name = "EMC2305",
.num_tachs = 5,
.num_fans = 5,
.fan_drive_registers = { EMCFAN_230X_FAN_1_DRIVE, EMCFAN_230X_FAN_2_DRIVE, EMCFAN_230X_FAN_3_DRIVE, EMCFAN_230X_FAN_4_DRIVE, EMCFAN_230X_FAN_5_DRIVE },
.fan_divider_registers = { EMCFAN_230X_FAN_1_DIVIDE, EMCFAN_230X_FAN_2_DIVIDE, EMCFAN_230X_FAN_3_DIVIDE, EMCFAN_230X_FAN_4_DIVIDE, EMCFAN_230X_FAN_5_DIVIDE },
.internal_temp_zone = false,
.num_external_temp_zones = 0,
.vin4_temp_zone = false,
.num_gpio_pins = 0,
.register_void[0] = 0b1111111111101111001111101111000100000000000000000000000000000000,
.register_void[1] = 0b1111111111101111111111111110111111111111111011111111111111101111,
.register_void[2] = 0b0000000000000000000000000000000000000000000000000000000000000000,
.register_void[3] = 0b1111000000000000100000000000000000000000000000000000000000000000,
}
};
#endif
lib/libc/include/generic-netbsd/dev/i2c/emcfanreg.h
Vendored
+127
View File
@@ -0,0 +1,127 @@
/* $NetBSD: emcfanreg.h,v 1.1 2025/03/11 13:56:46 brad Exp $ */
/*
* Copyright (c) 2025 Brad Spencer <brad@anduin.eldar.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _DEV_I2C_EMCFANREG_H_
#define _DEV_I2C_EMCFANREG_H_
#include <dev/i2c/i2c_io.h>
static const i2c_addr_t emcfan_typical_addrs[] = { 0x2c, 0x2d, 0x2e, 0x2f, 0x4c, 0x4d };
#define EMCFAN_VOID_READ 0x55
#define EMCFAN_INTERNAL_TEMP_HIGH 0x00
#define EMCFAN_INTERNAL_TEMP_LOW 0x01
#define EMCFAN_2101_EXTERNAL_TEMP_HIGH 0x01
#define EMCFAN_2101_CHIP_CONFIG 0x03
#define EMCFAN_EXTERNAL_1_TEMP_HIGH 0x02
#define EMCFAN_2101_EXTERNAL_TEMP_LOW 0x10
#define EMCFAN_EXTERNAL_1_TEMP_LOW 0x03
#define EMCFAN_EXTERNAL_2_TEMP_HIGH 0x04
#define EMCFAN_EXTERNAL_2_TEMP_LOW 0x05
#define EMCFAN_EXTERNAL_3_TEMP_HIGH 0x06
#define EMCFAN_EXTERNAL_3_TEMP_LOW 0x07
#define EMCFAN_EXTERNAL_4_TEMP_HIGH 0x08
#define EMCFAN_EXTERNAL_4_TEMP_LOW 0x09
#define EMCFAN_VIN4_VOLTAGE 0x10
#define EMCFAN_CHIP_CONFIG 0x20
#define EMCFAN_CHIP_CONFIG_2 0x21
#define EMCFAN_TEMP_CONFIG_3 0x22
#define EMCFAN_210_346_FAN_STATUS 0x27
#define EMCFAN_POLARITY_CONFIG 0x2a
#define EMCFAN_210_346_PWM_BASEFREQ 0x2b
#define EMCFAN_2106_FAN_3_DIVIDE 0x2c
#define EMCFAN_2106_FAN_3_DRIVE 0x2d
#define EMCFAN_2106_FAN_4_DRIVE 0x2e
#define EMCFAN_2106_FAN_4_DIVIDE 0x2f
#define EMCFAN_2101_TACH_LOW 0x46
#define EMCFAN_2101_TACH_HIGH 0x47
#define EMCFAN_2101_FAN_CONFIG 0x4a
#define EMCFAN_2101_FAN_DRIVE 0x4c
#define EMCFAN_2101_FAN_DIVIDE 0x4e
#define EMCFAN_210_346_FAN_1_DRIVE 0x40
#define EMCFAN_210_346_FAN_1_DIVIDE 0x41
#define EMCFAN_210_346_CONFIG_1 0x42
#define EMCFAN_210_346_TACH_1_HIGH 0x4e
#define EMCFAN_210_346_TACH_1_LOW 0x4f
#define EMCFAN_210_346_CONFIG_2 0x82
#define EMCFAN_210_346_FAN_2_DRIVE 0x80
#define EMCFAN_210_346_FAN_2_DIVIDE 0x81
#define EMCFAN_210_346_TACH_2_HIGH 0x8e
#define EMCFAN_210_346_TACH_2_LOW 0x8f
#define EMCFAN_230X_FAN_STATUS 0x24
#define EMCFAN_230X_FAN_STALL_STATUS 0x25
#define EMCFAN_230X_FAN_SPIN_STATUS 0x26
#define EMCFAN_230X_FAN_DRIVE_STATUS 0x27
#define EMCFAN_230X_OUTPUT_CONFIG 0x2b
#define EMCFAN_230X_BASE_FREQ_45 0x2c
#define EMCFAN_230X_BASE_FREQ_123 0x2d
#define EMCFAN_230X_FAN_1_DRIVE 0x30
#define EMCFAN_230X_FAN_1_DIVIDE 0x31
#define EMCFAN_230X_CONFIG_1 0x32
#define EMCFAN_230X_TACH_1_HIGH 0x3e
#define EMCFAN_230X_TACH_1_LOW 0x3f
#define EMCFAN_230X_FAN_2_DRIVE 0x40
#define EMCFAN_230X_FAN_2_DIVIDE 0x41
#define EMCFAN_230X_CONFIG_2 0x42
#define EMCFAN_230X_TACH_2_HIGH 0x4e
#define EMCFAN_230X_TACH_2_LOW 0x4f
#define EMCFAN_230X_FAN_3_DRIVE 0x50
#define EMCFAN_230X_FAN_3_DIVIDE 0x51
#define EMCFAN_230X_CONFIG_3 0x52
#define EMCFAN_230X_TACH_3_HIGH 0x5e
#define EMCFAN_230X_TACH_3_LOW 0x5f
#define EMCFAN_230X_FAN_4_DRIVE 0x60
#define EMCFAN_230X_FAN_4_DIVIDE 0x61
#define EMCFAN_230X_CONFIG_4 0x62
#define EMCFAN_230X_TACH_4_HIGH 0x6e
#define EMCFAN_230X_TACH_4_LOW 0x6f
#define EMCFAN_230X_FAN_5_DRIVE 0x70
#define EMCFAN_230X_FAN_5_DIVIDE 0x71
#define EMCFAN_230X_CONFIG_5 0x72
#define EMCFAN_230X_TACH_5_HIGH 0x7e
#define EMCFAN_230X_TACH_5_LOW 0x7f
#define EMCFAN_PRODUCT_ID 0xfd
#define EMCFAN_PRODUCT_2101 0x16
#define EMCFAN_PRODUCT_2101R 0x28
#define EMCFAN_PRODUCT_2103_1 0x24
#define EMCFAN_PRODUCT_2103_24 0x26 /* EMC2103-2 and EMC2103-4 */
#define EMCFAN_PRODUCT_2104 0x1d
#define EMCFAN_PRODUCT_2106 0x1e
#define EMCFAN_PRODUCT_2305 0x34
#define EMCFAN_PRODUCT_2303 0x35
#define EMCFAN_PRODUCT_2302 0x36
#define EMCFAN_PRODUCT_2301 0x37
#define EMCFAN_MUX_PINS 0xe0
#define EMCFAN_DIR_PINS 0xe1
#define EMCFAN_OUTPUT_PIN_CONFIG 0xe2
#define EMCFAN_PINS_INPUT 0xe3
#define EMCFAN_PINS_OUTPUT 0xe4
#define EMCFAN_MANUFACTURER_ID 0xfe
#define EMCFAN_VALID_MANUFACTURER_ID 0x5d
#define EMCFAN_REVISION 0xff
#define EMCFAN_FAMILY_210X 1
#define EMCFAN_FAMILY_230X 2
#endif
lib/libc/include/generic-netbsd/dev/i2o/i2o.h
Vendored
+3 -366
View File
@@ -1,4 +1,4 @@
/* $NetBSD: i2o.h,v 1.17 2022/05/30 09:56:04 andvar Exp $ */
/* $NetBSD: i2o.h,v 1.18 2023/09/07 20:03:25 ad Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -32,7 +32,8 @@
/*
* Structures and constants, as presented by the I2O specification revision
* 1.5 (obtainable from http://www.intelligent-io.com/). Currently, only
* what's useful to us is defined in this file.
* what's useful to us is defined in this file. LAN defs used to be here
* but were removed as they're useless.
*/
#ifndef _I2O_I2O_H_
@@ -681,11 +682,6 @@ struct i2o_util_event_register_reply {
#define I2O_EVENT_EXEC_MODIFIED_LCT 0x00000200
#define I2O_EVENT_EXEC_DDM_AVAILIBILITY 0x00000400
/* LAN class events. */
#define I2O_EVENT_LAN_LINK_DOWN 0x00000001
#define I2O_EVENT_LAN_LINK_UP 0x00000002
#define I2O_EVENT_LAN_MEDIA_CHANGE 0x00000004
/*
* ================= Utility parameter groups =================
*/
@@ -1006,363 +1002,4 @@ struct i2o_param_scsi_device_info {
u_int64_t negsyncrate;
} __packed;
/*
* ================= LAN class messages =================
*/
#define I2O_LAN_PACKET_SEND 0x3b
struct i2o_lan_packet_send {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int32_t tcw;
/* SGL follows */
} __packed;
#define I2O_LAN_TCW_ACCESS_PRI_MASK 0x00000007
#define I2O_LAN_TCW_SUPPRESS_CRC 0x00000008
#define I2O_LAN_TCW_SUPPRESS_LOOPBACK 0x00000010
#define I2O_LAN_TCW_CKSUM_NETWORK 0x00000020
#define I2O_LAN_TCW_CKSUM_TRANSPORT 0x00000040
#define I2O_LAN_TCW_REPLY_BATCH 0x00000000
#define I2O_LAN_TCW_REPLY_IMMEDIATELY 0x40000000
#define I2O_LAN_TCW_REPLY_UNSUCCESSFUL 0x80000000
#define I2O_LAN_TCW_REPLY_NONE 0xc0000000
#define I2O_LAN_SDU_SEND 0x3d
struct i2o_lan_sdu_send {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int32_t tcw; /* As per PACKET_SEND. */
/* SGL follows */
} __packed;
struct i2o_lan_send_reply {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int32_t trl;
u_int16_t detail;
u_int8_t reserved;
u_int8_t reqstatus;
u_int32_t tctx[1];
} __packed;
#define I2O_LAN_RECEIVE_POST 0x3e
struct i2o_lan_receive_post {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int32_t bktcnt;
/* SGL follows */
} __packed;
struct i2o_lan_receive_reply {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int8_t trlcount;
u_int8_t trlesize;
u_int8_t reserved;
u_int8_t trlflags;
u_int32_t bucketsleft;
} __packed;
#define I2O_LAN_RECEIVE_REPLY_PDB 0x80
#define I2O_LAN_PDB_ERROR_NONE 0x00
#define I2O_LAN_PDB_ERROR_BAD_CRC 0x01
#define I2O_LAN_PDB_ERROR_ALIGNMENT 0x02
#define I2O_LAN_PDB_ERROR_TOO_LONG 0x03
#define I2O_LAN_PDB_ERROR_TOO_SHORT 0x04
#define I2O_LAN_PDB_ERROR_RX_OVERRUN 0x05
#define I2O_LAN_PDB_ERROR_L3_CKSUM_BAD 0x40
#define I2O_LAN_PDB_ERROR_L4_CKSUM_BAD 0x80
#define I2O_LAN_PDB_ERROR_CKSUM_MASK 0xc0
#define I2O_LAN_PDB_ERROR_OTHER 0xff
#define I2O_LAN_RESET 0x35
struct i2o_lan_reset {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int16_t reserved;
u_int16_t resrcflags;
} __packed;
#define I2O_LAN_RESRC_RETURN_BUCKETS 0x0001
#define I2O_LAN_RESRC_RETURN_XMITS 0x0002
#define I2O_LAN_SUSPEND 0x37
struct i2o_lan_suspend {
u_int32_t msgflags;
u_int32_t msgfunc;
u_int32_t msgictx;
u_int16_t reserved;
u_int16_t resrcflags; /* As per RESET. */
} __packed;
#define I2O_LAN_DSC_SUCCESS 0x00
#define I2O_LAN_DSC_DEVICE_FAILURE 0x01
#define I2O_LAN_DSC_DESTINATION_NOT_FOUND 0x02
#define I2O_LAN_DSC_TRANSMIT_ERROR 0x03
#define I2O_LAN_DSC_TRANSMIT_ABORTED 0x04
#define I2O_LAN_DSC_RECEIVE_ERROR 0x05
#define I2O_LAN_DSC_RECEIVE_ABORTED 0x06
#define I2O_LAN_DSC_DMA_ERROR 0x07
#define I2O_LAN_DSC_BAD_PACKET_DETECTED 0x08
#define I2O_LAN_DSC_OUT_OF_MEMORY 0x09
#define I2O_LAN_DSC_BUCKET_OVERRUN 0x0a
#define I2O_LAN_DSC_IOP_INTERNAL_ERROR 0x0b
#define I2O_LAN_DSC_CANCELED 0x0c
#define I2O_LAN_DSC_INVALID_TRANSACTION_CONTEXT 0x0d
#define I2O_LAN_DSC_DEST_ADDRESS_DETECTED 0x0e
#define I2O_LAN_DSC_DEST_ADDRESS_OMITTED 0x0f
#define I2O_LAN_DSC_PARTIAL_PACKET_RETURNED 0x10
#define I2O_LAN_DSC_TEMP_SUSPENDED_STATE 0x11
/*
* ================= LAN class parameter groups =================
*/
#define I2O_PARAM_LAN_DEVICE_INFO 0x0000
struct i2o_param_lan_device_info {
u_int16_t lantype;
u_int16_t flags;
u_int8_t addrfmt;
u_int8_t reserved1;
u_int16_t reserved2;
u_int32_t minpktsize;
u_int32_t maxpktsize;
u_int8_t hwaddr[8];
u_int64_t maxtxbps;
u_int64_t maxrxbps;
} __packed;
#define I2O_LAN_TYPE_ETHERNET 0x0030
#define I2O_LAN_TYPE_100BASEVG 0x0040
#define I2O_LAN_TYPE_TOKEN_RING 0x0050
#define I2O_LAN_TYPE_FDDI 0x0060
#define I2O_LAN_TYPE_FIBRECHANNEL 0x0070
#define I2O_PARAM_LAN_MAC_ADDRESS 0x0001
struct i2o_param_lan_mac_address {
u_int8_t activeaddr[8];
u_int8_t localaddr[8];
u_int8_t addrmask[8];
u_int32_t filtermask;
u_int32_t hwfiltercaps;
u_int32_t maxmcastaddr;
u_int32_t maxfilterperfect;
u_int32_t maxfilterimperfect;
} __packed;
#define I2O_PARAM_LAN_MAC_ADDRESS_activeaddr 0
#define I2O_PARAM_LAN_MAC_ADDRESS_localaddr 1
#define I2O_PARAM_LAN_MAC_ADDRESS_addrmask 2
#define I2O_PARAM_LAN_MAC_ADDRESS_filtermask 3
#define I2O_PARAM_LAN_MAC_ADDRESS_hwfiltercaps 4
#define I2O_PARAM_LAN_MAC_ADDRESS_maxmcastaddr 5
#define I2O_PARAM_LAN_MAC_ADDRESS_maxfilterperfect 6
#define I2O_PARAM_LAN_MAC_ADDRESS_maxfilterimperfect 7
#define I2O_LAN_FILTERMASK_UNICAST_DISABLE 0x0001
#define I2O_LAN_FILTERMASK_PROMISC_ENABLE 0x0002
#define I2O_LAN_FILTERMASK_PROMISC_MCAST_ENABLE 0x0004
#define I2O_LAN_FILTERMASK_BROADCAST_DISABLE 0x0100
#define I2O_LAN_FILTERMASK_MCAST_DISABLE 0x0200
#define I2O_LAN_FILTERMASK_FUNCADDR_DISABLE 0x0400
#define I2O_LAN_FILTERMASK_MACMODE_0 0x0800
#define I2O_LAN_FILTERMASK_MACMODE_1 0x1000
#define I2O_PARAM_LAN_MCAST_MAC_ADDRESS 0x0002
/*
* This one's a table, not a scalar.
*/
#define I2O_PARAM_LAN_BATCH_CONTROL 0x0003
struct i2o_param_lan_batch_control {
u_int32_t batchflags;
u_int32_t risingloaddly; /* 1.5 only */
u_int32_t risingloadthresh; /* 1.5 only */
u_int32_t fallingloaddly; /* 1.5 only */
u_int32_t fallingloadthresh; /* 1.5 only */
u_int32_t maxrxbatchcount;
u_int32_t maxrxbatchdelay;
u_int32_t maxtxbatchdelay; /* 2.0 (conflict with 1.5) */
u_int32_t maxtxbatchcount; /* 2.0 only */
} __packed;
#define I2O_PARAM_LAN_BATCH_CONTROL_batchflags 0
#define I2O_PARAM_LAN_BATCH_CONTROL_risingloaddly 1
#define I2O_PARAM_LAN_BATCH_CONTROL_risingloadthresh 2
#define I2O_PARAM_LAN_BATCH_CONTROL_fallingloaddly 3
#define I2O_PARAM_LAN_BATCH_CONTROL_fallingloadthresh 4
#define I2O_PARAM_LAN_BATCH_CONTROL_maxrxbatchcount 5
#define I2O_PARAM_LAN_BATCH_CONTROL_maxrxbatchdelay 6
#define I2O_PARAM_LAN_BATCH_CONTROL_maxtxbatchdelay 7
#define I2O_PARAM_LAN_BATCH_CONTROL_maxtxbatchcount 8
#define I2O_PARAM_LAN_OPERATION 0x0004
struct i2o_param_lan_operation {
u_int32_t pktprepad;
u_int32_t userflags;
u_int32_t pktorphanlimit;
u_int32_t txmodesenable; /* 2.0 only */
u_int32_t rxmodesenable; /* 2.0 only */
} __packed;
#define I2O_PARAM_LAN_OPERATION_pktprepad 0
#define I2O_PARAM_LAN_OPERATION_userflags 1
#define I2O_PARAM_LAN_OPERATION_pktorphanlimit 2
#define I2O_PARAM_LAN_OPERATION_txmodesenable 3
#define I2O_PARAM_LAN_OPERATION_rxmodesenable 4
#define I2O_PARAM_LAN_MEDIA_OPERATION 0x0005
struct i2o_param_lan_media_operation {
u_int32_t connectortype;
u_int32_t connectiontype;
u_int32_t curtxbps;
u_int32_t currxbps;
u_int8_t fullduplex;
u_int8_t linkstatus;
u_int8_t badpkthandling; /* v1.5 only */
u_int8_t duplextarget; /* v2.0 only */
u_int32_t connectortarget; /* v2.0 only */
u_int32_t connectiontarget; /* v2.0 only */
} __packed;
#define I2O_PARAM_LAN_MEDIA_OPERATION_connectortype 0
#define I2O_PARAM_LAN_MEDIA_OPERATION_connectiontype 1
#define I2O_PARAM_LAN_MEDIA_OPERATION_curtxbps 2
#define I2O_PARAM_LAN_MEDIA_OPERATION_currxbps 3
#define I2O_PARAM_LAN_MEDIA_OPERATION_fullduplex 4
#define I2O_PARAM_LAN_MEDIA_OPERATION_linkstatus 5
#define I2O_PARAM_LAN_MEDIA_OPERATION_badpkthandling 6
#define I2O_PARAM_LAN_MEDIA_OPERATION_duplextarget 7
#define I2O_PARAM_LAN_MEDIA_OPERATION_connectortarget 8
#define I2O_PARAM_LAN_MEDIA_OPERATION_connectiontarget 9
#define I2O_LAN_CONNECTOR_OTHER 0x00
#define I2O_LAN_CONNECTOR_UNKNOWN 0x01
#define I2O_LAN_CONNECTOR_AUI 0x02
#define I2O_LAN_CONNECTOR_UTP 0x03
#define I2O_LAN_CONNECTOR_BNC 0x04
#define I2O_LAN_CONNECTOR_RJ45 0x05
#define I2O_LAN_CONNECTOR_STP_DB9 0x06
#define I2O_LAN_CONNECTOR_FIBER_MIC 0x07
#define I2O_LAN_CONNECTOR_APPLE_AUI 0x08
#define I2O_LAN_CONNECTOR_MII 0x09
#define I2O_LAN_CONNECTOR_COPPER_DB9 0x0a
#define I2O_LAN_CONNECTOR_COPPER_AW 0x0b
#define I2O_LAN_CONNECTOR_OPTICAL_LW 0x0c
#define I2O_LAN_CONNECTOR_SIP 0x0d
#define I2O_LAN_CONNECTOR_OPTICAL_SW 0x0e
#define I2O_LAN_CONNECTION_UNKNOWN 0x0000
#define I2O_LAN_CONNECTION_ETHERNET_AUI 0x0301
#define I2O_LAN_CONNECTION_ETHERNET_10BASE5 0x0302
#define I2O_LAN_CONNECTION_ETHERNET_FOIRL 0x0303
#define I2O_LAN_CONNECTION_ETHERNET_10BASE2 0x0304
#define I2O_LAN_CONNECTION_ETHERNET_10BROAD36 0x0305
#define I2O_LAN_CONNECTION_ETHERNET_10BASET 0x0306
#define I2O_LAN_CONNECTION_ETHERNET_10BASEFP 0x0307
#define I2O_LAN_CONNECTION_ETHERNET_10BASEFB 0x0308
#define I2O_LAN_CONNECTION_ETHERNET_10BASEFL 0x0309
#define I2O_LAN_CONNECTION_ETHERNET_100BASETX 0x030a
#define I2O_LAN_CONNECTION_ETHERNET_100BASEFX 0x030b
#define I2O_LAN_CONNECTION_ETHERNET_100BASET4 0x030c
#define I2O_LAN_CONNECTION_ETHERNET_1000BASESX 0x030d
#define I2O_LAN_CONNECTION_ETHERNET_1000BASELX 0x030e
#define I2O_LAN_CONNECTION_ETHERNET_1000BASECX 0x030f
#define I2O_LAN_CONNECTION_ETHERNET_1000BASET 0x0310
#define I2O_LAN_CONNECTION_100BASEVG_ETHERNET 0x0401
#define I2O_LAN_CONNECTION_100BASEVG_TOKEN_RING 0x0402
#define I2O_LAN_CONNECTION_TOKEN_RING_4MBIT 0x0501
#define I2O_LAN_CONNECTION_TOKEN_RING_16MBIT 0x0502
#define I2O_LAN_CONNECTION_FDDI_125MBIT 0x0601
#define I2O_LAN_CONNECTION_FIBRECHANNEL_P2P 0x0701
#define I2O_LAN_CONNECTION_FIBRECHANNEL_AL 0x0702
#define I2O_LAN_CONNECTION_FIBRECHANNEL_PL 0x0703
#define I2O_LAN_CONNECTION_FIBRECHANNEL_F 0x0704
#define I2O_LAN_CONNECTION_OTHER_EMULATED 0x0f00
#define I2O_LAN_CONNECTION_OTHER_OTHER 0x0f01
#define I2O_LAN_CONNECTION_DEFAULT 0xffffffff
#define I2O_PARAM_LAN_TRANSMIT_INFO 0x0007
struct i2o_param_lan_transmit_info {
u_int32_t maxpktsg;
u_int32_t maxchainsg;
u_int32_t maxoutstanding;
u_int32_t maxpktsout;
u_int32_t maxpktsreq;
u_int32_t txmodes;
} __packed;
#define I2O_LAN_MODES_NO_DA_IN_SGL 0x0002
#define I2O_LAN_MODES_CRC_SUPPRESSION 0x0004
#define I2O_LAN_MODES_LOOPBACK_SUPPRESSION 0x0004 /* 1.5 only */
#define I2O_LAN_MODES_FCS_RECEPTION 0x0008 /* 2.0 only */
#define I2O_LAN_MODES_MAC_INSERTION 0x0010
#define I2O_LAN_MODES_RIF_INSERTION 0x0020
#define I2O_LAN_MODES_IPV4_CHECKSUM 0x0100 /* 2.0 only */
#define I2O_LAN_MODES_TCP_CHECKSUM 0x0200 /* 2.0 only */
#define I2O_LAN_MODES_UDP_CHECKSUM 0x0400 /* 2.0 only */
#define I2O_LAN_MODES_RSVP_CHECKSUM 0x0800 /* 2.0 only */
#define I2O_LAN_MODES_ICMP_CHECKSUM 0x1000 /* 2.0 only */
#define I2O_PARAM_LAN_RECEIVE_INFO 0x0008
struct i2o_param_lan_receive_info {
u_int32_t maxchain;
u_int32_t maxbuckets;
} __packed;
#define I2O_PARAM_LAN_STATS 0x0009
struct i2o_param_lan_stats {
u_int64_t opackets;
u_int64_t obytes;
u_int64_t ipackets;
u_int64_t oerrors;
u_int64_t ierrors;
u_int64_t rxnobuffer;
u_int64_t resetcount;
} __packed;
#define I2O_PARAM_LAN_802_3_STATS 0x0200
struct i2o_param_lan_802_3_stats {
u_int64_t alignmenterror;
u_int64_t onecollision;
u_int64_t manycollisions;
u_int64_t deferred;
u_int64_t latecollision;
u_int64_t maxcollisions;
u_int64_t carrierlost;
u_int64_t excessivedeferrals;
} __packed;
#define I2O_PARAM_LAN_FDDI_STATS 0x0400
struct i2o_param_lan_fddi_stats {
u_int64_t configstate;
u_int64_t upstreamnode;
u_int64_t downstreamnode;
u_int64_t frameerrors;
u_int64_t frameslost;
u_int64_t ringmgmtstate;
u_int64_t lctfailures;
u_int64_t lemrejects;
u_int64_t lemcount;
u_int64_t lconnectionstate;
} __packed;
#endif /* !defined _I2O_I2O_H_ */
lib/libc/include/generic-netbsd/dev/ic/hd44780var.h
Vendored
+3 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: hd44780var.h,v 1.8 2015/09/06 06:01:00 dholland Exp $ */
/* $NetBSD: hd44780var.h,v 1.11 2023/08/08 17:31:13 nat Exp $ */
/*
* Copyright (c) 2002 Dennis I. Chernoivanov
@@ -97,6 +97,7 @@ struct hd44780_chip {
#define HD_UP 0x10 /* if set, lcd has been initialized */
#define HD_TIMEDOUT 0x20 /* lcd has recently stopped talking */
#define HD_MULTICHIP 0x40 /* two HD44780 controllers (4-line) */
#define HD_WRITEONLY 0x80 /* write only if set */
uint8_t sc_flags;
uint8_t sc_cols; /* visible columns */
@@ -136,6 +137,7 @@ struct hd44780_chip {
(sc)->sc_readreg((sc), (en), 1)
void hd44780_attach_subr(struct hd44780_chip *);
void hd44780_detach(struct hd44780_chip *);
void hd44780_busy_wait(struct hd44780_chip *, uint32_t);
int hd44780_init(struct hd44780_chip *);
int hd44780_chipinit(struct hd44780_chip *, uint32_t);
lib/libc/include/generic-netbsd/dev/ic/scmdreg.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: scmdreg.h,v 1.2 2022/05/21 19:07:23 andvar Exp $ */
/* $NetBSD: scmdreg.h,v 1.3 2023/04/05 21:53:56 andvar Exp $ */
/*
* Copyright (c) 2021 Brad Spencer <brad@anduin.eldar.org>
@@ -222,7 +222,7 @@
#define SCMD_LAST_REG SCMD_REG_REM_READ /* The last register address on a module */
#define SCMD_REG_SIZE 0x7F /* Size of the register space including the holes */
#define SCMD_REMOTE_ADDR_LOW 0x50 /* The first remote I2C addreess */
#define SCMD_REMOTE_ADDR_LOW 0x50 /* The first remote I2C address */
#define SCMD_REMOTE_ADDR_HIGH 0x5F /* The last remote I2C address */
#define SCMD_HOLE_VALUE 0x55 /* Artificial value on read for a hole register */
#define SCMD_IS_HOLE(r) \
lib/libc/include/generic-netbsd/dev/ic/stireg.h
Vendored
+777
View File
@@ -0,0 +1,777 @@
/* $NetBSD: stireg.h,v 1.18 2025/05/30 13:42:33 tsutsui Exp $ */
/* $OpenBSD: stireg.h,v 1.14 2015/04/05 23:25:57 miod Exp $ */
/*
* Copyright (c) 2000 Michael Shalayeff
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _IC_STIREG_H_
#define _IC_STIREG_H_
/* #define STIDEBUG */
#define STI_REGION_MAX 8
#define STI_MONITOR_MAX 256
#define STI_DEVNAME_LEN 32
#define STI_NCMAP 256
/* code ROM definitions */
#define STI_BEGIN 0
#define STI_INIT_GRAPH 0
#define STI_STATE_MGMT 1
#define STI_FONT_UNPMV 2
#define STI_BLOCK_MOVE 3
#define STI_SELF_TEST 4
#define STI_EXCEP_HDLR 5
#define STI_INQ_CONF 6
#define STI_SCM_ENT 7
#define STI_DMA_CTRL 8
#define STI_FLOW_CTRL 9
#define STI_UTIMING 10
#define STI_PROC_MGR 11
#define STI_UTIL 12
#define STI_END 13
#define STI_CODECNT 16
#define STI_CODEBASE_MAIN 0x40
#define STI_CODEBASE_ALT 0x80
#define STI_CODEBASE_PA STI_CODEBASE_MAIN
#define STI_CODEBASE_M68K STI_CODEBASE_ALT
#define STI_CODEBASE_PA64 STI_CODEBASE_ALT
/* sti returns */
#define STI_OK 0
#define STI_FAIL -1
#define STI_NRDY 1
/* sti errno */
#define STI_NOERRNO 0 /* no error */
#define STI_BADREENTLVL 1 /* bad reentry level */
#define STI_NOREGIONSDEF 2 /* region table is not setup */
#define STI_ILLNPLANES 3 /* invalid num of text planes */
#define STI_ILLINDEX 4 /* invalid font index */
#define STI_ILLLOC 5 /* invalid font location */
#define STI_ILLCOLOUR 6 /* invalid colour */
#define STI_ILLBLKMVFROM 7 /* invalid from in blkmv */
#define STI_ILLBLKMVTO 8 /* invalid to in blkmv */
#define STI_ILLBLKMVSIZE 9 /* invalid size in blkmv */
#define STI_BEIUNSUPP 10 /* bus error ints unsupported */
#define STI_UNXPBE 11 /* unexpected bus error */
#define STI_UNXHWF 12 /* unexpected hardware failure */
#define STI_NEGCFG 13 /* no ext global config struct */
#define STI_NEIG 14 /* no ext init struct */
#define STI_ILLSCME 15 /* invalid set cmap entry */
#define STI_ILLCMVAL 16 /* invalid cmap value */
#define STI_NORESMEM 17 /* no requested global memory */
#define STI_RESMEMCORR 18 /* reserved memory corrupted */
#define STI_ILLNTBLKMV 19 /* invalid non-text blkmv */
#define STI_ILLMONITOR 20 /* monitor selection is out of range */
#define STI_ILLEXCADDR 21 /* invalid excpt handler addr */
#define STI_ILLEXCFLAGS 22 /* invalid excpt handler flags */
#define STI_NOEHE 23 /* no ext exhdl struct */
#define STI_NOINQCE 24 /* no ext inq cfg struct */
#define STI_ILLRGNPTR 25 /* invalid region pointer */
#define STI_ILLUTLOP 26 /* invalid util opcode */
#define STI_UNKNOWN 250 /* unknown error */
#define STI_NOCFGPTR 251 /* no config ptr defined */
#define STI_NOFLPTR 252 /* no flag ptr defined */
#define STI_NOINPTR 253 /* no in ptr defined */
#define STI_NOOUTPTR 254 /* no way you can get it */
#define STI_NOLOCK 255 /* kernel dishonour graphics lock */
/* colours */
#define STI_COLOUR_BLACK 0
#define STI_COLOUR_WHITE 1
#define STI_COLOUR_RED 2
#define STI_COLOUR_YELLOW 3
#define STI_COLOUR_GREEN 4
#define STI_COLOUR_CYAN 5
#define STI_COLOUR_BLUE 6
#define STI_COLOUR_MAGENTA 7
/* LSB high */
struct sti_dd {
uint32_t dd_type; /* 0x00 device type */
#define STI_DEVTYPE1 1
#define STI_DEVTYPE4 3
uint8_t dd_unused;
uint8_t dd_nmon; /* 0x05 number monitor rates */
uint8_t dd_grrev; /* 0x06 global rom revision */
uint8_t dd_lrrev; /* 0x07 local rom revision */
uint32_t dd_grid[2]; /* 0x08 graphics id */
#define STI_DD_CRX 0x26D1482A /* single-head CRX */
#define STI_DD_GRX 0x26D1488C /* gray-scale GRX */
#define STI_DD_CRX24 0x26D148EE /* CRX+ */
#define STI_DD_382C 0x27134C8E /* 382 on-board mid-res */
#define STI_DD_EVRX 0x27134C9F /* 425e on-board */
#define STI_DD_3X2V 0x27134CB4 /* 362/382 on-board VGA-res */
#define STI_DD_TIMBER 0x27F12392 /* on-board 710, older 715 */
#define STI_DD_DUAL_CRX 0x27FCCB6D /* dual-head CRX */
#define STI_DD_ARTIST 0x2B4DED6D /* on-board 712/715, also GSC */
#define STI_DD_HCRX 0x2BCB015A
#define STI_DD_EG 0x2D08C0A7 /* Visualize EG */
#define STI_DD_SUMMIT 0x2FC1066B /* Visualize FX2, FX4, FX6 */
#define STI_DD_PINNACLE 0x35ACDA16 /* Visualize FXe */
#define STI_DD_LEGO 0x35ACDA30 /* Visualize FX5, FX10 */
#define STI_DEV4_DD_GRID 0x08 /* offset for STI_DEVTYPE4 */
#define STI_DEV1_DD_GRID 0x10 /* offset for STI_DEVTYPE1 */
uint32_t dd_fntaddr; /* 0x10 font start address */
uint32_t dd_maxst; /* 0x14 max state storage */
uint32_t dd_romend; /* 0x18 rom last address */
#define STI_DEV4_DD_ROMEND 0x18 /* offset for STI_DEVTYPE4 */
#define STI_DEV1_DD_ROMEND 0x50 /* offset for STI_DEVTYPE1 */
uint32_t dd_reglst; /* 0x1c device region list */
uint16_t dd_maxreent; /* 0x20 max reent storage */
uint16_t dd_maxtimo; /* 0x22 max execution timeout .1 sec */
uint32_t dd_montbl; /* 0x24 mon table address, array of
names num of dd_nmon */
uint32_t dd_udaddr; /* 0x28 user data address */
uint32_t dd_stimemreq; /* 0x2c sti memory request */
uint32_t dd_udsize; /* 0x30 user data size */
uint16_t dd_pwruse; /* 0x34 power usage */
uint8_t dd_bussup; /* 0x36 bus support */
#define STI_BUSSUPPORT_GSCINTL 0x01 /* supports pulling INTL for int */
#define STI_BUSSUPPORT_GSC15X 0x02 /* supports GSC 1.5X */
#define STI_BUSSUPPORT_GSC2X 0x04 /* supports GSC 2.X */
#define STI_BUSSUPPORT_PCIIOEIM 0x08 /* will use directed int */
#define STI_BUSSUPPORT_PCISTD 0x10 /* will use std PCI int */
#define STI_BUSSUPPORT_ILOCK 0x20 /* supports implicit locking */
#define STI_BUSSUPPORT_ROMMAP 0x40 /* rom is only in pci erom space */
#define STI_BUSSUPPORT_2DECODE 0x80 /* single address decoder */
uint8_t dd_ebussup; /* 0x37 extended bus support */
#define STI_EBUSSUPPORT_DMA 0x01 /* supports dma */
#define STI_EBUSSUPPORT_PIOLOCK 0x02 /* no implicit locking for dma */
uint8_t dd_altcodet; /* 0x38 alternate code type */
#define STI_ALTCODE_UNKNOWN 0x00
#define STI_ALTCODE_PA64 0x01 /* alt code is in pa64 */
uint8_t dd_eddst[3]; /* 0x39 extended DD struct */
uint32_t dd_cfbaddr; /* 0x3c CFB address, location of
X11 driver to be used for
servers w/o accel */
uint32_t dd_pacode[16]; /* 0x40 routines for pa-risc */
uint32_t dd_altcode[16]; /* 0x80 routines for m68k/i386 */
} __packed;
#define STI_REVISION(maj, min) (((maj) << 4) | ((min) & 0x0f))
/* after the last region there is one indirect list ptr */
struct sti_region {
u_int offset :14; /* page offset dev io space relative */
u_int sys_only: 1; /* whether allow user access */
u_int cache : 1; /* map in cache */
u_int btlb : 1; /* should use BTLB if available */
u_int last : 1; /* last region in the list */
u_int length :14; /* size in pages */
} __packed;
#define STI_PGSHIFT 12 /* sti(4) assumes 4KB/page for offset/length */
struct sti_font {
uint16_t first;
uint16_t last;
uint8_t width;
uint8_t height;
uint8_t type;
#define STI_FONT_HPROMAN8 1
#define STI_FONT_KANA8 2
uint8_t bpc;
uint32_t next;
uint8_t uheight;
uint8_t uoffset;
uint8_t unused[2];
} __packed;
struct sti_fontcfg {
uint16_t first;
uint16_t last;
uint8_t width;
uint8_t height;
uint8_t type;
uint8_t bpc;
uint8_t uheight;
uint8_t uoffset;
} __packed;
typedef struct sti_mon {
uint32_t width: 12;
uint32_t height: 12;
uint32_t hz: 7; /* low 7 bits of refresh rate */
uint32_t flat: 1; /* flatpanel */
uint32_t vesa: 1; /* vesa mode */
uint32_t grey: 1; /* greyscale */
uint32_t dblbuf: 1; /* double buffered */
uint32_t user: 1; /* user-defined mode */
uint32_t stereo: 1; /* stereo display */
uint32_t sam: 1; /* ? */
uint32_t : 15;
uint32_t hz_upper: 3; /* upper 3 bits of refresh rate */
uint32_t font: 8; /* rom font index */
} __packed *sti_mon_t;
typedef struct sti_ecfg {
uint8_t current_monitor;
uint8_t uf_boot;
uint16_t power; /* power dissipation Watts */
uint32_t freq_ref;
uint32_t *addr; /* memory block of size dd_stimemreq */
void *future;
} __packed *sti_ecfg_t;
typedef struct sti_cfg {
uint32_t text_planes;
uint16_t scr_width;
uint16_t scr_height;
uint16_t oscr_width;
uint16_t oscr_height;
uint16_t fb_width;
uint16_t fb_height;
uint32_t regions[STI_REGION_MAX];
uint32_t reent_level;
uint32_t *save_addr;
sti_ecfg_t ext_cfg;
} __packed *sti_cfg_t;
/* routine types */
#define STI_DEP(n) \
typedef int (*sti_##n##_t)( \
sti_##n##flags_t, sti_##n##in_t, sti_##n##out_t, sti_cfg_t);
typedef struct sti_initflags {
uint32_t flags;
#define STI_INITF_WAIT 0x80000000
#define STI_INITF_RESET 0x40000000
#define STI_INITF_TEXT 0x20000000
#define STI_INITF_NTEXT 0x10000000
#define STI_INITF_CLEAR 0x08000000
#define STI_INITF_CMB 0x04000000 /* non-text planes cmap black */
#define STI_INITF_EBET 0x02000000 /* enable bus error timer */
#define STI_INITF_EBETI 0x01000000 /* enable bus error timer interrupt */
#define STI_INITF_PTS 0x00800000 /* preserve text settings */
#define STI_INITF_PNTS 0x00400000 /* preserve non-text settings */
#define STI_INITF_PBET 0x00200000 /* preserve BET settings */
#define STI_INITF_PBETI 0x00100000 /* preserve BETI settings */
#define STI_INITF_ICMT 0x00080000 /* init cmap for text planes */
#define STI_INITF_SCMT 0x00040000 /* change current monitor type */
#define STI_INITF_RIE 0x00020000 /* retain int enables */
void *future;
} __packed *sti_initflags_t;
typedef struct sti_einitin {
uint8_t mon_type;
uint8_t pad;
uint16_t inflight; /* possible on pci */
void *future;
} __packed *sti_einitin_t;
typedef struct sti_initin {
uint32_t text_planes; /* number of planes for text */
sti_einitin_t ext_in;
} __packed *sti_initin_t;
typedef struct sti_initout {
int32_t errno;
uint32_t text_planes; /* number of planes used for text */
void *future;
} __packed *sti_initout_t;
STI_DEP(init);
typedef struct sti_mgmtflags {
uint32_t flags;
#define STI_MGMTF_WAIT 0x80000000
#define STI_MGMTF_SAVE 0x40000000
#define STI_MGMTF_RALL 0x20000000 /* restore all display planes */
void *future;
} __packed *sti_mgmtflags_t;
typedef struct sti_mgmtin {
void *addr;
void *future;
} __packed *sti_mgmtin_t;
typedef struct sti_mgmtout {
int32_t errno;
void *future;
} __packed *sti_mgmtout_t;
STI_DEP(mgmt);
typedef struct sti_unpmvflags {
uint32_t flags;
#define STI_UNPMVF_WAIT 0x80000000
#define STI_UNPMVF_NTXT 0x40000000 /* intp non-text planes */
void *future;
} __packed *sti_unpmvflags_t;
typedef struct sti_unpmvin {
uint32_t *font_addr; /* font */
uint16_t index; /* character index in the font */
uint8_t fg_colour;
uint8_t bg_colour;
uint16_t x, y;
void *future;
} __packed *sti_unpmvin_t;
typedef struct sti_unpmvout {
uint32_t errno;
void *future;
} __packed *sti_unpmvout_t;
STI_DEP(unpmv);
typedef struct sti_blkmvflags {
uint32_t flags;
#define STI_BLKMVF_WAIT 0x80000000
#define STI_BLKMVF_COLR 0x40000000 /* change colour on move */
#define STI_BLKMVF_CLR 0x20000000 /* clear on move */
#define STI_BLKMVF_NTXT 0x10000000 /* move in non-text planes */
void *future;
} __packed *sti_blkmvflags_t;
typedef struct sti_blkmvin {
uint8_t fg_colour;
uint8_t bg_colour;
uint16_t srcx, srcy, dstx, dsty;
uint16_t width, height;
uint16_t pad;
void *future;
} __packed *sti_blkmvin_t;
typedef struct sti_blkmvout {
uint32_t errno;
void *future;
} __packed *sti_blkmvout_t;
STI_DEP(blkmv);
typedef struct sti_testflags {
uint32_t flags;
#define STI_TESTF_WAIT 0x80000000
#define STI_TESTF_ETST 0x40000000
void *future;
} __packed *sti_testflags_t;
typedef struct sti_testin {
void *future;
} __packed *sti_testin_t;
typedef struct sti_testout {
uint32_t errno;
uint32_t result;
void *future;
} __packed *sti_testout_t;
STI_DEP(test);
typedef struct sti_exhdlflags {
uint32_t flags;
#define STI_EXHDLF_WAIT 0x80000000
#define STI_EXHDLF_CINT 0x40000000 /* clear int */
#define STI_EXHDLF_CBE 0x20000000 /* clear BE */
#define STI_EXHDLF_PINT 0x10000000 /* preserve int */
#define STI_EXHDLF_RINT 0x08000000 /* restore int */
#define STI_EXHDLF_WEIM 0x04000000 /* write eim w/ sti_eexhdlin */
#define STI_EXHDLF_REIM 0x02000000 /* read eim to sti_eexhdlout */
#define STI_EXHDLF_GIE 0x01000000 /* global int enable */
#define STI_EXHDLF_PGIE 0x00800000
#define STI_EXHDLF_WIEM 0x00400000
#define STI_EXHDLF_EIEM 0x00200000
#define STI_EXHDLF_BIC 0x00100000 /* begin int cycle */
#define STI_EXHDLF_EIC 0x00080000 /* end int cycle */
#define STI_EXHDLF_RIE 0x00040000 /* reset do not clear int enables */
void *future;
} __packed *sti_exhdlflags_t;
typedef struct sti_eexhdlin {
uint32_t eim_addr;
uint32_t eim_data;
uint32_t iem; /* enable mask */
uint32_t icm; /* clear mask */
void *future;
} __packed *sti_eexhdlin_t;
typedef struct sti_exhdlint {
uint32_t flags;
#define STI_EXHDLINT_BET 0x80000000 /* bus error timer */
#define STI_EXHDLINT_HW 0x40000000 /* high water */
#define STI_EXHDLINT_LW 0x20000000 /* low water */
#define STI_EXHDLINT_TM 0x10000000 /* texture map */
#define STI_EXHDLINT_VB 0x08000000 /* vertical blank */
#define STI_EXHDLINT_UDC 0x04000000 /* unbuffered dma complete */
#define STI_EXHDLINT_BDC 0x02000000 /* buffered dma complete */
#define STI_EXHDLINT_UDPC 0x01000000 /* unbuf priv dma complete */
#define STI_EXHDLINT_BDPC 0x00800000 /* buffered priv dma complete */
} __packed *sti_exhdlint_t;
typedef struct sti_exhdlin {
sti_exhdlint_t addr;
sti_eexhdlin_t ext;
} __packed *sti_exhdlin_t;
typedef struct sti_eexhdlout {
uint32_t eim_addr;
uint32_t eim_data;
uint32_t iem; /* enable mask */
uint32_t icm; /* clear mask */
void *future;
} __packed *sti_eexhdlout_t;
typedef struct sti_exhdlout {
uint32_t errno;
uint32_t flags;
#define STI_EXHDLO_BE 0x80000000 /* BE was intercepted */
#define STI_EXHDLO_IP 0x40000000 /* there is int pending */
#define STI_EXHDLO_IE 0x20000000 /* global enable set */
sti_eexhdlout_t ext;
} __packed *sti_exhdlout_t;
STI_DEP(exhdl);
typedef struct sti_inqconfflags {
uint32_t flags;
#define STI_INQCONFF_WAIT 0x80000000
void *future;
} __packed *sti_inqconfflags_t;
typedef struct sti_inqconfin {
void *future;
} __packed *sti_inqconfin_t;
typedef struct sti_einqconfout {
uint32_t crt_config[3];
uint32_t crt_hw[3];
void *future;
} __packed *sti_einqconfout_t;
typedef struct sti_inqconfout {
uint32_t errno;
uint16_t width, height, owidth, oheight, fbwidth, fbheight;
uint32_t bpp; /* bits per pixel */
uint32_t bppu; /* accessible bpp */
uint32_t planes;
uint8_t name[STI_DEVNAME_LEN];
uint32_t attributes;
#define STI_INQCONF_Y2X 0x0001 /* pixel is higher than wider */
#define STI_INQCONF_HWBLKMV 0x0002 /* hw blkmv is present */
#define STI_INQCONF_AHW 0x0004 /* adv hw accel */
#define STI_INQCONF_INT 0x0008 /* can interrupt */
#define STI_INQCONF_GONOFF 0x0010 /* supports on/off */
#define STI_INQCONF_AONOFF 0x0020 /* supports alpha on/off */
#define STI_INQCONF_VARY 0x0040 /* variable fb height */
#define STI_INQCONF_ODDBYTES 0x0080 /* use only odd fb bytes */
#define STI_INQCONF_FLUSH 0x0100 /* fb cache requires flushing */
#define STI_INQCONF_DMA 0x0200 /* supports dma */
#define STI_INQCONF_VDMA 0x0400 /* supports vdma */
#define STI_INQCONF_YUV1 0x2000 /* supports YUV type 1 */
#define STI_INQCONF_YUV2 0x4000 /* supports YUV type 2 */
#define STI_INQCONF_BITS \
"\020\001y2x\002hwblkmv\003ahw\004int\005gonoff\006aonoff\007vary"\
"\010oddb\011flush\012dma\013vdma\016yuv1\017yuv2"
sti_einqconfout_t ext;
} __packed *sti_inqconfout_t;
STI_DEP(inqconf);
typedef struct sti_scmentflags {
uint32_t flags;
#define STI_SCMENTF_WAIT 0x80000000
void *future;
} __packed *sti_scmentflags_t;
typedef struct sti_scmentin {
uint32_t entry;
uint32_t value;
void *future;
} __packed *sti_scmentin_t;
typedef struct sti_scmentout {
uint32_t errno;
void *future;
} __packed *sti_scmentout_t;
STI_DEP(scment);
typedef struct sti_dmacflags {
uint32_t flags;
#define STI_DMACF_WAIT 0x80000000
#define STI_DMACF_PRIV 0x40000000 /* priv dma */
#define STI_DMACF_DIS 0x20000000 /* disable */
#define STI_DMACF_BUF 0x10000000 /* buffered */
#define STI_DMACF_MRK 0x08000000 /* write a marker */
#define STI_DMACF_ABRT 0x04000000 /* abort dma xfer */
void *future;
} __packed *sti_dmacflags_t;
typedef struct sti_dmacin {
uint32_t pa_upper;
uint32_t pa_lower;
uint32_t len;
uint32_t mrk_data;
uint32_t mrk_off;
void *future;
} __packed *sti_dmacin_t;
typedef struct sti_dmacout {
uint32_t errno;
void *future;
} __packed *sti_dmacout_t;
STI_DEP(dmac);
typedef struct sti_flowcflags {
uint32_t flags;
#define STI_FLOWCF_WAIT 0x80000000
#define STI_FLOWCF_CHW 0x40000000 /* check high water */
#define STI_FLOWCF_WHW 0x20000000 /* write high water */
#define STI_FLOWCF_WLW 0x10000000 /* write low water */
#define STI_FLOWCF_PCSE 0x08000000 /* preserve cse */
#define STI_FLOWCF_CSE 0x04000000
#define STI_FLOWCF_CSWF 0x02000000 /* cs write fine */
#define STI_FLOWCF_CSWC 0x01000000 /* cs write coarse */
#define STI_FLOWCF_CSWQ 0x00800000 /* cs write fifo */
void *future;
} __packed *sti_flowcflags_t;
typedef struct sti_flowcin {
uint32_t retry;
uint32_t bufz;
uint32_t hwcnt;
uint32_t lwcnt;
uint32_t csfv; /* cs fine value */
uint32_t cscv; /* cs coarse value */
uint32_t csqc; /* cs fifo count */
void *future;
} __packed *sti_flowcin_t;
typedef struct sti_flowcout {
uint32_t errno;
uint32_t retry_result;
uint32_t fifo_size;
void *future;
} __packed *sti_flowcout_t;
STI_DEP(flowc);
typedef struct sti_utimingflags {
uint32_t flags;
#define STI_UTIMF_WAIT 0x80000000
#define STI_UTIMF_HKS 0x40000000 /* has kbuf_size */
void *future;
} __packed *sti_utimingflags_t;
typedef struct sti_utimingin {
void *data;
void *kbuf;
void *future;
} __packed *sti_utimingin_t;
typedef struct sti_utimingout {
uint32_t errno;
uint32_t kbuf_size; /* buffer required size */
void *future;
} __packed *sti_utimingout_t;
STI_DEP(utiming);
typedef struct sti_pmgrflags {
uint32_t flags;
#define STI_UTIMF_WAIT 0x80000000
#define STI_UTIMOP_CLEANUP 0x00000000
#define STI_UTIMOP_BAC 0x10000000
#define STI_UTIMF_CRIT 0x04000000
#define STI_UTIMF_BUFF 0x02000000
#define STI_UTIMF_IBUFF 0x01000000
void *future;
} __packed *sti_pmgrflags_t;
typedef struct sti_pmgrin {
uint32_t reserved[4];
void *future;
} __packed *sti_pmgrin_t;
typedef struct sti_pmgrout {
int32_t errno;
void *future;
} __packed *sti_pmgrout_t;
STI_DEP(pmgr);
typedef struct sti_utilflags {
uint32_t flags;
#define STI_UTILF_ROOT 0x80000000 /* was called as root */
void *future;
} __packed *sti_utilflags_t;
typedef struct sti_utilin {
uint32_t in_size;
uint32_t out_size;
uint8_t *buf;
} __packed *sti_utilin_t;
typedef struct sti_utilout {
int32_t errno;
void *future;
} __packed *sti_utilout_t;
STI_DEP(util);
/*
* NGLE register layout.
* Based upon xc/programs/Xserver/hw/hp/ngle/dregs.h
*/
#define BA(F,C,S,A,J,B,I) \
(((F)<<31)|((C)<<27)|((S)<<24)|((A)<<21)|((J)<<16)|((B)<<12)|(I))
/* FCCC CSSS AAAJ JJJJ BBBB IIII IIII IIII */
/* F */
#define IndexedDcd 0 /* Pixel data is indexed (pseudo) color */
#define FractDcd 1 /* Pixel data is Fractional 8-8-8 */
/* C */
#define Otc04 2 /* Pixels in each longword transfer (4) */
#define Otc32 5 /* Pixels in each longword transfer (32) */
#define Otc24 7 /* NGLE uses this for 24bit blits */
/* S */
#define Ots08 3 /* Each pixel is size (8)d transfer (1) */
#define OtsIndirect 6 /* Each bit goes through FG/BG color(8) */
/* A */
#define AddrByte 3 /* byte access? Used by NGLE for direct fb */
#define AddrLong 5 /* FB address is Long aligned (pixel) */
#define Addr24 7 /* used for colour map access */
/* B */
#define BINapp0I 0x0 /* Application Buffer 0, Indexed */
#define BINapp1I 0x1 /* Application Buffer 1, Indexed */
#define BINovly 0x2 /* 8 bit overlay */
#define BINcursor 0x6 /* cursor bitmap on EG */
#define BINcmask 0x7 /* cursor mask on EG */
#define BINapp0F8 0xa /* Application Buffer 0, Fractional 8-8-8 */
#define BINattr 0xd /* Attribute Bitmap */
#define BINcmap 0xf /* colour map(s) */
/* other buffers are unknown */
/* J - 'BA just point' - function unknown */
/* I - 'BA index base' - function unknown */
#define IBOvals(R,M,X,S,D,L,B,F) \
(((R)<<8)|((M)<<16)|((X)<<24)|((S)<<29)|((D)<<28)|((L)<<31)|((B)<<1)|(F))
/* LSSD XXXX MMMM MMMM RRRR RRRR ???? ??BF */
/* R is a standard X11 ROP, no idea if the other bits areused for anything */
#define RopClr 0x0
#define RopSrc 0x3
#define RopInv 0xc
#define RopSet 0xf
/* M: 'mask addr offset' - function unknown */
/* X */
#define BitmapExtent08 3 /* Each write hits ( 8) bits in depth */
#define BitmapExtent32 5 /* Each write hits (32) bits in depth */
/* S: 'static reg' flag, NGLE sets it for blits, function is unknown but
we get occasional garbage in 8bit blits without it */
/* D */
#define DataDynamic 0 /* Data register reloaded by direct access */
/* L */
#define MaskDynamic 1 /* Mask register reloaded by direct access */
#define MaskOtc 0 /* Mask contains Object Count valid bits */
/* B = 1 -> background transparency for masked fills */
/* F probably the same for foreground */
#define NGLE_REG_1 0x000118 /* Artist LUT blt ctrl */
#define NGLE_REG_28 0x000420 /* HCRX video bus access */
#define NGLE_REG_2 0x000480 /* BINC src */
#define NGLE_REG_3 0x0004a0 /* BINC dst */
#define NGLE_REG_22 0x0005a0 /* BINC dst mask */
#define NGLE_REG_23 0x0005c0 /* BINC data */
#define NGLE_REG_4 0x000600 /* palette data */
#define NGLE_REG_5 0x0006a0 /* cursor data */
#define NGLE_REG_6 0x000800 /* rectfill XY */
#define NGLE_REG_7 0x000804 /* bitblt size WH */
#define NGLE_REG_24 0x000808 /* bitblt src XY */
#define NGLE_REG_8 0x000820 /* 'transfer data' - this is */
/* a pixel mask on fills */
#define NGLE_REG_37 0x000944 /* HCRX fast rect fill, size */
#define NGLE_REG_9 0x000a04 /* rect fill size, start */
#define NGLE_REG_25 0x000b00 /* bitblt dst XY, start */
#define NGLE_REG_RAMDAC 0x001000
#define NGLE_REG_10 0x018000 /* buffer ctl */
#define NGLE_REG_11 0x018004 /* dest bitmap access */
#define NGLE_REG_12 0x01800c /* control plane register */
#define NGLE_REG_35 0x018010 /* fg colour */
#define NGLE_REG_36 0x018014 /* bg colour */
#define NGLE_REG_13 0x018018 /* image planemask */
#define NGLE_REG_14 0x01801c /* raster op */
#define NGLE_REG_15 0x200000 /* 'busy dodger' idle */
#define DODGER_IDLE 0x1000 /* or 0x10000, likely tpyo */
#define NGLE_REG_15b0 0x200000 /* busy register */
#define NGLE_REG_16 0x200004
#define NGLE_REG_16b1 0x200005 /* setup copyarea */
#define NGLE_REG_16b3 0x200007 /* ROM table index on CRX */
#define NGLE_REG_34 0x200008 /* # of fifo slots */
#define NGLE_REG_17 0x200100 /* cursor coordinates */
#define NGLE_REG_18 0x200104 /* cursor enable */
#define NGLE_REG_26 0x200118 /* EG LUT blt ctrl */
#define NGLE_REG_19 0x200200 /* artist sprite size */
#define NGLE_REG_20 0x200208 /* cursor geometry */
#define NGLE_REG_21 0x200218 /* Artist misc video */
#define NGLE_REG_27 0x200308 /* Artist misc ctrl */
#define NGLE_REG_29 0x210000 /* HCRX cursor coord & enable */
#define HCRX_ENABLE_CURSOR 0x80000000
#define NGLE_REG_30 0x210004 /* HCRX cursor address */
#define NGLE_REG_31 0x210008 /* HCRX cursor data */
#define NGLE_REG_38 0x210020 /* HCRX LUT blt ctrl */
/* EWRRRROO OOOOOOOO TTRRRRLL LLLLLLLL */
#define LBC_ENABLE 0x80000000
#define LBC_WAIT_BLANK 0x40000000
#define LBS_OFFSET_SHIFT 16
#define LBC_TYPE_MASK 0xc000
#define LBC_TYPE_CMAP 0
#define LBC_TYPE_CURSOR 0x8000
#define LBC_TYPE_OVERLAY 0xc000
#define LBC_LENGTH_SHIFT 0
#define NGLE_REG_41 0x210024
#define NGLE_REG_42 0x210028 /* these seem to control */
#define NGLE_REG_43 0x21002c /* how the 24bit planes */
#define NGLE_REG_44 0x210030 /* are displayed on HCRX - */
#define NGLE_REG_45 0x210034 /* no info on bits */
#define NGLE_REG_32 0x21003c /* HCRX plane enable */
#define NGLE_REG_33 0x210040 /* HCRX misc video */
#define HCRX_VIDEO_ENABLE 0x0A000000
#define NGLE_REG_39 0x210120 /* HCRX 'hyperbowl' mode 2 */
#define HYPERBOWL_MODE2_8_24 15
#define NGLE_REG_40 0x210130 /* HCRX 'hyperbowl' */
#define HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES 4
#define HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE 8
#define HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE 10
#define NGLE_BUFF0_CMAP0 0x00001e02
#define NGLE_BUFF1_CMAP0 0x02001e02
#define NGLE_BUFF1_CMAP3 0x0c001e02
#define NGLE_ARTIST_CMAP0 0x00000102
/* mimic HP/UX, this will return the device's graphics ID */
#define GCID _IOR('G', 40, u_int)
#endif /* _IC_STIREG_H_ */
lib/libc/include/generic-netbsd/dev/ic/summitreg.h
Vendored
+214
View File
@@ -0,0 +1,214 @@
/* $NetBSD: summitreg.h,v 1.16 2025/01/29 15:35:22 macallan Exp $ */
/*
* Copyright (c) 2024 Michael Lorenz
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/* HP Visualize FX 4 and related hardware, aka Summit */
/*
* register values, found by disassembling the ROM
* some found by Sven Schnelle
* ( see https://patchwork.kernel.org/project/linux-parisc/patch/20211031204952.25678-2-svens@stackframe.org/ )
* some by me
*/
#ifndef SUMMITREG_H
#define SUMMITREG_H
#define VISFX_CONTROL 0x641000
#define CONTROL_WFC 0x00000200 // FIFO when 0, direct when 1
#define VISFX_FC 0x641040 // Fault Control
#define VISFX_STATUS 0x641400 // zero when idle
/*
* about the FIFO register:
* - on FX4, there are 0x800 FIFO slots, quite a lot
* - based on observation, every register write seems to occupy *two* slots
* - we need to write 0 to VISFX_CONTROL to enable FIFO pacing
* - the FIFO is quite difficult to overrun but things like x11perf copywinwin
* will do it if we're not careful
*/
#define VISFX_FIFO 0x641440
#define VISFX_FOE 0x920404 // Fragment Operation Enable
#define FOE_TEXTURE 0x00000001
#define FOE_SPECULAR 0x00000002
#define FOE_DEPTHCUE 0x00000004
#define FOE_ALPHATEST 0x00000008
#define FOE_STENCIL 0x00000010
#define FOE_Z_TEST 0x00000020
#define FOE_BLEND_ROP 0x00000040 // IBO is used
#define FOE_DITHER 0x00000080
#define VISFX_IBO 0x921110 // ROP in lowest nibble
#define VISFX_CBR 0x92111c // constant colour for blending
#define VISFX_IAA0 0x921200 // XLUT, 16 entries
#define VISFX_IAA(n) (0x921200 + ((n) << 2))
#define VISFX_OTR 0x921148 // overlay transparency
#define VISFX_VRAM_WRITE_MODE 0xa00808
#define VISFX_VRAM_READ_MODE 0xa0080c
#define VISFX_PIXEL_MASK 0xa0082c
#define VISFX_FG_COLOUR 0xa0083c
#define VISFX_BG_COLOUR 0xa00844
#define VISFX_PLANE_MASK 0xa0084c
/* this controls what we see in the FB aperture */
#define VISFX_APERTURE_ACCESS 0xa00858
#define VISFX_DEPTH_8 0x30
#define VISFX_DEPTH_32 0x50
#define VISFX_RPH 0xa0085c // read prefetch hint
#define VISFX_RPH_RTL 0x80000000 // right-to-left
#define VISFX_RPH_LTR 0x00000000 // left-to-right
#define VISFX_READ_DATA 0xa41480
#define VISFX_VRAM_WRITE_DATA_INCRX 0xa60000
#define VISFX_VRAM_WRITE_DATA_INCRY 0xa68000
#define VISFX_VRAM_WRITE_DEST 0xac1000
#define VISFX_TCR 0xac1024 /* throttle control */
#define VISFX_CLIP_TL 0xac1050 /* clipping rect, top/left */
#define VISFX_CLIP_WH 0xac1054 /* clipping rect, w/h */
#define VISFX_WRITE_MODE_PLAIN 0x02000000
#define VISFX_WRITE_MODE_EXPAND 0x050004c0
#define VISFX_WRITE_MODE_FILL 0x050008c0
#define VISFX_WRITE_MODE_TRANSPARENT 0x00000800 /* bg is tansparent */
#define VISFX_WRITE_MODE_MASK 0x00000400 /* apply pixel mask */
/* 0x00000200 - some pattern */
/* looks like 0x000000c0 enables fb/bg colours to be applied */
#define VISFX_READ_MODE_COPY 0x02000400
#define OTC01 0x00000000 /* one pixel per 32bit write */
#define OTC04 0x02000000 /* 4 pixels per 32bit write */
#define OTC32 0x05000000 /* 32 pixels per 32bit write */
#define BIN8I 0x00000000 /* 8bit indexed */
#define BIN12I 0x00010000 /* 12bit indexed */
#define BIN332F 0x00040000 /* R3G3B2 */
#define BIN8F 0x00070000 /* ARGB8 */
#define BINapln 0x00110000 /* attribute plane */
#define BINhost 0x00300000 /* DMA to host */
#define BUFovl 0x00000000 /* 8bit overlay */
#define BUFBL 0x00008000 /* back/left */
#define BUFFL 0x00004000 /* front/left */
#define BUFBR 0x00002000 /* back/right */
#define BUFFR 0x00001000 /* front/right */
/* attribute table, this only selects depth and CFS */
#define IAA_8I 0x00000000 /* 8bit CI */
#define IAA_8F 0x00000070 /* RGB8 */
#define IAA_CFS0 0x00000000 /* CFS select */
#define IAA_CFS1 0x00000100 /* CFS 1 etc. */
#define OTR_T 0x00010000 /* when set 0 is transparent, otherwise 0xff */
#define OTR_A 0x00000100 /* always transparent */
#define OTR_L1 0x00000002 /* transparency controlled by CFS17 */
#define OTR_L0 0x00000001 /* transparency controlled by CFS16 */
/*
* for STI colour change mode:
* set VISFX_FG_COLOUR, VISFX_BG_COLOUR
* set VISFX_VRAM_READ_MODE 0x05000400
* set VISFX_VRAM_WRITE_MODE 0x050000c0
*/
/* fill */
#define VISFX_START 0xb3c000
#define VISFX_SIZE 0xb3c808 /* start, FX4 uses 0xb3c908 */
/* copy */
#define VISFX_COPY_SRC 0xb3c010
#define VISFX_COPY_WH 0xb3c008
#define VISFX_COPY_DST 0xb3cc00
/*
* looks like ORing 0x800 to the register address starts a command
* - 0x800 - fill
* - 0xc00 - copy
* 0x100 and 0x200 seem to have functions as well, not sure what though
* for example, the FX4 ROM uses 0xb3c908 to start a rectangle fill, but
* it also works with 0xb3c808 and 0xb3ca08
* same with copy, 0xc00 seems to be what matters, setting 0x100 or 0x200
* doesn't seem to make a difference
* 0x400 or 0x100 by themselves don't start a command either
*/
/*
* alpha blending operations
* source and destination blend functions are in 0xf0 and 0x0f
* how they're combined is in 0x700
*/
#define IBO_ROP 0 /* ROP in lower 4 bit */
#define IBO_ADD 0x200
#define IBO_S_MINUS_D 0x400 /* source - dest */
#define IBO_D_MINUS_S 0x500 /* dest - source */
#define IBO_MIN 0x600
#define IBO_MAX 0x700
/*
* here are the blend functions I identified
* apparently the upper byte in 32bit mode is not implemented on FX2/4/6, and
* neither is any blend mode that takes the colour value from CBR
* so no blending with screen-to-screen blits, alpha will always read zero
* the only ways to actually use alpha blending is with fills ( the alpha part
* of the FG register is used ) and BINC writes, or when using constant alpha
*/
#define IBO_ZERO 0
#define IBO_ONE 1
#define IBO_SRC 4 /* src alpha */
#define IBO_ONE_MINUS_SRC 5 /* 1 - src alpha */
#define IBO_CBR 14 /* alpha from CBR */
#define IBO_ONE_MINUS_CBR 15 /* 1 - alpha from CBR */
#define SRC(n) ((n) << 4)
#define DST(n) (n)
/*
* use unbuffered space for cursor registers
* The _POS, _INDEX and _DATA registers work exactly like on HCRX
*/
#define VISFX_CURSOR_POS 0x400000
#define VISFX_CURSOR_ENABLE 0x80000000
#define VISFX_CURSOR_INDEX 0x400004
#define VISFX_CURSOR_DATA 0x400008
#define VISFX_CURSOR_FG 0x40000c
#define VISFX_CURSOR_BG 0x400010
#define VISFX_COLOR_MASK 0x800018
#define VISFX_COLOR_INDEX 0x800020
#define VISFX_COLOR_VALUE 0x800024
#define VISFX_FATTR 0x80003c /* force attribute */
#define VISFX_MPC 0x80004c
#define MPC_VIDEO_ON 0x0c
#define MPC_VSYNC_OFF 0x02
#define MPC_HSYNC_OFF 0x01
#define VISFX_CFS0 0x800100 /* colour function select */
#define VISFX_CFS(n) (VISFX_CFS0 + ((n) << 2))
/* 0 ... 6 for image planes, 7 or bypass, 16 and 17 for overlay */
#define CFS_CR 0x80 // enable color recovery
#define CFS_332 0x00 // R3G3B2
#define CFS_8I 0x40 // 8bit indexed
#define CFS_8F 0x70 // ARGB8
#define CFS_LUT0 0x00 // use LUT 0
#define CFS_LUT1 0x01 // LUT 1 etc.
#define CFS_BYPASS 0x07 // bypass LUT
#endif /* SUMMITREG_H */
lib/libc/include/generic-netbsd/dev/iscsi/iscsi.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: iscsi.h,v 1.4.50.1 2023/12/18 14:15:58 martin Exp $ */
/* $NetBSD: iscsi.h,v 1.5 2023/11/25 10:08:27 mlelstv Exp $ */
/*-
* Copyright (c) 2004,2006,2011 The NetBSD Foundation, Inc.
lib/libc/include/generic-netbsd/dev/pci/amrreg.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: amrreg.h,v 1.5 2008/09/08 23:36:54 gmcgarry Exp $ */
/* $NetBSD: amrreg.h,v 1.6 2023/08/15 04:04:10 mrg Exp $ */
/*-
* Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
@@ -313,7 +313,7 @@ struct amr_enquiry3 {
u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */
u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */
u_int8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */
u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES];
u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES / 16];
u_int8_t ae_targxfer[80]; /* physical drive transfer rates */
u_int8_t res1[263]; /* pad to 1024 bytes */
lib/libc/include/generic-netbsd/dev/pci/mlyreg.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mlyreg.h,v 1.8 2021/10/24 20:00:11 andvar Exp $ */
/* $NetBSD: mlyreg.h,v 1.9 2024/02/10 09:21:53 andvar Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -1242,7 +1242,7 @@ union mly_cmd_packet {
* PG6: 5.4.4 Doorbell 1
*
* Note that the documentation claims that these bits are set when the
* status queue(s) are empty, wheras the Linux driver and experience
* status queue(s) are empty, whereas the Linux driver and experience
* suggest they are set when there is status available.
*/
#define MLY_HM_STSREADY (1<<0)
lib/libc/include/generic-netbsd/dev/pci/pcidevs.h
Vendored
+177 -22
View File
@@ -1,10 +1,10 @@
/* $NetBSD: pcidevs.h,v 1.1452.2.15 2024/12/06 20:18:33 snj Exp $ */
/* $NetBSD: pcidevs.h,v 1.1506.2.3 2025/11/24 17:28:21 martin Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* NetBSD: pcidevs,v 1.1471.2.14 2024/12/06 20:15:04 snj Exp
* NetBSD: pcidevs,v 1.1527.2.3 2025/11/24 17:27:40 martin Exp
*/
/*
@@ -653,6 +653,7 @@
#define PCI_VENDOR_ASMEDIA 0x1b21 /* ASMedia */
#define PCI_VENDOR_REDHAT 0x1b36 /* Red Hat */
#define PCI_VENDOR_MARVELL2 0x1b4b /* Marvell */
#define PCI_VENDOR_ETRON 0x1b6f /* Etron Technology, Inc. */
#define PCI_VENDOR_FRESCO 0x1b73 /* Fresco Logic */
#define PCI_VENDOR_QINHENG2 0x1c00 /* Nanjing QinHeng Electronics (PCIe) */
#define PCI_VENDOR_SYMPHONY2 0x1c1c /* Symphony Labs (2nd PCI Vendor ID) */
@@ -905,6 +906,9 @@
#define PCI_PRODUCT_ADP2_ASR2200S_SUB2M 0x0287 /* ASR-2200S */
#define PCI_PRODUCT_ADP2_ASR2410SA 0x0290 /* ASR-2410SA */
#define PCI_PRODUCT_ADP2_AAR2810SA 0x0292 /* AAR-2810SA */
#define PCI_PRODUCT_ADP2_5445 0x02b5 /* RAID 5445 */
#define PCI_PRODUCT_ADP2_5805 0x02b6 /* RAID 5805 */
#define PCI_PRODUCT_ADP2_5085 0x02b7 /* RAID 5085 */
#define PCI_PRODUCT_ADP2_3405 0x02bb /* RAID 3405 */
#define PCI_PRODUCT_ADP2_3805 0x02bc /* RAID 3805 */
#define PCI_PRODUCT_ADP2_2405 0x02d5 /* RAID 2405 */
@@ -1293,9 +1297,15 @@
#define PCI_PRODUCT_AMD_HUDSON_PCIE_2 0x43a2 /* Hudson PCIe Root Port 2 */
#define PCI_PRODUCT_AMD_HUDSON_PCIE_3 0x43a3 /* Hudson PCIe Root Port 3 */
#define PCI_PRODUCT_AMD_300SERIES_PCIE 0x43b4 /* 300 Series PCIe */
#define PCI_PRODUCT_AMD_X370SERIES_SATA 0x43b5 /* X370 Series SATA */
#define PCI_PRODUCT_AMD_X399SERIES_SATA 0x43b6 /* X399 Series SATA */
#define PCI_PRODUCT_AMD_300SERIES_SATA 0x43b7 /* 300 Series SATA */
#define PCI_PRODUCT_AMD_FCH_SATA_D 0x43b8 /* FCH SATA Controller D */
#define PCI_PRODUCT_AMD_A320SERIES_SATA 0x43b8 /* A320 Series SATA */
#define PCI_PRODUCT_AMD_X370SERIES_XHCI 0x43b9 /* X370 Series xHCI */
#define PCI_PRODUCT_AMD_X399SERIES_XHCI 0x43ba /* X399 Series xHCI */
#define PCI_PRODUCT_AMD_300SERIES_XHCI 0x43bb /* 300 Series xHCI */
#define PCI_PRODUCT_AMD_A320SERIES_XHCI 0x43bc /* A320 Series xHCI */
#define PCI_PRODUCT_AMD_FCH_AHCI_SATA_RAID 0x43bd /* FCH AHCI SATA (RAID mode) */
#define PCI_PRODUCT_AMD_400SERIES_PCIE_1 0x43c6 /* 400 Series PCIe */
#define PCI_PRODUCT_AMD_400SERIES_PCIE_2 0x43c7 /* 400 Series PCIe */
#define PCI_PRODUCT_AMD_400SERIES_AHCI 0x43c8 /* 400 Series AHCI */
@@ -1304,7 +1314,12 @@
#define PCI_PRODUCT_AMD_500SERIES_PCIE_1 0x43e9 /* 500 Series PCIe */
#define PCI_PRODUCT_AMD_500SERIES_PCIE_2 0x43ea /* 500 Series PCIe */
#define PCI_PRODUCT_AMD_500SERIES_AHCI 0x43eb /* 500 Series AHCI */
#define PCI_PRODUCT_AMD_A520SERIES_XHCI 0x43ec /* A520 Series xHCI */
#define PCI_PRODUCT_AMD_500SERIES_XHCI 0x43ee /* 500 Series xHCI */
#define PCI_PRODUCT_AMD_600SERIES_PCIE_1 0x43f4 /* 600 Series PCIe Switch Upstream Port */
#define PCI_PRODUCT_AMD_600SERIES_PCIE_2 0x43f5 /* 600 Series PCIe Switch Downstream Port */
#define PCI_PRODUCT_AMD_600SERIES_SATA 0x43f6 /* 600 Series SATA */
#define PCI_PRODUCT_AMD_600SERIES_XHCI 0x43f7 /* 600 Series xHCI */
#define PCI_PRODUCT_AMD_500SERIES_PCIE_3 0x57a3 /* 500 Series PCIe */
#define PCI_PRODUCT_AMD_500SERIES_PCIE_4 0x57a4 /* 500 Series PCIe */
#define PCI_PRODUCT_AMD_500SERIES_PCIE_5 0x57ad /* 500 Series PCIe */
@@ -1583,6 +1598,9 @@
#define PCI_PRODUCT_ATI_RADEON_KAVERI_HDMI 0x1308 /* Kaveri HDMI Audio */
#define PCI_PRODUCT_ATI_RADEON_KAVERI_R7_1 0x1313 /* Kaveri Radeon R7 (Kaveri) */
#define PCI_PRODUCT_ATI_RADEON_WRESTLER_HDMI 0x1314 /* Wrestler HDMI Audio */
#define PCI_PRODUCT_ATI_NAVI_PCIE_1 0x1478 /* Navi PCIe Switch Upstream Port */
#define PCI_PRODUCT_ATI_NAVI_PCIE_2 0x1479 /* Navi PCIe Switch Downstream Port */
#define PCI_PRODUCT_ATI_RADEON_RAVEN_RIDGE 0x15dd /* Raven Ridge Radeon Vega (Mobile) Series */
#define PCI_PRODUCT_ATI_RADEON_BEAVERCREEK_HDMI 0x1714 /* BeaverCreek HDMI Audio */
#define PCI_PRODUCT_ATI_RADEON_RV380_3150 0x3150 /* Radeon Mobility X600 (M24) 3150 */
#define PCI_PRODUCT_ATI_RADEON_RV380_3154 0x3154 /* FireGL M24 GL 3154 */
@@ -3320,6 +3338,10 @@
/* ESS Technology products */
#define PCI_PRODUCT_ESSTECH2_MAESTRO1 0x0100 /* Maestro 1 PCI Audio Accelerator */
/* Etron Technology products */
#define PCI_PRODUCT_ETRON_EJ168 0x7023 /* EJ168 USB 3.0 xHCI */
#define PCI_PRODUCT_ETRON_EJ188 0x7052 /* EJ188/EJ198 USB 3.0 xHCI */
/* Eumitcom products */
#define PCI_PRODUCT_EUMITCOM_WL11000P 0x1100 /* WL11000P PCI WaveLAN/IEEE 802.11 */
@@ -3345,6 +3367,7 @@
#define PCI_PRODUCT_EXAR_XR17D154 0x0154 /* quad-channel Universal PCI UART */
#define PCI_PRODUCT_EXAR_XR17D158 0x0158 /* octal-channel Universal PCI UART */
#define PCI_PRODUCT_EXAR_XR17V354 0x0354 /* quad-channel Universal PCIe UART */
#define PCI_PRODUCT_EXAR_XR17V358 0x0358 /* octal-channel Universal PCIe UART */
/* FORE products */
#define PCI_PRODUCT_FORE_PCA200 0x0210 /* ATM PCA-200 */
@@ -3549,7 +3572,7 @@
#define PCI_PRODUCT_MARVELL2_88SE9485 0x9485 /* 88SE9485 SATA Controller */
/* Micro-star International Co Ltd */
#define PCI_PRODUCT_MSI_RT3090 0x891a /* MIS RT3090 */
#define PCI_PRODUCT_MSI_RT3090 0x891a /* MSI RT3090 */
/* Global Sun Tech products */
#define PCI_PRODUCT_GLOBALSUN_GL24110P 0x1101 /* GL24110P PCI IEEE 802.11b */
@@ -5141,6 +5164,7 @@
#define PCI_PRODUCT_INTEL_63XXESB_SMB 0x269b /* 63xxESB SMBus Controller */
#define PCI_PRODUCT_INTEL_63XXESB_IDE 0x269e /* 63xxESB IDE Controller */
#define PCI_PRODUCT_INTEL_SNR_DLB 0x270b /* Snow Ridge DLB 1.0 */
#define PCI_PRODUCT_INTEL_WIFI7 0x272b /* Wi-Fi 7 */
#define PCI_PRODUCT_INTEL_82945P_MCH 0x2770 /* 82945G/P Memory Controller Hub */
#define PCI_PRODUCT_INTEL_82945P_EXP 0x2771 /* 82945G/P PCI Express Bridge */
#define PCI_PRODUCT_INTEL_82945P_IGD 0x2772 /* 82945G/P Integrated Graphics Device */
@@ -6516,6 +6540,7 @@
#define PCI_PRODUCT_INTEL_APL_SSRAM 0x5aec /* Apollo Lake Shared SRAM */
#define PCI_PRODUCT_INTEL_APL_UART_3 0x5aee /* Apollo Lake UART 3 */
#define PCI_PRODUCT_INTEL_APL_HB 0x5af0 /* Apollo Lake Host Bridge */
#define PCI_PRODUCT_INTEL_NPU_LNL 0x643e /* Lunar Lake NPU */
#define PCI_PRODUCT_INTEL_XEOND_HB_DMI2 0x6f00 /* Core i7-6xxxK/Xeon-D Host Bridge (DMI2) */
#define PCI_PRODUCT_INTEL_XEOND_HB_PCIE 0x6f01 /* Xeon-D Host Bridge (PCIe) */
#define PCI_PRODUCT_INTEL_XEOND_PCIE_1 0x6f02 /* Xeon-D PCIe Root Port (x8 or x4 max) */
@@ -6778,6 +6803,17 @@
#define PCI_PRODUCT_INTEL_6HS_H_I2C_4 0x7afc /* 600 Series PCH-H I2C 4 */
#define PCI_PRODUCT_INTEL_6HS_H_I2C_5 0x7afd /* 600 Series PCH-H I2C 5 */
#define PCI_PRODUCT_INTEL_6HS_H_UART_2 0x7afe /* 600 Series PCH-H UART 2 */
#define PCI_PRODUCT_INTEL_VMD_MTL 0x7d0b /* Volume Management Device */
#define PCI_PRODUCT_INTEL_NPU_MTL 0x7d1d /* Meteor Lake NPU */
#define PCI_PRODUCT_INTEL_LPC_MTL 0x7e02 /* Meteor Lake LPC/ISA Bridge */
#define PCI_PRODUCT_INTEL_PCH_MTL 0x7d14 /* Meteor Lake PCH */
#define PCI_PRODUCT_INTEL_SMBUS_MTL 0x7e22 /* Meteor Lake SMbus */
#define PCI_PRODUCT_INTEL_SPI_MTL 0x7e23 /* Meteor Lake SPI Controller */
#define PCI_PRODUCT_INTEL_ARCG_MTL 0x7d55 /* Meteor Lake Arc Graphics */
#define PCI_PRODUCT_INTEL_AHCI_MTL 0x7e63 /* Meteor Lake AHCI Controller */
#define PCI_PRODUCT_INTEL_USB32_MTL 0x7e7d /* Meteor Lake USB 3.2 Gen 2x1 xHCI Host Controller */
#define PCI_PRODUCT_INTEL_MPM_MTL 0x7e7f /* Meteor Lake Memory Power Management */
#define PCI_PRODUCT_INTEL_TB4USB_MTL 0x7ec0 /* Meteor Lake Thunderbolt 4 USB Controller */
#define PCI_PRODUCT_INTEL_SCH_IDE 0x811a /* SCH IDE Controller */
#define PCI_PRODUCT_INTEL_E600_HDA 0x811b /* E600 HD Audio */
#define PCI_PRODUCT_INTEL_E600_PCIB_0 0x8180 /* E600 Virtual PCI-PCI Bridge */
@@ -7614,6 +7650,8 @@
#define PCI_PRODUCT_INTEL_RPL_IGD_10 0xa7aa /* Raptor Lake Graphics (96 or 80EU) */
#define PCI_PRODUCT_INTEL_RPL_IGD_11 0xa7ac /* Raptor Lake Graphics (96 or 80EU) */
#define PCI_PRODUCT_INTEL_RPL_IGD_12 0xa7ad /* Raptor Lake Graphics (64EU) */
#define PCI_PRODUCT_INTEL_NPU_ARL 0xad1d /* Arrow Lake NPU */
#define PCI_PRODUCT_INTEL_NPU_PTL 0xb03e /* Panther Lake NPU */
#define PCI_PRODUCT_INTEL_21152 0xb152 /* S21152BB PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_21154 0xb154 /* S21152BA,S21154AE/BE PCI-PCI Bridge */
#define PCI_PRODUCT_INTEL_21555 0xb555 /* 21555 Non-Transparent PCI-PCI Bridge */
@@ -7850,7 +7888,13 @@
#define PCI_PRODUCT_MICREL_KSZ8842 0x8842 /* Switched 2 Port 10/100 Ethernet */
/* Micron/Crucial Technology products */
#define PCI_PRODUCT_MICRON_SM2263 0x2263 /* SM2263 NVMe Controller */
#define PCI_PRODUCT_MICRON_P1 0x2263 /* P1 NVMe SSD */
#define PCI_PRODUCT_MICRON_P1_1 0x5403 /* P1 NVMe SSD */
#define PCI_PRODUCT_MICRON_P5PLUS 0x5407 /* P5 Plus NVMe SSD */
#define PCI_PRODUCT_MICRON_P2P3P3P 0x540a /* P2 / P3 / P3 Plus NVMe SSD */
#define PCI_PRODUCT_MICRON_P5 0x5412 /* P5 NVMe SSD */
#define PCI_PRODUCT_MICRON_T500 0x5415 /* T500 NVMe SSD */
#define PCI_PRODUCT_MICRON_T700 0x5419 /* T700 NVMe SSD */
/* Middle Digital products */
#define PCI_PRODUCT_MIDDLE_DIGITAL_WEASEL_VGA 0x9050 /* Weasel Virtual VGA */
@@ -8344,6 +8388,7 @@
#define PCI_PRODUCT_NVIDIA_GEFORCE3_TI200 0x0201 /* GeForce3 Ti 200 */
#define PCI_PRODUCT_NVIDIA_GEFORCE3_TI500 0x0202 /* GeForce3 Ti 500 */
#define PCI_PRODUCT_NVIDIA_QUADRO_DCC 0x0203 /* Quadro DCC */
#define PCI_PRODUCT_NVIDIA_GEFORCE_6200A 0x0221 /* GeForce 6200A */
#define PCI_PRODUCT_NVIDIA_GEFORCE_6150 0x0240 /* GeForce 6150 */
#define PCI_PRODUCT_NVIDIA_GEFORCE_6150LE 0x0241 /* GeForce 6150 LE */
#define PCI_PRODUCT_NVIDIA_GEFORCE4_TI4600 0x0250 /* GeForce4 Ti 4600 */
@@ -8590,7 +8635,45 @@
#define PCI_PRODUCT_NVIDIA_GF108_HDA 0x0bea /* GF108 HD Audio */
#define PCI_PRODUCT_NVIDIA_GF116_HDA 0x0bee /* GF116 HD Audio */
#define PCI_PRODUCT_NVIDIA_GF_440 0x0de0 /* GeForce GT 440 */
#define PCI_PRODUCT_NVIDIA_GF_GT630 0x0f00 /* GeForce GT 630 */
#define PCI_PRODUCT_NVIDIA_GF_GT620 0x0f01 /* GeForce GT 620 */
#define PCI_PRODUCT_NVIDIA_GF_GT730_4 0x0f02 /* GeForce GT 730 */
#define PCI_PRODUCT_NVIDIA_GF_GT640_1 0x0fc0 /* GeForce GT 640 */
#define PCI_PRODUCT_NVIDIA_GF_GT640_2 0x0fc1 /* GeForce GT 640 */
#define PCI_PRODUCT_NVIDIA_GF_GT630_2 0x0fc2 /* GeForce GT 630 */
#define PCI_PRODUCT_NVIDIA_GF_GTX650 0x0fc6 /* GeForce GTX 650 */
#define PCI_PRODUCT_NVIDIA_GF_GT740 0x0fc8 /* GeForce GT 740 */
#define PCI_PRODUCT_NVIDIA_GF_GT730_3 0x0fc9 /* GeForce GT 730 */
#define PCI_PRODUCT_NVIDIA_GF_GT755M 0x0fcd /* GeForce GT 755M */
#define PCI_PRODUCT_NVIDIA_GF_GT640M_LE 0x0fce /* GeForce GT 640M LE */
#define PCI_PRODUCT_NVIDIA_GF_GT650M 0x0fd1 /* GeForce GT 650M */
#define PCI_PRODUCT_NVIDIA_GF_GT640M 0x0fd2 /* GeForce GT 640M */
#define PCI_PRODUCT_NVIDIA_GF_GT640M_LE_2 0x0fd3 /* GeForce GT 640M LE */
#define PCI_PRODUCT_NVIDIA_GF_GTX660M 0x0fd4 /* GeForce GTX 660M */
#define PCI_PRODUCT_NVIDIA_GF_GT650M_2 0x0fd5 /* GeForce GT 650M */
#define PCI_PRODUCT_NVIDIA_GF_GT640M_2 0x0fd8 /* GeForce GT 640M */
#define PCI_PRODUCT_NVIDIA_GF_GT645M 0x0fd9 /* GeForce GT 645M */
#define PCI_PRODUCT_NVIDIA_GF_GT740M_2 0x0fdf /* GeForce GT 740M */
#define PCI_PRODUCT_NVIDIA_GF_GTX660M_2 0x0fe0 /* GeForce GTX 660M */
#define PCI_PRODUCT_NVIDIA_GF_GT730M_2 0x0fe1 /* GeForce GT 730M */
#define PCI_PRODUCT_NVIDIA_GF_GT745M 0x0fe2 /* GeForce GT 745M */
#define PCI_PRODUCT_NVIDIA_GF_GT745M_2 0x0fe3 /* GeForce GT 745M */
#define PCI_PRODUCT_NVIDIA_GF_GT750M 0x0fe4 /* GeForce GT 750M */
#define PCI_PRODUCT_NVIDIA_GF_GT750M_2 0x0fe9 /* GeForce GT 750M */
#define PCI_PRODUCT_NVIDIA_GF_GT755M_2 0x0fea /* GeForce GT 755M */
#define PCI_PRODUCT_NVIDIA_GF_GT710A 0x0fec /* GeForce 710A */
#define PCI_PRODUCT_NVIDIA_GRID_K340 0x0fef /* GRID K340 */
#define PCI_PRODUCT_NVIDIA_GRID_K1 0x0ff2 /* GRID K1 */
#define PCI_PRODUCT_NVIDIA_QUADRO_K420 0x0ff3 /* Quadro K420 */
#define PCI_PRODUCT_NVIDIA_QUADRO_K1100M 0x0ff6 /* Quadro K1100M */
#define PCI_PRODUCT_NVIDIA_QUADRO_K500M 0x0ff8 /* Quadro K500M */
#define PCI_PRODUCT_NVIDIA_QUADRO_K2000D 0x0ff9 /* Quadro K2000D */
#define PCI_PRODUCT_NVIDIA_QUADRO_K600 0x0ffa /* Quadro K600 */
#define PCI_PRODUCT_NVIDIA_QUADRO_K2000M 0x0ffb /* Quadro K2000M */
#define PCI_PRODUCT_NVIDIA_QUADRO_K1000M 0x0ffc /* Quadro K1000M */
#define PCI_PRODUCT_NVIDIA_QUADRO_NVS510 0x0ffd /* NVS 510 */
#define PCI_PRODUCT_NVIDIA_QUADRO_K2000 0x0ffe /* Quadro K2000 */
#define PCI_PRODUCT_NVIDIA_QUADRO_410 0x0fff /* Quadro 410 */
#define PCI_PRODUCT_NVIDIA_GT520 0x1040 /* GeForce GT 520 */
#define PCI_PRODUCT_NVIDIA_GEFORCE_510 0x1042 /* GeForce 510 */
#define PCI_PRODUCT_NVIDIA_GEFORCE_605 0x1048 /* GeForce 605 */
@@ -8802,7 +8885,6 @@
#define PCI_PRODUCT_NVIDIA_GF_RTX2080M 0x1ed0 /* GeForce RTX 2080 Mobile */
#define PCI_PRODUCT_NVIDIA_GF_RTX2070SM 0x1ed1 /* GeForce RTX 2070 SUPER Mobile / Max-Q */
#define PCI_PRODUCT_NVIDIA_GF_RTX2080SM 0x1ed3 /* GeForce RTX 2080 SUPER Mobile / Max-Q */
#define PCI_PRODUCT_NVIDIA_GF_RTX2070 0x1f02 /* GeForce RTX 2070 */
#define PCI_PRODUCT_NVIDIA_GF_RTX2060S 0x1f06 /* GeForce RTX 2060 SUPER */
#define PCI_PRODUCT_NVIDIA_GF_RTX2070_2 0x1f07 /* GeForce RTX 2070 Rev. A */
@@ -8956,13 +9038,20 @@
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_0 0xc101 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_1 0xc105 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952P 0xc110 /* OXPCIe952 Parallel */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952SN1 0xc11b /* OXPCIe952 1 Native Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_2S 0xc120 /* OXPCIe952 2 Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_2 0xc124 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952SN1_2 0xc138 /* OXPCIe952 1 Native Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_3 0xc140 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_4 0xc141 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_5 0xc144 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952_6 0xc145 /* OXPCIe952 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952SN2 0xc158 /* OXPCIe952 2 Native Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE952SN2_2 0xc15d /* OXPCIe952 2 Native Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE954 0xc208 /* OXPCIe954 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE954SN4 0xc20d /* OXPCIe954 4 Native Serial */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE958 0xc308 /* OXPCIe958 */
#define PCI_PRODUCT_OXFORDSEMI_OXPCIE958SN8 0xc30d /* OXPCIe958 8 Native Serial */
/* Packet Engines products */
#define PCI_PRODUCT_PACKETENGINES_GNICII 0x0911 /* G-NIC II Ethernet */
@@ -9203,7 +9292,6 @@
#define PCI_PRODUCT_QUMRANET_VIRTIO_103D 0x103d /* Virtio */
#define PCI_PRODUCT_QUMRANET_VIRTIO_103E 0x103e /* Virtio */
#define PCI_PRODUCT_QUMRANET_VIRTIO_103F 0x103f /* Virtio */
#define PCI_PRODUCT_QUMRANET_VIRTIO_1040 0x1040 /* Virtio */
#define PCI_PRODUCT_QUMRANET_VIRTIO_1041 0x1041 /* Virtio Network */
#define PCI_PRODUCT_QUMRANET_VIRTIO_1042 0x1042 /* Virtio Storage */
@@ -9351,6 +9439,7 @@
#define PCI_PRODUCT_REALTEK_RT8100 0x8100 /* 8100 10/100 Ethernet */
#define PCI_PRODUCT_REALTEK_RT8125 0x8125 /* 8125 10/100/1G/2.5G Ethernet */
#define PCI_PRODUCT_REALTEK_RT8126 0x8126 /* 8126 10/100/1G/2.5G/5G Ethernet */
#define PCI_PRODUCT_REALTEK_RT8127 0x8127 /* 8127 10/100/1G/2.5G/5G Ethernet */
#define PCI_PRODUCT_REALTEK_RT8129 0x8129 /* 8129 10/100 Ethernet */
#define PCI_PRODUCT_REALTEK_RT8101E 0x8136 /* 8100E/8101E/8102E 10/100 Ethernet */
#define PCI_PRODUCT_REALTEK_RT8138 0x8138 /* 8138 10/100 Ethernet */
@@ -9987,22 +10076,27 @@
/* VIA Technologies products, from http://www.via.com.tw/ */
#define PCI_PRODUCT_VIATECH_VT6305 0x0130 /* VT6305 IEEE 1394 Host Controller */
#define PCI_PRODUCT_VIATECH_K8M800_0 0x0204 /* K8M800 Host */
#define PCI_PRODUCT_VIATECH_K8T890_0 0x0238 /* K8T890 Host */
#define PCI_PRODUCT_VIATECH_K8M800_0 0x0204 /* K8M800 Host Controller */
#define PCI_PRODUCT_VIATECH_K8T890_0 0x0238 /* K8T890 Host Controller */
#define PCI_PRODUCT_VIATECH_CN400_AGP 0x0259 /* CN333/CN400/PM880 AGP */
#define PCI_PRODUCT_VIATECH_KT880 0x0269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_K8HTB_0 0x0282 /* K8HTB Host */
#define PCI_PRODUCT_VIATECH_VT8363_HB 0x0305 /* VT8363 (Apollo KT133) Host Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_HB 0x0327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB 0x0336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT3351_HB_0351 0x0351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_HC 0x0353 /* VX800/VX820 Host Controller */
#define PCI_PRODUCT_VIATECH_P4M900 0x0364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8371_HB 0x0391 /* VT8371 (Apollo KX133) Host Bridge */
#define PCI_PRODUCT_VIATECH_VX855_HB 0x0409 /* VX855 Host Control */
#define PCI_PRODUCT_VIATECH_VX900_HB 0x0410 /* VX900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VT6415_IDE 0x0415 /* VT6415/VT6330 IDE Controller */
#define PCI_PRODUCT_VIATECH_VT8501_MVP4 0x0501 /* VT8501 (Apollo MVP4) Host Bridge */
#define PCI_PRODUCT_VIATECH_VT82C505 0x0505 /* VT82C505 (Pluto) */
#define PCI_PRODUCT_VIATECH_VT82C561 0x0561 /* VT82C561 */
#define PCI_PRODUCT_VIATECH_VT82C586A_IDE 0x0571 /* VT82C586A IDE Controller */
#define PCI_PRODUCT_VIATECH_VT82C576 0x0576 /* VT82C576 3V */
#define PCI_PRODUCT_VIATECH_CX700_IDE 0x0581 /* CX700 IDE Controller */
#define PCI_PRODUCT_VIATECH_CX700_IDE 0x0581 /* CX700(M2)/VX700/VX800 SATA/IDE RAID Controller */
#define PCI_PRODUCT_VIATECH_VT82C580VP 0x0585 /* VT82C580 (Apollo VP) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT82C586_ISA 0x0586 /* VT82C586 PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_SATA 0x0591 /* VT8237A Integrated SATA Controller */
@@ -10010,6 +10104,7 @@
#define PCI_PRODUCT_VIATECH_VT82C596A 0x0596 /* VT82C596A PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT82C597 0x0597 /* VT82C597 (Apollo VP3) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT82C598PCI 0x0598 /* VT82C598 (Apollo MVP3) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8601A_HB 0x0601 /* VT8601A (Apollo PLE133) Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8605PCI 0x0605 /* VT8605 (Apollo ProMedia 133) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT82C686A_ISA 0x0686 /* VT82C686A PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT82C691 0x0691 /* VT82C691 (Apollo Pro) Host-PCI */
@@ -10018,27 +10113,39 @@
#define PCI_PRODUCT_VIATECH_VT82C570M 0x1000 /* VT82C570M (Apollo) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT82C570MV 0x1006 /* VT82C570M (Apollo) PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_CHROME9HC3 0x1122 /* VX800/VX820 Chrome 9 HC3 Integrated Graphics */
#define PCI_PRODUCT_VIATECH_K8T890_ERR 0x1238 /* K8T890 Error Reporting */
#define PCI_PRODUCT_VIATECH_CN400_ERR 0x1259 /* CN333/CN400/PM880 Error Reporting */
#define PCI_PRODUCT_VIATECH_KT880_1 0x1269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_HB_2 0x1327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_2 0x1336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT3351_HB_1351 0x1351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_ERR 0x1353 /* VX800/VX820 Error Reporting */
#define PCI_PRODUCT_VIATECH_P4M900_1 0x1364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX855_ERR 0x1409 /* VX855 Error Reporting */
#define PCI_PRODUCT_VIATECH_VX900_ERR 0x1410 /* VX900 Error Reporting */
#define PCI_PRODUCT_VIATECH_VT82C586_IDE 0x1571 /* VT82C586 IDE Controller */
#define PCI_PRODUCT_VIATECH_VT82C595_2 0x1595 /* VT82C595 (Apollo VP2) Host-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT6105M_BOM 0x2006 /* VT6105M_BOM (Rhine III) 10/100 Ethernet */
#define PCI_PRODUCT_VIATECH_K8T890_HBC 0x2238 /* K8T890 Host Bus Control */
#define PCI_PRODUCT_VIATECH_CN400_HCB 0x2259 /* CN333/CN400/PM880 Host CPU Bus */
#define PCI_PRODUCT_VIATECH_KT880_2 0x2269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_HB_3 0x2327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_3 0x2336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT3351_HB_2351 0x2351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_HBC 0x2353 /* VX800/VX820 Host Bus Control */
#define PCI_PRODUCT_VIATECH_P4M900_2 0x2364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX855_HBC 0x2409 /* VX855 Host Bus Control */
#define PCI_PRODUCT_VIATECH_VX900_0 0x2410 /* VX900 CPU Bus Controller */
#define PCI_PRODUCT_VIATECH_VT8251_PPB_287A 0x287a /* VT8251 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8251_HB 0x287b /* VT8251 Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8251_PCIE1 0x287c /* VT8251 PCIe Root Port1 */
#define PCI_PRODUCT_VIATECH_VT8251_PCIE2 0x287d /* VT8251 PCIe Root Port2 */
#define PCI_PRODUCT_VIATECH_VT8251_VLINK 0x287e /* VT8251 Ultra VLINK Controller */
#define PCI_PRODUCT_VIATECH_VT8251_VLINK 0x287e /* VT8237A/VT8237S/VT8251 Ultra VLINK Controller */
#define PCI_PRODUCT_VIATECH_VT83C572 0x3038 /* VT83C572 USB Controller */
#define PCI_PRODUCT_VIATECH_VT82C586_PWR 0x3040 /* VT82C586 Power Management Controller */
#define PCI_PRODUCT_VIATECH_VT3043 0x3043 /* VT3043 (Rhine) 10/100 Ethernet */
#define PCI_PRODUCT_VIATECH_VT6306 0x3044 /* VT6306 IEEE 1394 Host Controller */
#define PCI_PRODUCT_VIATECH_VT82C596B_PWR 0x3050 /* VT82C596B Power Management Controller */
#define PCI_PRODUCT_VIATECH_VT6105M 0x3053 /* VT6105M (Rhine III) 10/100 Ethernet */
#define PCI_PRODUCT_VIATECH_VT82C686A_PWR 0x3057 /* VT82C686A Power Management Controller */
#define PCI_PRODUCT_VIATECH_VT82C686A_AC97 0x3058 /* VT82C686A AC-97 Audio Controller */
@@ -10050,58 +10157,94 @@
#define PCI_PRODUCT_VIATECH_VT8653 0x3101 /* VT8653 (Apollo Pro 266T) CPU-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8237_EHCI 0x3104 /* VT8237 EHCI USB Controller */
#define PCI_PRODUCT_VIATECH_VT6105 0x3106 /* VT6105 (Rhine III) 10/100 Ethernet */
#define PCI_PRODUCT_VIATECH_VT3108_IG 0x3108 /* K8M800/K8N800(A) UniChrome Pro IGP */
#define PCI_PRODUCT_VIATECH_VT8233C 0x3109 /* VT8233C PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT3118_IG 0x3118 /* CN400/PM8x0/PN8x0 UniChrome Pro IGP */
#define PCI_PRODUCT_VIATECH_VT612X 0x3119 /* VT612X (Velocity) 10/100/1000 Ethernet */
#define PCI_PRODUCT_VIATECH_VT8623_VGA 0x3122 /* VT8623 (Apollo CLE266) VGA Controller */
#define PCI_PRODUCT_VIATECH_VT8623 0x3123 /* VT8623 (Apollo CLE266) CPU-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8233A 0x3147 /* VT8233A PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8751_HB 0x3148 /* P4M266 Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8237_SATA 0x3149 /* VT8237 Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT3157_IG 0x3157 /* CX700/VX700 Unichrome Pro IGP */
#define PCI_PRODUCT_VIATECH_VT6410_RAID 0x3164 /* VT6410 ATA133 RAID Controller */
#define PCI_PRODUCT_VIATECH_VT8235 0x3177 /* VT8235 (Apollo KT400) PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8235 0x3177 /* VT8235 Bus Control & Power Management */
#define PCI_PRODUCT_VIATECH_K8HTB 0x3188 /* K8HTB Host */
#define PCI_PRODUCT_VIATECH_VT8377 0x3189 /* VT8377 Apollo KT400 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8378 0x3205 /* VT8378 Apollo KM400 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8237 0x3227 /* VT8237 PCI-LPC Bridge */
#define PCI_PRODUCT_VIATECH_K8T890_DRAM 0x3238 /* K8T890 DRAM Bus Control */
#define PCI_PRODUCT_VIATECH_VT3230_IG 0x3230 /* K8M890CE/K8N890CE Chrome 9 IGP */
#define PCI_PRODUCT_VIATECH_VT6421_RAID 0x3249 /* VT6421 Serial RAID Controller */
#define PCI_PRODUCT_VIATECH_CN400_DRAM 0x3259 /* CN333/CN400/PM880 DRAM Bus Control */
#define PCI_PRODUCT_VIATECH_KT880_3 0x3269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8251 0x3287 /* VT8251 PCI-LPC Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_HDA 0x3288 /* VT8237A/VT8251 High Definition Audio Controller */
#define PCI_PRODUCT_VIATECH_P4M890_HB_4 0x3327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_4 0x3336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_ISA 0x3337 /* VT8237A/VT82C586A PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT3314_IG 0x3344 /* VT3314 CN900 UniChrome Integrated Graphics */
#define PCI_PRODUCT_VIATECH_VT8237R_SATA 0x3349 /* VT8237R Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT3343_IG 0x3343 /* P4M890 UniChrome Pro IGP */
#define PCI_PRODUCT_VIATECH_VT3314_IG 0x3344 /* CN700/P4M800 (Pro/CE)/VN800 UniChrome Pro IGP */
#define PCI_PRODUCT_VIATECH_VT8251_SATA 0x3349 /* VT8251 Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT3351_HB_3351 0x3351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_PPB_2 0x3353 /* VX800/VX820 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M900_3 0x3364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_CHROME9_HC 0x3371 /* Chrome9 HC IGP */
#define PCI_PRODUCT_VIATECH_VT3371_IG 0x3371 /* CN896/VN896/P4M900 Chrome9 HC IGP */
#define PCI_PRODUCT_VIATECH_VT8237S_ISA 0x3372 /* VT8237S PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_PPB 0x337a /* VT8237A PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_HB 0x337b /* VT8237A Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_PPB 0x337a /* VT8237A/S PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8237A_HB 0x337b /* VT8237A/S Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8261 0x3402 /* VT8261 PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT6315_FW 0x3403 /* VT6315/VT6330 FireWire Controller */
#define PCI_PRODUCT_VIATECH_VX855_DRAM 0x3409 /* VX855 DRAM Bus Control */
#define PCI_PRODUCT_VIATECH_VX900_DRAM 0x3410 /* VX900 DRAM Controller */
#define PCI_PRODUCT_VIATECH_VL80x_XHCI 0x3432 /* VL80x xHCI */
#define PCI_PRODUCT_VIATECH_VL805_XHCI 0x3483 /* VL805 xHCI */
#define PCI_PRODUCT_VIATECH_CHROME_645_IGP 0x3a01 /* VX11 Graphics [Chrome 645/640] */
#define PCI_PRODUCT_VIATECH_K8T890_PMC 0x4238 /* K8T890 Power Management Control */
#define PCI_PRODUCT_VIATECH_CN400_PMC 0x4259 /* CN333/CN400/PM880 Power Management Control */
#define PCI_PRODUCT_VIATECH_KT880_4 0x4269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_HB_5 0x4327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_5 0x4336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT3351_HB_4351 0x4351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_PMC 0x4353 /* VX800/VX820 Power Management Control */
#define PCI_PRODUCT_VIATECH_P4M900_4 0x4364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX855_PMC 0x4409 /* VX855 Power Management Control */
#define PCI_PRODUCT_VIATECH_VX900_1 0x4410 /* VX900 Power Management Controller */
#define PCI_PRODUCT_VIATECH_CX700M2_IDE 0x5324 /* CX700M2/VX700 IDE Controller */
#define PCI_PRODUCT_VIATECH_VX800_IG 0x5122 /* VX855/VX875 Chrome9 HCM IGP */
#define PCI_PRODUCT_VIATECH_K8T890_IOAPIC 0x5238 /* K8T890 APIC and Central Traffic Control */
#define PCI_PRODUCT_VIATECH_VT8251_SATA_2 0x5287 /* VT8251 Integrated SATA Controller (IDE mode) */
#define PCI_PRODUCT_VIATECH_CX700M2_IDE 0x5324 /* CX700(M2)/VX700/VX800/VX820 IDE Controller */
#define PCI_PRODUCT_VIATECH_P4M890_IOAPIC 0x5327 /* P4M890/PT890 I/O APIC Interrupt Controller */
#define PCI_PRODUCT_VIATECH_K8M890CE_IOAPIC 0x5336 /* K8M890CE I/O APIC Interrupt Controller */
#define PCI_PRODUCT_VIATECH_VT8237A_SATA_2 0x5337 /* VT8237A Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT3351_IOAPIC 0x5351 /* VT3351 I/O APIC Interrupt Controller */
#define PCI_PRODUCT_VIATECH_VX800_APIC 0x5353 /* VX800/VX820 APIC and Central Traffic Control */
#define PCI_PRODUCT_VIATECH_P4M900_IOAPIC 0x5364 /* CN896/P4M900 IOAPIC */
#define PCI_PRODUCT_VIATECH_VT8237S_SATA 0x5372 /* VT8237S Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VX855_APIC 0x5409 /* VX855 APIC and Central Traffic Control */
#define PCI_PRODUCT_VIATECH_VX900_APIC 0x5410 /* VX900 APIC and Traffic Controller */
#define PCI_PRODUCT_VIATECH_VT86C100A 0x6100 /* VT86C100A (Rhine-II) 10/100 Ethernet */
#define PCI_PRODUCT_VIATECH_VT8251_SATA 0x6287 /* VT8251 Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_CHROME520_IGP 0x6122 /* VN1000 Graphics [Chrome 520 IGP] */
#define PCI_PRODUCT_VIATECH_K8T890_SCRATCH 0x6238 /* K8T890 Scratch Registers */
#define PCI_PRODUCT_VIATECH_VT8251_AHCI 0x6287 /* VT8251 Integrated AHCI SATA Controller */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_6 0x6290 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_SECURITY 0x6327 /* P4M890/PT890 Security Device */
#define PCI_PRODUCT_VIATECH_VX800_SCRATCH 0x6353 /* VX800/VX820 Scratch Registers */
#define PCI_PRODUCT_VIATECH_P4M900_6 0x6364 /* CN896/P4M900 Security Device */
#define PCI_PRODUCT_VIATECH_VX855_SCRATCH 0x6409 /* VX855 Scratch Registers */
#define PCI_PRODUCT_VIATECH_VX900_SCRATCH 0x6410 /* VX900 Scratch Registers */
#define PCI_PRODUCT_VIATECH_CHROME9_HD 0x7122 /* VX900 Graphics [Chrome9 HD] */
#define PCI_PRODUCT_VIATECH_VT8378_IG 0x7205 /* VT8378 KM400 UniChrome Integrated Graphics */
#define PCI_PRODUCT_VIATECH_VT7205_IG 0x7205 /* KM400/KN400/P4M800 UniChrome IGP */
#define PCI_PRODUCT_VIATECH_K8T890_VLINK 0x7238 /* K8T890 V-Link Control */
#define PCI_PRODUCT_VIATECH_CN400_VLINK 0x7259 /* CN333/CN400/PM880 V-Link Control */
#define PCI_PRODUCT_VIATECH_KT880_5 0x7269 /* KT880 CPU to PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_HB_6 0x7327 /* P4M890/PT890 Host Bridge */
#define PCI_PRODUCT_VIATECH_K8M890CE_HB_7 0x7336 /* K8M890CE Host Bridge */
#define PCI_PRODUCT_VIATECH_VT3351_HB_7351 0x7351 /* VT3351 Host Bridge */
#define PCI_PRODUCT_VIATECH_VX800_1 0x7353 /* VX800/VX820 North-South Module Interface Control */
#define PCI_PRODUCT_VIATECH_P4M900_7 0x7364 /* CN896/P4M900 Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID 0x7372 /* VT8237S Integrated SATA Controller (RAID mode) */
#define PCI_PRODUCT_VIATECH_VX855_NSMIC 0x7409 /* VX855 North-South Module Interface Control */
#define PCI_PRODUCT_VIATECH_VX900_2 0x7410 /* VX900 North-South Module Interface Control */
#define PCI_PRODUCT_VIATECH_VT8231 0x8231 /* VT8231 PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8231_PWR 0x8235 /* VT8231 Power Management Controller */
@@ -10109,16 +10252,26 @@
#define PCI_PRODUCT_VIATECH_CX700 0x8324 /* CX700 PCI-LPC Bridge */
#define PCI_PRODUCT_VIATECH_VX800 0x8353 /* VX800/VX820 PCI-LPC Bridge */
#define PCI_PRODUCT_VIATECH_VT8371_PPB 0x8391 /* VT8371 (Apollo KX133) PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX855 0x8409 /* VX855 PCI-LPC Bridge */
#define PCI_PRODUCT_VIATECH_VX855 0x8409 /* VX855 Bus Control and Power Management */
#define PCI_PRODUCT_VIATECH_VX900 0x8410 /* VX900 Bus Control and Power Management */
#define PCI_PRODUCT_VIATECH_VT8501AGP 0x8501 /* VT8501 (Apollo MVP4) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT82C597AGP 0x8597 /* VT82C597 (Apollo VP3) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT82C598AGP 0x8598 /* VT82C598 (Apollo MVP3) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT8601AGP 0x8601 /* VT8601A (Apollo PLE 133) PCI to AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT8605AGP 0x8605 /* VT8605 (Apollo ProMedia 133) Host-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VX900_IDE 0x9001 /* VX900 IDE Controller */
#define PCI_PRODUCT_VIATECH_VT8261_SATA 0x9000 /* VT8261 Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VX900_IDE 0x9001 /* VX900/VX11 Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT8261_RAID 0x9040 /* VT8261 Integrated SATA Controller (RAID mode) */
#define PCI_PRODUCT_VIATECH_VX900_RAID 0x9041 /* VX900/VX11 Integrated SATA Controller (RAID mode) */
#define PCI_PRODUCT_VIATECH_VX900_AHCI 0x9082 /* VX900/VX11 Integrated AHCI SATA Controller */
#define PCI_PRODUCT_VIATECH_VX11_XHCI 0x9201 /* VX11 USB 3.0 xHCI Controller */
#define PCI_PRODUCT_VIATECH_VX800_SD 0x9530 /* VX800/VX900 SD Card Controller */
#define PCI_PRODUCT_VIATECH_VX800_SDIO 0x95d0 /* VX800/VX900 SDIO Host Controller */
#define PCI_PRODUCT_VIATECH_K8T890_PPB_A238 0xa238 /* K8T890 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_PPB_A327 0xa327 /* P4M890/PT890 PCI to PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX800_0 0xa353 /* VX8xx/VX900 South-North Module Interface Control */
#define PCI_PRODUCT_VIATECH_P4M900_PPB_1 0xa364 /* CN896/P4M900 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX855_USBD 0xa409 /* VX855 USB Device */
#define PCI_PRODUCT_VIATECH_VX900_PCIE_0 0xa410 /* VX900 PCI Express Root Port 0 */
#define PCI_PRODUCT_VIATECH_VT8633AGP 0xb091 /* VT8633 (Apollo Pro 266) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT8366AGP 0xb099 /* VT8366 (Apollo KT266) CPU-AGP Bridge */
@@ -10129,8 +10282,10 @@
#define PCI_PRODUCT_VIATECH_VX900_PCIE_1 0xb410 /* VX900 PCI Express Root Port 1 */
#define PCI_PRODUCT_VIATECH_VT3237_PPB 0xb999 /* K8T890 North / VT8237 South PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_K8T890_PPB_C238 0xc238 /* K8T890 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_P4M890_PPB_C327 0xc327 /* P4M890/PT890 PCI to PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX800_PCIE_G0 0xc353 /* VX800/VX820 PCI Express Root Port G0 */
#define PCI_PRODUCT_VIATECH_P4M900_PPB_2 0xc364 /* CN896/P4M900 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX855_IDE 0xc409 /* VX855/VX875 EIDE Controller */
#define PCI_PRODUCT_VIATECH_VX900_PCIE_2 0xc410 /* VX900 PCI Express Root Port 2 */
#define PCI_PRODUCT_VIATECH_K8T890_PPB_D238 0xd238 /* K8T890 PCI-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VX900_PCIE_3 0xd410 /* VX900 PCI Express Root Port 3 */
lib/libc/include/generic-netbsd/dev/pci/pcidevs_data.h
Vendored
+15270 -14887
View File
File diff suppressed because it is too large Load Diff
lib/libc/include/generic-netbsd/dev/pci/pcireg.h
Vendored
+14 -14
View File
@@ -1,4 +1,4 @@
/* $NetBSD: pcireg.h,v 1.168.2.1 2024/06/22 11:01:18 martin Exp $ */
/* $NetBSD: pcireg.h,v 1.172 2024/12/31 14:00:35 skrll Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -50,8 +50,8 @@
*/
#define PCI_ID_REG 0x00
typedef u_int16_t pci_vendor_id_t;
typedef u_int16_t pci_product_id_t;
typedef uint16_t pci_vendor_id_t;
typedef uint16_t pci_product_id_t;
#define PCI_VENDOR_SHIFT 0
#define PCI_VENDOR_MASK 0xffffU
@@ -129,10 +129,10 @@ typedef u_int16_t pci_product_id_t;
*/
#define PCI_CLASS_REG 0x08
typedef u_int8_t pci_class_t;
typedef u_int8_t pci_subclass_t;
typedef u_int8_t pci_interface_t;
typedef u_int8_t pci_revision_t;
typedef uint8_t pci_class_t;
typedef uint8_t pci_subclass_t;
typedef uint8_t pci_interface_t;
typedef uint8_t pci_revision_t;
#define PCI_CLASS_SHIFT 24
#define PCI_CLASS_MASK 0xffU
@@ -1302,10 +1302,10 @@ struct pci_msix_table_entry {
*/
#define PCI_INTERRUPT_REG 0x3c
typedef u_int8_t pci_intr_latency_t;
typedef u_int8_t pci_intr_grant_t;
typedef u_int8_t pci_intr_pin_t;
typedef u_int8_t pci_intr_line_t;
typedef uint8_t pci_intr_latency_t;
typedef uint8_t pci_intr_grant_t;
typedef uint8_t pci_intr_pin_t;
typedef uint8_t pci_intr_line_t;
#define PCI_MAX_LAT_SHIFT 24
#define PCI_MAX_LAT_MASK 0xff
@@ -1963,8 +1963,8 @@ struct pci_rom {
#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
#define PCI_EA_PROP_IO 0x02 /* I/O Space */
#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resource for VF use. Mem. Non-Pref */
#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resource for VF use. Mem. Prefetch */
#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
@@ -2116,7 +2116,7 @@ struct pci_rom {
#define PCI_DPCCTL_DLACTECOR __BIT(23) /* DL_Active ERR_COR Enable */
#define PCI_DPC_STATESID 0x08 /* Status and Error Source ID Register */
#define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Staus */
#define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Status */
#define PCI_DPCSTAT_TREASON __BITS(2, 1) /* DPC Trigger Reason */
#define PCI_DPCSTAT_ISTAT __BIT(3) /* DPC Interrupt Status */
#define PCI_DPCSTAT_RPBUSY __BIT(4) /* DPC RP Busy */
lib/libc/include/generic-netbsd/dev/pckbc/pckbdreg.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: pckbdreg.h,v 1.3 2013/03/06 03:26:17 christos Exp $ */
/* $NetBSD: pckbdreg.h,v 1.4 2023/07/16 19:09:07 christos Exp $ */
/*
* Keyboard definitions
@@ -11,6 +11,7 @@
#define KBC_DISABLE 0xF5 /* as per KBC_SETDEFAULT, but also disable key scanning */
#define KBC_ENABLE 0xF4 /* enable key scanning */
#define KBC_TYPEMATIC 0xF3 /* set typematic rate and delay */
#define KBC_GETID 0xF2 /* get keyboard ID */
#define KBC_SETTABLE 0xF0 /* set scancode translation table */
#define KBC_MODEIND 0xED /* set mode indicators (i.e. LEDs) */
#define KBC_ECHO 0xEE /* request an echo from the keyboard */
lib/libc/include/generic-netbsd/dev/pcmcia/if_rayreg.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: if_rayreg.h,v 1.12 2022/05/22 11:27:35 andvar Exp $ */
/* $NetBSD: if_rayreg.h,v 1.13 2025/02/17 22:37:26 andvar Exp $ */
/*
* Copyright (c) 2000 Christian E. Hopps
* All rights reserved.
@@ -451,7 +451,7 @@ struct ray_cmd_update_mcast {
};
/* RAY_CMD_UPDATE_APM */
struct ray_cmd_udpate_apm {
struct ray_cmd_update_apm {
u_int8_t c_status; /* ccs generic header */
u_int8_t c_cmd; /* " */
u_int8_t c_link; /* " */
lib/libc/include/generic-netbsd/dev/raidframe/raidframeio.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: raidframeio.h,v 1.11.6.1 2024/04/28 12:09:08 martin Exp $ */
/* $NetBSD: raidframeio.h,v 1.12 2023/09/17 20:07:39 oster Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
* All rights reserved.
lib/libc/include/generic-netbsd/dev/scsipi/scsi_disk.h
Vendored
+42 -7
View File
@@ -1,4 +1,4 @@
/* $NetBSD: scsi_disk.h,v 1.34 2021/11/10 16:17:34 msaitoh Exp $ */
/* $NetBSD: scsi_disk.h,v 1.38 2025/02/27 17:17:00 jakllsch Exp $ */
/*
* SCSI-specific interface description
@@ -136,9 +136,9 @@ struct scsi_defect_descriptor_psf {
};
/*
* XXX for now this isn't in the ATAPI specs, but if there are on day
* XXX for now this isn't in the ATAPI specs, but if there are one day
* ATAPI hard disks, it is likely that they implement this command (or a
* command like this ?
* command like this?).
*/
#define SCSI_REASSIGN_BLOCKS 0x07
struct scsi_reassign_blocks {
@@ -298,7 +298,7 @@ union scsi_disk_pages {
u_int8_t rpm[2]; /* media rotation speed */
u_int8_t reserved2;
u_int8_t reserved3;
} rigid_geometry;
} rigid_geometry;
struct page_flex_geometry {
u_int8_t pg_code; /* page code (should be 5) */
u_int8_t pg_length; /* page length (should be 0x1e) */
@@ -333,7 +333,7 @@ union scsi_disk_pages {
u_int8_t pg_length; /* page length (should be 0x0a) */
u_int8_t flags; /* cache parameter flags */
#define CACHING_RCD 0x01 /* read cache disable */
#define CACHING_MF 0x02 /* multiplcation factor */
#define CACHING_MF 0x02 /* multiplication factor */
#define CACHING_WCE 0x04 /* write cache enable (write-back) */
#define CACHING_SIZE 0x08 /* use CACHE SEGMENT SIZE */
#define CACHING_DISC 0x10 /* pftch across time discontinuities */
@@ -364,13 +364,13 @@ union scsi_disk_pages {
u_int8_t pg_code; /* page code (should be 0x0a) */
u_int8_t pg_length; /* page length (should be 0x0a) */
u_int8_t ctl_flags1; /* First set of flags */
#define CTL1_TST_PER_INTR 0x40 /* Task set per initiator */
#define CTL1_TST_PER_INTR 0x40 /* Task set per initiator */
#define CTL1_TST_FIELD 0xe0 /* Full field */
#define CTL1_D_SENSE 0x04 /* Descriptor-format sense return */
#define CTL1_GLTSD 0x02 /* Glob. Log Targ. Save Disable */
#define CTL1_RLEC 0x01 /* Rpt Logging Exception Condition */
u_int8_t ctl_flags2; /* Second set of flags */
#define CTL2_QAM_UNRESTRICT 0x10 /* Unrestricted reordering allowed */
#define CTL2_QAM_UNRESTRICT 0x10 /* Unrestricted reordering allowed */
#define CTL2_QAM_FIELD 0xf0 /* Full Queue alogo. modifier field */
#define CTL2_QERR_ABRT 0x02 /* Queue error - abort all */
#define CTL2_QERR_ABRT_SELF 0x06 /* Queue error - abort intr's */
@@ -394,4 +394,39 @@ union scsi_disk_pages {
} control_params;
};
struct scsi_vpd_logical_block_provisioning {
struct {
/*1*/ u_int8_t device;
/*2*/ u_int8_t pagecode;
/*3*/ u_int8_t length[2];
};
/*4*/ u_int8_t threshold_exponent;
/*5*/ u_int8_t flags;
#define VPD_LBP_LBPU 0x80
#define VPD_LBP_LBPWS 0x40
#define VPD_LBP_LBPWS10 0x20
/*6*/ u_int8_t reserved6[2];
} __packed;
#define UNMAP_10 0x42
struct scsi_unmap_10 {
u_int8_t opcode;
u_int8_t byte2;
u_int8_t reserved3[4];
u_int8_t byte7;
u_int8_t length[2];
u_int8_t control;
} __packed;
struct scsi_unmap_10_data {
u_int8_t unmap_data_length[2];
u_int8_t unmap_block_descriptor_data_length[2];
u_int8_t reserved5[4];
struct {
u_int8_t addr[8];
u_int8_t len[4];
u_int8_t reserved13[4];
} unmap_block_descriptor[1];
} __packed;
#endif /* _DEV_SCSIPI_SCSI_DISK_H_ */
lib/libc/include/generic-netbsd/dev/scsipi/scsi_spc.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: scsi_spc.h,v 1.7 2022/01/27 18:37:02 jakllsch Exp $ */
/* $NetBSD: scsi_spc.h,v 1.8 2024/02/09 22:08:36 andvar Exp $ */
/*-
* Copyright (c) 2005 The NetBSD Foundation, Inc.
@@ -443,7 +443,7 @@ struct scsi_repsuppopcode {
#define RSOC_ALL 0x00 /* report all */
#define RSOC_ONE 0x01 /* report one */
#define RSOC_ONESACD 0x02 /* report one or CHECK CONDITION */
#define RSOC_ONESA 0x03 /* report one mark presense in data */
#define RSOC_ONESA 0x03 /* report one mark presence in data */
#define RSOC_RCTD 0x80 /* report timeouts */
u_int8_t reqopcode;
lib/libc/include/generic-netbsd/dev/scsipi/scsipi_all.h
Vendored
+83 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: scsipi_all.h,v 1.33 2007/12/25 18:33:42 perry Exp $ */
/* $NetBSD: scsipi_all.h,v 1.35 2025/02/10 14:42:33 jakllsch Exp $ */
/*
* SCSI and SCSI-like general interface description
@@ -59,7 +59,9 @@
struct scsipi_inquiry {
u_int8_t opcode;
u_int8_t byte2;
u_int8_t unused[2];
#define SINQ_EVPD 0x01
u_int8_t pagecode;
u_int8_t length_hi; /* upper byte of length */
u_int8_t length;
u_int8_t control;
} __packed;
@@ -165,4 +167,83 @@ struct scsipi_inquiry_data {
#define SCSIPI_INQUIRY_LENGTH_SCSI3 74
} __packed; /* 74 Bytes */
/* Vital product data when SINQ_EVPD is set */
struct scsipi_inquiry_evpd_header {
/* 1*/ u_int8_t device;
/* 2*/ u_int8_t pagecode;
/* 3*/ u_int8_t length[2];
};
#define SINQ_VPD_PAGES 0x00
#define SINQ_VPD_UNIT_SERIAL 0x80
#define SINQ_VPD_DEVICE_ID 0x83
#define SINQ_VPD_SOFTWARE_ID 0x84
#define SINQ_VPD_MN_ADDRESS 0x85
#define SINQ_VPD_INQUIRY 0x86
#define SINQ_VPD_MP_POLICY 0x87
#define SINQ_VPD_PORTS 0x88
#define SINQ_VPD_POWER_COND 0x8a
#define SINQ_VPD_CONSTITUENTS 0x8b
#define SINQ_VPD_CFA_PROFILE 0x8c
#define SINQ_VPD_CONSUMPTION 0x8d
#define SINQ_VPD_BLOCK_LIMITS 0xb0
#define SINQ_VPD_BLOCK_CHARS 0xb1
#define SINQ_VPD_LOGICAL_PROV 0xb2
#define SINQ_VPD_REFERRALS 0xb3
#define SINQ_VPD_SUPPORTED 0xb4
#define SINQ_VPD_BLOCK_CHARSX 0xb5
#define SINQ_VPD_BLOCK_ZONED 0xb6
#define SINQ_VPD_BLOCK_LIMITSX 0xb7
#define SINQ_VPD_FIRMWARE_NUM 0xc0
#define SINQ_VPD_JUMPERS 0xc2
#define SINQ_VPD_BEHAVIOUR 0xc3
#define SINQ_VPD_DATE_CODE 0xc1
struct scsipi_inquiry_evpd_date_code {
/* 1*/ u_int8_t etf_log_date[8]; /* MMDDYYYY */
/* 9*/ u_int8_t compile_date[8]; /* MMDDYYYY */
/*17*/ u_int8_t spindown_count[2];
/*19*/ u_int8_t spindown_time[6]; /* HHMMSS */
} __packed;
#define SINQ_VPD_SERIAL 0x80
struct scsipi_inquiry_evpd_serial {
/* 1*/ u_int8_t serial_number[251];
} __packed;
#define SINQ_VPD_DEVICE_ID 0x83
struct scsipi_inquiry_evpd_device_id {
/* 1*/ u_int8_t pc;
#define SINQ_DEVICE_ID_PROTOCOL 0xf0
#define SINQ_DEVICE_ID_PROTOCOL_FC 0x00
#define SINQ_DEVICE_ID_PROTOCOL_SSA 0x20
#define SINQ_DEVICE_ID_PROTOCOL_IEEE1394 0x30
#define SINQ_DEVICE_ID_PROTOCOL_RDMA 0x40
#define SINQ_DEVICE_ID_PROTOCOL_ISCSI 0x50
#define SINQ_DEVICE_ID_PROTOCOL_SAS 0x60
#define SINQ_DEVICE_ID_CODESET 0x0f
#define SINQ_DEVICE_ID_CODESET_BINARY 0x01
#define SINQ_DEVICE_ID_CODESET_ASCII 0x02
#define SINQ_DEVICE_ID_CODESET_UTF8 0x03
/* 2*/ u_int8_t flags;
#define SINQ_DEVICE_ID_PIV 0x80
#define SINQ_DEVICE_ID_ASSOCIATION 0x30
#define SINQ_DEVICE_ID_ASSOCIATION_DEVICE 0x00
#define SINQ_DEVICE_ID_ASSOCIATION_PORT 0x10
#define SINQ_DEVICE_ID_ASSOCIATION_TARGET 0x20
#define SINQ_DEVICE_ID_TYPE 0x0f
#define SINQ_DEVICE_ID_TYPE_UNASSIGNED 0x00
#define SINQ_DEVICE_ID_TYPE_VENDOR 0x01
#define SINQ_DEVICE_ID_TYPE_EUI64 0x02
#define SINQ_DEVICE_ID_TYPE_FC 0x03
#define SINQ_DEVICE_ID_TYPE_PORTNUMBER1 0x04
#define SINQ_DEVICE_ID_TYPE_PORTNUMBER2 0x05
#define SINQ_DEVICE_ID_TYPE_PORTNUMBER3 0x06
#define SINQ_DEVICE_ID_TYPE_MD5 0x07
/* 3*/ u_int8_t reserved;
/* 4*/ u_int8_t designator_length;
/* 5*/ u_int8_t designator[1];
} __packed;
#endif /* _DEV_SCSIPI_SCSIPI_ALL_H_ */
lib/libc/include/generic-netbsd/dev/scsipi/scsipiconf.h
Vendored
+3 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: scsipiconf.h,v 1.130 2019/03/28 10:44:29 kardel Exp $ */
/* $NetBSD: scsipiconf.h,v 1.133 2024/10/29 15:50:07 nat Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2004 The NetBSD Foundation, Inc.
@@ -504,6 +504,8 @@ struct scsipi_periph {
#define PQUIRK_NOREPSUPPOPC 0x01000000 /* does not grok
REPORT SUPPORTED OPCODES
to fetch device timeouts */
#define PQUIRK_NOREADDISCINFO 0x02000000 /* device doesn't do
READ_DISCINFO properly */
/*
* Error values an adapter driver may return
*/
lib/libc/include/generic-netbsd/dev/tc/sfbreg.h
Vendored
+3 -3
View File
@@ -1,4 +1,4 @@
/* $NetBSD: sfbreg.h,v 1.3 2000/12/19 01:25:46 perseant Exp $ */
/* $NetBSD: sfbreg.h,v 1.4 2025/02/03 22:30:15 andvar Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
@@ -29,7 +29,7 @@
/*
* Smart ("CXTurbo") Frame Buffer definitions, from:
* ``DEC 3000 300/400/500/600/700/800/900 AXP Models System Prgrammer's Manual''
* ``DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual''
* (DEC order number EK-D3SYS-PM), section 6.
*
* All definitions are in "dense" TURBOchannel space.
@@ -91,7 +91,7 @@
#define SFB_ASIC_VIDCLK 0x007c /* VIDCLK count (R/W) */
/*
* Same as above but in 32-bit units, and named like the corrseponding
* Same as above but in 32-bit units, and named like the corresponding
* TGA registers, for easy comparison.
*/
typedef u_int32_t sfb_reg_t;
lib/libc/include/generic-netbsd/dev/tc/sticio.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: sticio.h,v 1.6 2020/09/12 16:44:41 kamil Exp $ */
/* $NetBSD: sticio.h,v 1.7 2024/02/09 22:08:36 andvar Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -75,7 +75,7 @@ struct stic_xcomm {
#ifdef _KERNEL
/*
* stic_xmap: a description of the area returned by mapping the board.
* sxm_xcomm and sxm_buf are physically contigious and of variable size as a
* sxm_xcomm and sxm_buf are physically contiguous and of variable size as a
* whole; the combined size is learnt from stic_xinfo::sxi_buf_size.
*/
struct stic_xmap {
lib/libc/include/generic-netbsd/dev/usb/umcpmio_hid_reports.h
Vendored
+499
View File
@@ -0,0 +1,499 @@
/* $NetBSD: umcpmio_hid_reports.h,v 1.2 2025/03/17 18:24:08 riastradh Exp $ */
/*
* Copyright (c) 2024 Brad Spencer <brad@anduin.eldar.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UMCPMIO_HID_REPORTS_H_
#define _UMCPMIO_HID_REPORTS_H_
#include <sys/types.h>
/*
* It is nice that all HID reports want a 64 byte request and return a
* 64 byte response.
*/
#define MCP2221_REQ_BUFFER_SIZE 64
#define MCP2221_RES_BUFFER_SIZE 64
#define MCP2221_CMD_STATUS 0x10
#define MCP2221_CMD_I2C_FETCH_READ_DATA 0x40
#define MCP2221_CMD_SET_GPIO_CFG 0x50
#define MCP2221_CMD_GET_GPIO_CFG 0x51
#define MCP2221_CMD_SET_SRAM 0x60
#define MCP2221_CMD_GET_SRAM 0x61
#define MCP2221_I2C_WRITE_DATA 0x90
#define MCP2221_I2C_READ_DATA 0x91
#define MCP2221_I2C_WRITE_DATA_RS 0x92
#define MCP2221_I2C_READ_DATA_RS 0x93
#define MCP2221_I2C_WRITE_DATA_NS 0x94
#define MCP2221_CMD_GET_FLASH 0xb0
#define MCP2221_CMD_SET_FLASH 0xb1
#define MCP2221_CMD_SEND_FLASH_PASSWORD 0xb2
#define MCP2221_CMD_COMPLETE_OK 0x00
#define MCP2221_CMD_COMPLETE_NO_SUPPORT 0x02
#define MCP2221_CMD_COMPLETE_EPERM 0x03
#define MCP2221_I2C_DO_CANCEL 0x10
#define MCP2221_INTERNAL_CLOCK 12000000
#define MCP2221_DEFAULT_I2C_SPEED 100000
#define MCP2221_I2C_SET_SPEED 0x20
/* The request and response structures are, perhaps, over literal. */
struct mcp2221_status_req {
uint8_t cmd; /* MCP2221_CMD_STATUS */
uint8_t dontcare1;
uint8_t cancel_transfer;
uint8_t set_i2c_speed;
uint8_t i2c_clock_divider;
uint8_t dontcare2[59];
};
#define MCP2221_I2C_SPEED_SET 0x20
#define MCP2221_I2C_SPEED_BUSY 0x21
#define MCP2221_ENGINE_T1_MASK_NACK 0x40
struct mcp2221_status_res {
uint8_t cmd;
uint8_t completion;
uint8_t cancel_transfer;
uint8_t set_i2c_speed;
uint8_t i2c_clock_divider;
uint8_t dontcare2[3];
uint8_t internal_i2c_state;
uint8_t lsb_i2c_req_len;
uint8_t msb_i2c_req_len;
uint8_t lsb_i2c_trans_len;
uint8_t msb_i2c_trans_len;
uint8_t internal_i2c_bcount;
uint8_t i2c_speed_divider;
uint8_t i2c_timeout_value;
uint8_t lsb_i2c_address;
uint8_t msb_i2c_address;
uint8_t dontcare3a[2];
uint8_t internal_i2c_state20;
uint8_t dontcare3b;
uint8_t scl_line_value;
uint8_t sda_line_value;
uint8_t interrupt_edge_state;
uint8_t i2c_read_pending;
uint8_t dontcare4[20];
uint8_t mcp2221_hardware_rev_major;
uint8_t mcp2221_hardware_rev_minor;
uint8_t mcp2221_firmware_rev_major;
uint8_t mcp2221_firmware_rev_minor;
uint8_t adc_channel0_lsb;
uint8_t adc_channel0_msb;
uint8_t adc_channel1_lsb;
uint8_t adc_channel1_msb;
uint8_t adc_channel2_lsb;
uint8_t adc_channel2_msb;
uint8_t dontcare5[8];
};
#define MCP2221_GPIO_CFG_ALTER 0xff
struct mcp2221_set_gpio_cfg_req {
uint8_t cmd; /* MCP2221_CMD_SET_GPIO_CFG */
uint8_t dontcare1;
uint8_t alter_gp0_value;
uint8_t new_gp0_value;
uint8_t alter_gp0_dir;
uint8_t new_gp0_dir;
uint8_t alter_gp1_value;
uint8_t new_gp1_value;
uint8_t alter_gp1_dir;
uint8_t new_gp1_dir;
uint8_t alter_gp2_value;
uint8_t new_gp2_value;
uint8_t alter_gp2_dir;
uint8_t new_gp2_dir;
uint8_t alter_gp3_value;
uint8_t new_gp3_value;
uint8_t alter_gp3_dir;
uint8_t new_gp3_dir;
uint8_t reserved[46];
};
struct mcp2221_set_gpio_cfg_res {
uint8_t cmd;
uint8_t completion;
uint8_t alter_gp0_value;
uint8_t new_gp0_value;
uint8_t alter_gp0_dir;
uint8_t new_gp0_dir;
uint8_t alter_gp1_value;
uint8_t new_gp1_value;
uint8_t alter_gp1_dir;
uint8_t new_gp1_dir;
uint8_t alter_gp2_value;
uint8_t new_gp2_value;
uint8_t alter_gp2_dir;
uint8_t new_gp2_dir;
uint8_t alter_gp3_value;
uint8_t new_gp3_value;
uint8_t alter_gp3_dir;
uint8_t new_gp3_dir;
uint8_t dontcare[46];
};
struct mcp2221_get_gpio_cfg_req {
uint8_t cmd; /* MCP2221_CMD_GET_GPIO_CFG */
uint8_t dontcare[63];
};
#define MCP2221_GPIO_CFG_VALUE_NOT_GPIO 0xEE
#define MCP2221_GPIO_CFG_DIR_NOT_GPIO 0xEF
#define MCP2221_GPIO_CFG_DIR_INPUT 0x01
#define MCP2221_GPIO_CFG_DIR_OUTPUT 0x00
struct mcp2221_get_gpio_cfg_res {
uint8_t cmd;
uint8_t completion;
uint8_t gp0_pin_value;
uint8_t gp0_pin_dir;
uint8_t gp1_pin_value;
uint8_t gp1_pin_dir;
uint8_t gp2_pin_value;
uint8_t gp2_pin_dir;
uint8_t gp3_pin_value;
uint8_t gp3_pin_dir;
uint8_t dontcare[54];
};
#define MCP2221_SRAM_GPIO_CHANGE_DCCD 0x80
#define MCP2221_SRAM_GPIO_CLOCK_DC_MASK 0x18
#define MCP2221_SRAM_GPIO_CLOCK_DC_75 0x18
#define MCP2221_SRAM_GPIO_CLOCK_DC_50 0x10
#define MCP2221_SRAM_GPIO_CLOCK_DC_25 0x08
#define MCP2221_SRAM_GPIO_CLOCK_DC_0 0x00
#define MCP2221_SRAM_GPIO_CLOCK_CD_MASK 0x07
#define MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ 0x07
#define MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ 0x06
#define MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ 0x05
#define MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ 0x04
#define MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ 0x03
#define MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ 0x02
#define MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ 0x01
#define MCP2221_SRAM_CHANGE_DAC_VREF 0x80
#define MCP2221_SRAM_DAC_IS_VRM 0x20
#define MCP2221_SRAM_DAC_VRM_MASK 0xC0
#define MCP2221_SRAM_DAC_VRM_4096V 0xC0
#define MCP2221_SRAM_DAC_VRM_2048V 0x80
#define MCP2221_SRAM_DAC_VRM_1024V 0x40
#define MCP2221_SRAM_DAC_VRM_OFF 0x00
#define MCP2221_SRAM_CHANGE_DAC_VALUE 0x80
#define MCP2221_SRAM_DAC_VALUE_MASK 0x1F
#define MCP2221_SRAM_CHANGE_ADC_VREF 0x80
#define MCP2221_SRAM_ADC_IS_VRM 0x04
#define MCP2221_SRAM_ADC_VRM_MASK 0x18
#define MCP2221_SRAM_ADC_VRM_4096V 0x18
#define MCP2221_SRAM_ADC_VRM_2048V 0x10
#define MCP2221_SRAM_ADC_VRM_1024V 0x08
#define MCP2221_SRAM_ADC_VRM_OFF 0x00
#define MCP2221_SRAM_ALTER_IRQ 0x80
#define MCP2221_SRAM_ALTER_POS_EDGE 0x10
#define MCP2221_SRAM_ENABLE_POS_EDGE 0x08
#define MCP2221_SRAM_ALTER_NEG_EDGE 0x04
#define MCP2221_SRAM_ENABLE_NEG_EDGE 0x02
#define MCP2221_SRAM_CLEAR_IRQ 0x01
#define MCP2221_SRAM_ALTER_GPIO 0xff
#define MCP2221_SRAM_GPIO_HIGH 0x0f
#define MCP2221_SRAM_GPIO_OUTPUT_HIGH 0x10
#define MCP2221_SRAM_GPIO_TYPE_MASK 0x08
#define MCP2221_SRAM_GPIO_INPUT 0x08
#define MCP2221_SRAM_PIN_TYPE_MASK 0x07
#define MCP2221_SRAM_PIN_IS_GPIO 0x00
#define MCP2221_SRAM_PIN_IS_DED 0x01
#define MCP2221_SRAM_PIN_IS_ALT0 0x02
#define MCP2221_SRAM_PIN_IS_ALT1 0x03
#define MCP2221_SRAM_PIN_IS_ALT2 0x04
struct mcp2221_set_sram_req {
uint8_t cmd; /* MCP2221_CMD_SET_SRAM */
uint8_t dontcare1;
uint8_t clock_output_divider;
uint8_t dac_voltage_reference;
uint8_t set_dac_output_value;
uint8_t adc_voltage_reference;
uint8_t irq_config;
uint8_t alter_gpio_config;
uint8_t gp0_settings;
uint8_t gp1_settings;
uint8_t gp2_settings;
uint8_t gp3_settings;
uint8_t reserved[52];
};
struct mcp2221_set_sram_res {
uint8_t cmd;
uint8_t completion;
uint8_t dontcare[62];
};
struct mcp2221_get_sram_req {
uint8_t cmd; /* MCP2221_CMD_GET_SRAM */
uint8_t dontcare[63];
};
struct mcp2221_get_sram_res {
uint8_t cmd;
uint8_t completion;
uint8_t len_chip_setting;
uint8_t len_gpio_setting;
uint8_t sn_initial_ps_cs;
uint8_t clock_divider;
uint8_t dac_reference_voltage;
uint8_t irq_adc_reference_voltage;
uint8_t lsb_usb_vid;
uint8_t msb_usb_vid;
uint8_t lsb_usb_pid;
uint8_t msb_usb_pid;
uint8_t usb_power_attributes;
uint8_t usb_requested_ma;
uint8_t current_password_byte_1;
uint8_t current_password_byte_2;
uint8_t current_password_byte_3;
uint8_t current_password_byte_4;
uint8_t current_password_byte_5;
uint8_t current_password_byte_6;
uint8_t current_password_byte_7;
uint8_t current_password_byte_8;
uint8_t gp0_settings;
uint8_t gp1_settings;
uint8_t gp2_settings;
uint8_t gp3_settings;
uint8_t dontcare[38];
};
#define MCP2221_I2C_ENGINE_BUSY 0x01
#define MCP2221_ENGINE_STARTTIMEOUT 0x12
#define MCP2221_ENGINE_REPSTARTTIMEOUT 0x17
#define MCP2221_ENGINE_STOPTIMEOUT 0x62
#define MCP2221_ENGINE_ADDRSEND 0x21
#define MCP2221_ENGINE_ADDRTIMEOUT 0x23
#define MCP2221_ENGINE_PARTIALDATA 0x41
#define MCP2221_ENGINE_READMORE 0x43
#define MCP2221_ENGINE_WRITETIMEOUT 0x44
#define MCP2221_ENGINE_READTIMEOUT 0x52
#define MCP2221_ENGINE_READPARTIAL 0x54
#define MCP2221_ENGINE_READCOMPLETE 0x55
#define MCP2221_ENGINE_ADDRNACK 0x25
#define MCP2221_ENGINE_WRITINGNOSTOP 0x45
struct mcp2221_i2c_req {
uint8_t cmd; /* MCP2221_I2C_WRITE_DATA
* MCP2221_I2C_READ_DATA
* MCP2221_I2C_WRITE_DATA_RS
* MCP2221_I2C_READ_DATA_RS
* MCP2221_I2C_WRITE_DATA_NS
*/
uint8_t lsblen;
uint8_t msblen;
uint8_t slaveaddr;
uint8_t data[60];
};
struct mcp2221_i2c_res {
uint8_t cmd;
uint8_t completion;
uint8_t internal_i2c_state;
uint8_t dontcare[61];
};
#define MCP2221_FETCH_READ_PARTIALDATA 0x41
#define MCP2221_FETCH_READERROR 0x7F
struct mcp2221_i2c_fetch_req {
uint8_t cmd; /* MCP2221_CMD_I2C_FETCH_READ_DATA */
uint8_t dontcare[63];
};
struct mcp2221_i2c_fetch_res {
uint8_t cmd;
uint8_t completion;
uint8_t internal_i2c_state;
uint8_t fetchlen;
uint8_t data[60];
};
#define MCP2221_FLASH_SUBCODE_CS 0x00
#define MCP2221_FLASH_SUBCODE_GP 0x01
#define MCP2221_FLASH_SUBCODE_USBMAN 0x02
#define MCP2221_FLASH_SUBCODE_USBPROD 0x03
#define MCP2221_FLASH_SUBCODE_USBSN 0x04
#define MCP2221_FLASH_SUBCODE_CHIPSN 0x05
struct mcp2221_get_flash_req {
uint8_t cmd; /* MCP2221_CMD_GET_FLASH */
uint8_t subcode;
uint8_t reserved[62];
};
struct mcp2221_get_flash_res {
uint8_t cmd;
uint8_t completion;
uint8_t res_len;
union {
struct {
uint8_t dontcare;
uint8_t uartenum_led_protection;
uint8_t clock_divider;
uint8_t dac_reference_voltage;
uint8_t irq_adc_reference_voltage;
uint8_t lsb_usb_vid;
uint8_t msb_usb_vid;
uint8_t lsb_usb_pid;
uint8_t msb_usb_pid;
uint8_t usb_power_attributes;
uint8_t usb_requested_ma;
uint8_t dontcare2[50];
} cs;
struct {
uint8_t dontcare;
uint8_t gp0_settings;
uint8_t gp1_settings;
uint8_t gp2_settings;
uint8_t gp3_settings;
uint8_t dontcare2[56];
} gp;
struct {
uint8_t always0x03;
uint8_t unicode_man_descriptor[60];
} usbman;
struct {
uint8_t always0x03;
uint8_t unicode_product_descriptor[60];
} usbprod;
struct usbsn {
uint8_t always0x03;
uint8_t unicode_serial_number[60];
} usbsn;
struct {
uint8_t dontcare;
uint8_t factory_serial_number[60];
} chipsn;
} u;
};
#define MCP2221_FLASH_GPIO_HIGH 0x0f
#define MCP2221_FLASH_GPIO_VALUE_MASK 0x10
#define MCP2221_FLASH_GPIO_TYPE_MASK 0x08
#define MCP2221_FLASH_GPIO_INPUT 0x08
#define MCP2221_FLASH_PIN_TYPE_MASK 0x07
#define MCP2221_FLASH_PIN_IS_GPIO 0x00
#define MCP2221_FLASH_PIN_IS_DED 0x01
#define MCP2221_FLASH_PIN_IS_ALT0 0x02
#define MCP2221_FLASH_PIN_IS_ALT1 0x03
#define MCP2221_FLASH_PIN_IS_ALT2 0x04
struct mcp2221_put_flash_req {
uint8_t cmd; /* MCP2221_CMD_SET_FLASH */
uint8_t subcode;
union {
struct {
uint8_t uartenum_led_protection;
uint8_t clock_divider;
uint8_t dac_reference_voltage;
uint8_t irq_adc_reference_voltage;
uint8_t lsb_usb_vid;
uint8_t msb_usb_vid;
uint8_t lsb_usb_pid;
uint8_t msb_usb_pid;
uint8_t usb_power_attributes;
uint8_t usb_requested_ma;
uint8_t password_byte_1;
uint8_t password_byte_2;
uint8_t password_byte_3;
uint8_t password_byte_4;
uint8_t password_byte_5;
uint8_t password_byte_6;
uint8_t password_byte_7;
uint8_t password_byte_8;
uint8_t dontcare[44];
} cs;
struct {
uint8_t gp0_settings;
uint8_t gp1_settings;
uint8_t gp2_settings;
uint8_t gp3_settings;
uint8_t dontcare[58];
} gp;
struct {
uint8_t len;
uint8_t always0x03;
uint8_t unicode_man_descriptor[60];
} usbman;
struct {
uint8_t len;
uint8_t always0x03;
uint8_t unicode_product_descriptor[60];
} usbprod;
struct {
uint8_t len;
uint8_t always0x03;
uint8_t unicode_serial_number[60];
} usbsn;
} u;
};
struct mcp2221_put_flash_res {
uint8_t cmd;
uint8_t completion;
uint8_t dontcare[62];
};
/* XXX - missing is the submit password call to unlock the chip */
#endif /* _UMCPMIO_HID_REPORTS_H_ */
lib/libc/include/generic-netbsd/dev/usb/umcpmio_io.h
Vendored
+45
View File
@@ -0,0 +1,45 @@
/* $NetBSD: umcpmio_io.h,v 1.2 2025/03/17 18:24:08 riastradh Exp $ */
/*
* Copyright (c) 2024 Brad Spencer <brad@anduin.eldar.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UMCPMIO_IO_H_
#define _UMCPMIO_IO_H_
#include <sys/types.h>
#include <sys/ioccom.h>
#include <dev/usb/umcpmio_hid_reports.h>
struct umcpmio_ioctl_get_flash {
uint8_t subcode;
struct mcp2221_get_flash_res get_flash_res;
};
struct umcpmio_ioctl_put_flash {
uint8_t subcode;
struct mcp2221_put_flash_req put_flash_req;
struct mcp2221_put_flash_res put_flash_res;
};
#define UMCPMIO_GET_STATUS _IOR('m', 1, struct mcp2221_status_res)
#define UMCPMIO_GET_SRAM _IOR('m', 2, struct mcp2221_get_sram_res)
#define UMCPMIO_GET_GP_CFG _IOR('m', 3, struct mcp2221_get_gpio_cfg_res)
#define UMCPMIO_GET_FLASH _IOWR('m', 4, struct umcpmio_ioctl_get_flash)
#define UMCPMIO_PUT_FLASH _IOWR('m', 5, struct umcpmio_ioctl_put_flash)
#endif /* _UMCPMIO_IO_H_ */
lib/libc/include/generic-netbsd/dev/usb/usb.h
Vendored
+44 -6
View File
@@ -1,4 +1,4 @@
/* $NetBSD: usb.h,v 1.121.4.1 2024/02/03 11:47:07 martin Exp $ */
/* $NetBSD: usb.h,v 1.124.4.1 2026/02/02 19:58:44 martin Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -746,6 +746,38 @@ typedef struct {
#define UIPROTO_BLUETOOTH 0x01
#define UIPROTO_RNDIS 0x03
#define UICLASS_MISC 0xef
#define UISUBCLASS_MISC_SYNC 0x01
#define UIPROTO_MISC_SYNC_ACTIVE 0x01
#define UIPROTO_MISC_SYNC_PALM 0x02
#define UISUBCLASS_MISC_INTERFACE 0x02
#define UIPROTO_MISC_INTERFACE_ASSOC 0x01
#define UIPROTO_MISC_INTERFACE_WAMP 0x02
#define UISUBCLASS_MISC_CABLE 0x03
#define UIPROTO_MISC_CABLE_ASSOC 0x01
#define UISUBCLASS_MISC_RNDIS 0x04
#define UIPROTO_MISC_RNDIS_ETHERNET 0x01
#define UIPROTO_MISC_RNDIS_WIFI 0x02
#define UIPROTO_MISC_RNDIS_WIMAX 0x03
#define UIPROTO_MISC_RNDIS_WWAN 0x04
#define UIPROTO_MISC_RNDIS_RAW_IPV4 0x05
#define UIPROTO_MISC_RNDIS_RAW_IPV6 0x06
#define UIPROTO_MISC_RNDIS_GPRS 0x07
#define UISUBCLASS_MISC_VISION 0x05
#define UIPROTO_MISC_VISION_CONTROL 0x01
#define UIPROTO_MISC_VISION_EVENT 0x02
#define UIPROTO_MISC_VISION_STREAMING 0x03
#define UISUBCLASS_MISC_STEP 0x06
#define UIPROTO_MISC_STEP 0x01
#define UIPROTO_MISC_STEP_RAW 0x02
#define UISUBCLASS_MISC_DVB 0x07
#define UIPROTO_MISC_DVB_CMD 0x01
#define UIPROTO_MISC_DVB_MEDIA 0x02
#define UISUBCLASS_MISC_OCP_SECFIRMWARE 0x08
#define UIPROTO_MISC_MISC_OCP_SECFIRMWARE_RECOVERY 0x01
#define UISUBCLASS_MISC_OCP_OMBF 0x09
#define UIPROTO_MISC_MISC_OCP_OMBF_ICP 0x01
#define UICLASS_APPL_SPEC 0xfe
#define UISUBCLASS_FIRMWARE_DOWNLOAD 1
#define UISUBCLASS_IRDA 2
@@ -913,7 +945,7 @@ struct usb_device_info {
};
/* <=3.0 had this layout of the structure */
struct usb_device_info_old {
struct usb_device_info30 {
uint8_t udi_bus;
uint8_t udi_addr; /* device address */
usb_event_cookie_t udi_cookie;
@@ -973,14 +1005,14 @@ struct usb_event {
};
/* old <=3.0 compat event */
struct usb_event_old {
struct usb_event30 {
int ue_type;
struct timespec ue_time;
union {
struct {
int ue_bus;
} ue_ctrlr;
struct usb_device_info_old ue_device;
struct usb_device_info30 ue_device;
struct {
usb_event_cookie_t ue_cookie;
char ue_devname[16];
@@ -988,13 +1020,19 @@ struct usb_event_old {
} u;
};
#if 1 /* XXX: remove me, for the benefit of sanitizers */
#define usb_device_info_old usb_device_info30
#define usb_event_old usb_event30
#define USB_DEVICEINFO_OLD USB_DEVICEINFO_30
#define USB_GET_DEVICEINFO_OLD USB_GET_DEVICEINFO_30
#endif
/* USB controller */
#define USB_REQUEST _IOWR('U', 1, struct usb_ctl_request)
#define USB_SETDEBUG _IOW ('U', 2, int)
#define USB_DISCOVER _IO ('U', 3)
#define USB_DEVICEINFO _IOWR('U', 4, struct usb_device_info)
#define USB_DEVICEINFO_OLD _IOWR('U', 4, struct usb_device_info_old)
#define USB_DEVICEINFO_30 _IOWR('U', 4, struct usb_device_info30)
#define USB_DEVICESTATS _IOR ('U', 5, struct usb_device_stats)
/* Generic HID device */
@@ -1018,7 +1056,7 @@ struct usb_event_old {
#define USB_GET_STRING_DESC _IOWR('U', 110, struct usb_string_desc)
#define USB_DO_REQUEST _IOWR('U', 111, struct usb_ctl_request)
#define USB_GET_DEVICEINFO _IOR ('U', 112, struct usb_device_info)
#define USB_GET_DEVICEINFO_OLD _IOR ('U', 112, struct usb_device_info_old)
#define USB_GET_DEVICEINFO_30 _IOR ('U', 112, struct usb_device_info30)
#define USB_SET_SHORT_XFER _IOW ('U', 113, int)
#define USB_SET_TIMEOUT _IOW ('U', 114, int)
#define USB_SET_BULK_RA _IOW ('U', 115, int)
lib/libc/include/generic-netbsd/dev/vndvar.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: vndvar.h,v 1.38 2018/10/07 11:51:26 mlelstv Exp $ */
/* $NetBSD: vndvar.h,v 1.39 2025/02/13 01:33:21 gutteridge Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -169,7 +169,7 @@ struct vnd_user {
/*
* Before you can use a unit, it must be configured with VNDIOCSET.
* The configuration persists across opens and closes of the device;
* an VNDIOCCLR must be used to reset a configuration. An attempt to
* a VNDIOCCLR must be used to reset a configuration. An attempt to
* VNDIOCSET an already active unit will return EBUSY.
*/
#define VNDIOCSET _IOWR('F', 0, struct vnd_ioctl) /* enable disk */
lib/libc/include/generic-netbsd/dev/wscons/wsconsio.h
Vendored
+19 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: wsconsio.h,v 1.126.4.1 2024/02/03 11:47:06 martin Exp $ */
/* $NetBSD: wsconsio.h,v 1.130 2025/07/26 14:18:14 martin Exp $ */
/*
* Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
@@ -367,6 +367,8 @@ struct wsmouse_parameters {
#define WSDISPLAY_TYPE_PLFB 65 /* ARM PrimeCell PL11x */
#define WSDISPLAY_TYPE_SSDFB 66 /* ssdfb(4) */
#define WSDISPLAY_TYPE_HOLLYWOOD 67 /* Nintendo Wii "Hollywood" SoC */
#define WSDISPLAY_TYPE_VC6 68 /* Broadcom VideoCore 6 */
#define WSDISPLAY_TYPE_VIOGPU 69 /* VirtIO GPU */
/* Basic display information. Not applicable to all display types. */
struct wsdisplay_fbinfo {
@@ -729,4 +731,20 @@ struct wsdisplayio_fontinfo {
#define WSDISPLAYIO_LISTFONTS _IOWR('W', 107, struct wsdisplayio_fontinfo)
struct wsdisplay_getfont {
char *gf_name;
uint32_t gf_size;
uint32_t gf_actual;
};
/*
* return currently active font
*
* gf_name points to a buffer of gf_size bytes, the result may be truncated
* and NUL-terminated.
* gf_actual is set to the size of full name.
*/
#define WSDISPLAYIO_GFONT _IOWR('W', 108, struct wsdisplay_getfont)
#endif /* _DEV_WSCONS_WSCONSIO_H_ */
lib/libc/include/generic-netbsd/dev/wscons/wsksymdef.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: wsksymdef.h,v 1.77 2021/09/22 17:37:32 nia Exp $ */
/* $NetBSD: wsksymdef.h,v 1.78 2023/12/11 13:38:13 mlelstv Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -687,7 +687,7 @@ action(KB_UA, 0, 0x1200, "ua", , "Ukrainian")
/* Define all the KB_xx numeric values using above table */
#define KBF_ENUM(tag, tagf, value, cc, ccf, country) tag=value,
enum { KB_ENC_FUN(KBF_ENUM) KB_NEXT=0x1d00 };
enum { KB_ENC_FUN(KBF_ENUM) KB_NEXT=0x2200 };
/* Define list of KB_xxx and country codes for array initialisation */
#define KBF_ENCTAB(tag, tagf, value, cc, ccf, country) { tag, cc },
lib/libc/include/generic-netbsd/dirent.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: dirent.h,v 1.37.2.1 2022/12/28 18:00:15 martin Exp $ */
/* $NetBSD: dirent.h,v 1.38 2022/12/28 11:51:21 nia Exp $ */
/*-
* Copyright (c) 1989, 1993
lib/libc/include/generic-netbsd/dlfcn.h
Vendored
+4 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: dlfcn.h,v 1.25 2017/07/11 15:21:35 joerg Exp $ */
/* $NetBSD: dlfcn.h,v 1.26 2024/11/02 20:53:58 nia Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -59,8 +59,10 @@ void *_dlauxinfo(void) __pure;
void *dlopen(const char *, int);
int dlclose(void *);
void *dlsym(void * __restrict, const char * __restrict);
#if defined(_NETBSD_SOURCE)
#if (_POSIX_C_SOURCE - 0 >= 202405L) || defined(_NETBSD_SOURCE)
int dladdr(const void * __restrict, Dl_info * __restrict);
#endif
#if defined(_NETBSD_SOURCE)
int dlctl(void *, int, void *);
int dlinfo(void *, int, void *);
void *dlvsym(void * __restrict, const char * __restrict,
lib/libc/include/generic-netbsd/elf.h
Vendored
+32 -20
View File
@@ -1,4 +1,4 @@
/* $NetBSD: exec_elf.h,v 1.170 2022/06/08 10:12:42 rin Exp $ */
/* $NetBSD: exec_elf.h,v 1.177 2025/05/27 14:03:08 christos Exp $ */
/*-
* Copyright (c) 1994 The NetBSD Foundation, Inc.
@@ -216,7 +216,7 @@ typedef struct {
#define EM_68K 4 /* Motorola 68000 */
#define EM_88K 5 /* Motorola 88000 */
#define EM_486 6 /* Intel 80486 [old] */
#define EM_IAMCU 6 /* Intel MCU. */
#define EM_IAMCU EM_486 /* Intel MCU. */
#define EM_860 7 /* Intel 80860 */
#define EM_MIPS 8 /* MIPS I Architecture */
#define EM_S370 9 /* Amdahl UTS on System/370 */
@@ -292,6 +292,7 @@ typedef struct {
#define EM_OR1K 92 /* OpenRISC 32-bit embedded processor */
#define EM_OPENRISC EM_OR1K
#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */
#define EM_ARC_COMPACT EM_ARC_A5 /* ARC International ARCompact processor (old spelling/synonym: EM_ARC_A5) */
#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */
#define EM_TMM_GPP 96 /* Thompson Multimedia General Purpose Processor */
@@ -301,7 +302,7 @@ typedef struct {
#define EM_ST200 100 /* STMicroelectronics ST200 microcontroller */
#define EM_IP2K 101 /* Ubicom IP2xxx microcontroller family */
#define EM_MAX 102 /* MAX processor */
#define EM_CR 103 /* National Semiconductor CompactRISC micorprocessor */
#define EM_CR 103 /* National Semiconductor CompactRISC microprocessor */
#define EM_F2MC16 104 /* Fujitsu F2MC16 */
#define EM_MSP430 105 /* Texas Instruments MSP430 */
#define EM_BLACKFIN 106 /* Analog Devices Blackfin DSP */
@@ -362,6 +363,7 @@ typedef struct {
#define EM_AARCH64 183 /* AArch64 64-bit ARM microprocessor */
/* 184 - Reserved */
#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor family*/
#define EM_STM8 186 /* STMicroelectronics STM8 8-bit microcontroller */
#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
#define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */
#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft processor core */
@@ -515,7 +517,8 @@ typedef struct {
#define SHT_PREINIT_ARRAY 16 /* Pre-initialization function ptrs */
#define SHT_GROUP 17 /* Section group */
#define SHT_SYMTAB_SHNDX 18 /* Section indexes (see SHN_XINDEX) */
#define SHT_NUM 19
#define SHT_RELR 19 /* Relative relocation information */
#define SHT_NUM 20
#define SHT_LOOS 0x60000000 /* Operating system specific range */
#define SHT_GNU_INCREMENTAL_INPUTS 0x6fff4700 /* GNU incremental build data */
@@ -540,9 +543,9 @@ typedef struct {
#define SHT_LOPROC 0x70000000 /* Processor-specific range */
#define SHT_AMD64_UNWIND 0x70000001 /* unwind information */
#define SHT_ARM_EXIDX 0x70000001 /* exception index table */
#define SHT_ARM_PREEMPTMAP 0x70000002 /* BPABI DLL dynamic linking
#define SHT_ARM_PREEMPTMAP 0x70000002 /* BPABI DLL dynamic linking
* pre-emption map */
#define SHT_ARM_ATTRIBUTES 0x70000003 /* Object file compatibility
#define SHT_ARM_ATTRIBUTES 0x70000003 /* Object file compatibility
* attributes */
#define SHT_ARM_DEBUGOVERLAY 0x70000004 /* See DBGOVL for details */
#define SHT_ARM_OVERLAYSECTION 0x70000005
@@ -575,7 +578,7 @@ typedef struct {
*/
typedef struct {
Elf32_Word st_name; /* Symbol name (.strtab index) */
Elf32_Word st_value; /* value of symbol */
Elf32_Addr st_value; /* value of symbol */
Elf32_Word st_size; /* size of symbol */
Elf_Byte st_info; /* type / binding attrs */
Elf_Byte st_other; /* unused */
@@ -679,6 +682,9 @@ typedef struct {
#define ELF32_R_TYPE(info) ((info) & 0xff)
#define ELF32_R_INFO(sym, type) (((sym) << 8) + (unsigned char)(type))
/* Relative relocations (DT_RELR, SHT_RELR, .relr.dyn) */
typedef Elf32_Word Elf32_Relr;
typedef struct {
Elf64_Addr r_offset; /* where to do it */
Elf64_Xword r_info; /* index & type of relocation */
@@ -695,6 +701,9 @@ typedef struct {
#define ELF64_R_TYPE(info) ((info) & 0xffffffff)
#define ELF64_R_INFO(sym,type) (((sym) << 32) + (type))
/* Relative relocations (DT_RELR, SHT_RELR, .relr.dyn) */
typedef Elf64_Xword Elf64_Relr;
/*
* Move entries
*/
@@ -792,10 +801,14 @@ typedef struct {
#define DT_FINI_ARRAYSZ 28 /* Size, in bytes, of DT_FINI_ARRAY array*/
#define DT_RUNPATH 29 /* overrides DT_RPATH */
#define DT_FLAGS 30 /* Encodes ORIGIN, SYMBOLIC, TEXTREL, BIND_NOW, STATIC_TLS */
#define DT_ENCODING 31 /* ??? */
#define DT_ENCODING 32 /* In [32, DT_LOOS), only evens use d_ptr */
#define DT_PREINIT_ARRAY 32 /* Address of pre-init function array */
#define DT_PREINIT_ARRAYSZ 33 /* Size, in bytes, of DT_PREINIT_ARRAY array */
#define DT_NUM 34
#define DT_SYMTAB_SHNDX 34 /* Addr. of SHT_SYMTAB_SHNDX § of DT_SYMTAB */
#define DT_RELRSZ 35 /* Size, in bytes, of DT_RELR table */
#define DT_RELR 36 /* Address of Relr relocation table */
#define DT_RELRENT 37 /* Size, in bytes, of one DT_RELR entry */
#define DT_NUM 38
#define DT_LOOS 0x60000000 /* Operating system specific range */
#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table */
@@ -972,7 +985,7 @@ typedef struct {
* GNU-specific note type: Build ID generated by ld
* name: GNU\0
* desc:
* word[0..4] SHA1 [default]
* word[0..4] SHA1 [default]
* or
* word[0..3] md5 or uuid
* descsz: 16 or 20
@@ -999,7 +1012,7 @@ typedef struct {
/* SuSE-specific note type: version
* name: SuSE\0\0\0\0
* namesz: 8
* desc:
* desc:
* word[0] = VVTTMMmm
*
* V = version of following data
@@ -1018,7 +1031,7 @@ typedef struct {
/* Go-specific note type: buildid
* name: Go\0\0
* namesz: 4
* desc:
* desc:
* words[10]
* descsz: 40
*/
@@ -1043,7 +1056,7 @@ typedef struct {
/* NetBSD-specific note type: NetBSD ABI version.
* name: NetBSD\0\0
* namesz: 8
* desc:
* desc:
* word[0]: MMmmrrpp00
*
* M = major version
@@ -1064,7 +1077,7 @@ typedef struct {
* namesz: 8
* desc:
* "netbsd\0"
*
*
* descsz: 8
*/
#define ELF_NOTE_TYPE_NETBSD_EMUL_TAG 2
@@ -1179,7 +1192,6 @@ struct netbsd_elfcore_procinfo {
/* NetBSD-specific note name */
#define ELF_NOTE_MCMODEL_NAME ELF_NOTE_NETBSD_NAME
#if !defined(ELFSIZE)
# if defined(_RUMPKERNEL) || !defined(_KERNEL)
# define ELFSIZE ARCH_ELFSIZE
@@ -1204,6 +1216,7 @@ struct netbsd_elfcore_procinfo {
#define Elf_Sym Elf32_Sym
#define Elf_Rel Elf32_Rel
#define Elf_Rela Elf32_Rela
#define Elf_Relr Elf32_Relr
#define Elf_Dyn Elf32_Dyn
#define Elf_Word Elf32_Word
#define Elf_Sword Elf32_Sword
@@ -1230,6 +1243,7 @@ struct netbsd_elfcore_procinfo {
#define Elf_Sym Elf64_Sym
#define Elf_Rel Elf64_Rel
#define Elf_Rela Elf64_Rela
#define Elf_Relr Elf64_Relr
#define Elf_Dyn Elf64_Dyn
#define Elf_Word Elf64_Word
#define Elf_Sword Elf64_Sword
@@ -1299,7 +1313,7 @@ typedef struct {
#define SYMINFO_NUM 2
/*
* These constants are used for Elf32_Verdef struct's version number.
* These constants are used for Elf32_Verdef struct's version number.
*/
#define VER_DEF_NONE 0
#define VER_DEF_CURRENT 1
@@ -1310,7 +1324,7 @@ typedef struct {
#define VER_DEF_IDX(x) VER_NDX(x)
/*
* These constants are used for Elf32_Verdef struct's vd_flags.
* These constants are used for Elf32_Verdef struct's vd_flags.
*/
#define VER_FLG_BASE 0x1
#define VER_FLG_WEAK 0x2
@@ -1323,7 +1337,7 @@ typedef struct {
#define VER_NDX_GIVEN 2
/*
* These constants are used for Elf32_Verneed struct's version number.
* These constants are used for Elf32_Verneed struct's version number.
*/
#define VER_NEED_NONE 0
#define VER_NEED_CURRENT 1
@@ -1460,7 +1474,6 @@ int coredump_elf32(struct lwp *, struct coredump_iostate *);
void coredump_savenote_elf32(struct note_state *, unsigned int,
const char *, void *, size_t);
#ifdef EXEC_ELF64
int exec_elf64_makecmds(struct lwp *, struct exec_package *);
int elf64_populate_auxv(struct lwp *, struct exec_package *, char **);
@@ -1475,7 +1488,6 @@ int coredump_elf64(struct lwp *, struct coredump_iostate *);
void coredump_savenote_elf64(struct note_state *, unsigned int,
const char *, void *, size_t);
#endif /* _KERNEL */
#endif /* !_SYS_EXEC_ELF_H_ */
lib/libc/include/generic-netbsd/elfdefinitions.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: elfdefinitions.h,v 1.7 2021/04/29 17:38:08 jkoshy Exp $ */
/* $NetBSD: elfdefinitions.h,v 1.8 2024/03/03 17:37:29 christos Exp $ */
/*-
* Copyright (c) 2010,2021 Joseph Koshy
lib/libc/include/generic-netbsd/evbarm/intr.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: intr.h,v 1.28.20.1 2023/08/09 17:42:02 martin Exp $ */
/* $NetBSD: intr.h,v 1.29 2023/07/11 10:42:07 riastradh Exp $ */
/*
* Copyright (c) 2001, 2003 Wasabi Systems, Inc.
lib/libc/include/generic-netbsd/evbmips/lwp_private.h
Vendored
+3
View File
@@ -0,0 +1,3 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:08 christos Exp $ */
#include <mips/lwp_private.h>
lib/libc/include/generic-netbsd/execinfo.h
Vendored
+4 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: execinfo.h,v 1.3 2017/06/30 21:39:43 christos Exp $ */
/* $NetBSD: execinfo.h,v 1.5 2025/01/23 12:08:12 christos Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -34,13 +34,15 @@
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#include <sys/ansi.h>
#ifdef _BSD_SIZE_T_
typedef _BSD_SIZE_T_ size_t;
#undef _BSD_SIZE_T_
#endif
__BEGIN_DECLS
int backtrace_sandbox_init(void);
void backtrace_sandbox_fini(void);
size_t backtrace(void **, size_t);
char **backtrace_symbols(void *const *, size_t);
int backtrace_symbols_fd(void *const *, size_t, int);
lib/libc/include/generic-netbsd/fcntl.h
Vendored
+26 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: fcntl.h,v 1.54 2020/03/30 20:17:42 kamil Exp $ */
/* $NetBSD: fcntl.h,v 1.57 2025/07/25 23:24:46 kre Exp $ */
/*-
* Copyright (c) 1983, 1990, 1993
@@ -123,6 +123,10 @@
#define O_REGULAR 0x02000000 /* fail if not a regular file */
#define O_EXEC 0x04000000 /* open for executing only */
#endif
#if (_POSIX_C_SOURCE - 0) >= 202405L || (_XOPEN_SOURCE - 0 >= 800) || \
defined(_NETBSD_SOURCE)
#define O_CLOFORK 0x08000000 /* set close on fork */
#endif
#ifdef _KERNEL
/* convert from open() flags to/from fflags; convert O_RD/WR to FREAD/FWRITE */
@@ -133,7 +137,8 @@
#define O_MASK (O_ACCMODE|O_NONBLOCK|O_APPEND|O_SHLOCK|O_EXLOCK|\
O_ASYNC|O_SYNC|O_CREAT|O_TRUNC|O_EXCL|O_DSYNC|\
O_RSYNC|O_NOCTTY|O_ALT_IO|O_NOFOLLOW|O_DIRECT|\
O_DIRECTORY|O_CLOEXEC|O_NOSIGPIPE|O_REGULAR|O_EXEC)
O_DIRECTORY|O_CLOEXEC|O_CLOFORK|O_NOSIGPIPE|\
O_REGULAR|O_EXEC)
#define FEXEC O_EXEC
#define FMARK 0x00001000 /* mark during gc() */
@@ -200,10 +205,20 @@
#define F_GETNOSIGPIPE 13 /* get SIGPIPE disposition */
#define F_SETNOSIGPIPE 14 /* set SIGPIPE disposition */
#define F_GETPATH 15 /* get pathname associated with fd */
#define F_ADD_SEALS 16 /* set seals */
#define F_GET_SEALS 17 /* get seals */
#endif
#if (_POSIX_C_SOURCE - 0) >= 202405L || (_XOPEN_SOURCE - 0 >= 800) || \
defined(_NETBSD_SOURCE)
#define F_DUPFD_CLOFORK 18 /* close on fork duplicated fd */
#endif
#if defined(_NETBSD_SOURCE)
#define F_DUPFD_CLOBOTH 19 /* close on exec/fork duplicated fd */
#endif
/* file descriptor flags (F_GETFD, F_SETFD) */
#define FD_CLOEXEC 1 /* close-on-exec flag */
#define FD_CLOFORK 2 /* close-on-fork flag */
/* record locking flags (F_GETLK, F_SETLK, F_SETLKW) */
#define F_RDLCK 1 /* shared or read lock */
@@ -215,6 +230,15 @@
#define F_POSIX 0x040 /* Use POSIX semantics for lock */
#endif
/* types of seals (F_ADD_SEALS, F_GET_SEALS) */
#if defined(_NETBSD_SOURCE)
#define F_SEAL_SEAL 0x0001 /* prevent further seals from being set */
#define F_SEAL_SHRINK 0x0002 /* prevent file from shrinking */
#define F_SEAL_GROW 0x0004 /* prevent file from growing */
#define F_SEAL_WRITE 0x0008 /* prevent writes */
#define F_SEAL_FUTURE_WRITE 0x0010 /* prevent future writes while mapped */
#endif
/* Constants for fcntl's passed to the underlying fs - like ioctl's. */
#if defined(_NETBSD_SOURCE)
#define F_PARAM_MASK 0xfff
lib/libc/include/generic-netbsd/float.h
Vendored
+58 -2
View File
@@ -1,3 +1,59 @@
/* $NetBSD: float.h,v 1.1 2002/12/09 12:16:02 scw Exp $ */
/* $NetBSD: float.h,v 1.2 2024/10/30 15:56:11 riastradh Exp $ */
#include <powerpc/float.h>
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RISCV_FLOAT_H_
#define _RISCV_FLOAT_H_
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#define LDBL_MANT_DIG __LDBL_MANT_DIG__
#define LDBL_DIG __LDBL_DIG__
#define LDBL_MIN_EXP __LDBL_MIN_EXP__
#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
#define LDBL_MAX_EXP __LDBL_MAX_EXP__
#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__
#define LDBL_EPSILON __LDBL_EPSILON__
#define LDBL_MIN __LDBL_MIN__
#define LDBL_MAX __LDBL_MAX__
#include <sys/float_ieee754.h>
#if (!defined(_ANSI_SOURCE) && !defined(_POSIX_C_SOURCE) \
&& !defined(_XOPEN_SOURCE)) \
|| (__STDC_VERSION__ - 0) >= 199901L \
|| (_POSIX_C_SOURCE - 0) >= 200112L \
|| ((_XOPEN_SOURCE - 0) >= 600) \
|| defined(_ISOC99_SOURCE) || defined(_NETBSD_SOURCE)
#define DECIMAL_DIG __DECIMAL_DIG__
#endif
#endif /* !_RISCV_FLOAT_H_ */
lib/libc/include/generic-netbsd/fmtmsg.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: fmtmsg.h,v 1.3 2008/04/28 20:22:54 martin Exp $ */
/* $NetBSD: fmtmsg.h,v 1.4 2023/12/08 21:46:02 andvar Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -58,7 +58,7 @@
#define MM_INFO 4 /* Informative message */
/* `Null' values for message components. */
#define MM_NULLMC 0L /* `Null' classsification component */
#define MM_NULLMC 0L /* `Null' classification component */
#define MM_NULLLBL (char *)0 /* `Null' label component */
#define MM_NULLSEV 0 /* `Null' severity component */
#define MM_NULLTXT (char *)0 /* `Null' text component */
lib/libc/include/generic-netbsd/fs/hfs/libhfs.h
Vendored
+1 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: libhfs.h,v 1.8.30.1 2023/07/31 15:47:20 martin Exp $ */
/* $NetBSD: libhfs.h,v 1.9 2023/03/01 16:21:14 riastradh Exp $ */
/*-
* Copyright (c) 2005, 2007 The NetBSD Foundation, Inc.
lib/libc/include/generic-netbsd/fs/nilfs/nilfs_fs.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: nilfs_fs.h,v 1.4 2022/02/16 22:00:56 andvar Exp $ */
/* $NetBSD: nilfs_fs.h,v 1.5 2024/12/26 21:16:26 andvar Exp $ */
/*
* Copyright (c) 2008, 2009 Reinoud Zandijk
@@ -436,7 +436,7 @@ struct nilfs_segment_summary {
#define NILFS_SS_GC 0x0010 /* segment written for cleaner operation */
#define NILFS_SS_FLAG_BITS "\20\1LOGBGN\2LOGEND\3SR\4SYNDT\5GC"
/* Segment summary constrains */
/* Segment summary constraints */
#define NILFS_SEG_MIN_BLOCKS 16 /* minimum number of blocks in a
full segment */
#define NILFS_PSEG_MIN_BLOCKS 2 /* minimum number of blocks in a
lib/libc/include/generic-netbsd/gelf.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: gelf.h,v 1.3 2016/02/20 02:43:42 christos Exp $ */
/* $NetBSD: gelf.h,v 1.4 2024/03/03 17:37:33 christos Exp $ */
/*-
* Copyright (c) 2006,2008 Joseph Koshy
@@ -25,7 +25,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Id: gelf.h 3174 2015-03-27 17:13:41Z emaste
* Id: gelf.h 3174 2015-03-27 17:13:41Z emaste
*/
#ifndef _GELF_H_
lib/libc/include/generic-netbsd/i386/asm.h
Vendored
+12 -4
View File
@@ -1,4 +1,4 @@
/* $NetBSD: asm.h,v 1.44 2020/04/25 15:26:17 bouyer Exp $ */
/* $NetBSD: asm.h,v 1.47 2025/01/05 16:53:26 riastradh Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -181,11 +181,19 @@
#define ASMSTR .asciz
#ifdef __ELF__
#define RCSID(x) .pushsection ".ident","MS",@progbits,1; \
.asciz x; \
#define _IDENTSTR(x) .pushsection ".ident","MS",@progbits,1; \
x; \
.popsection
#else
#define RCSID(x) .text; .asciz x
#define _IDENTSTR(x) .text; x
#endif
#ifdef _NETBSD_REVISIONID
#define RCSID(_s) \
_IDENTSTR(.asciz _s); \
_IDENTSTR(.ascii "$"; .ascii "NetBSD: "; .ascii __FILE__; .ascii " "; \
.ascii _NETBSD_REVISIONID; .asciz " $")
#else
#define RCSID(_s) _IDENTSTR(.asciz _s)
#endif
#ifdef NO_KERNEL_RCSIDS
lib/libc/include/generic-netbsd/i386/byte_swap.h
Vendored
+2 -2
View File
@@ -1,4 +1,4 @@
/* $NetBSD: byte_swap.h,v 1.17 2020/08/10 10:59:33 rin Exp $ */
/* $NetBSD: byte_swap.h,v 1.17.28.1 2025/12/18 19:57:53 martin Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#ifndef _I386_BYTE_SWAP_H_
#define _I386_BYTE_SWAP_H_
#include <sys/types.h>
#include <sys/stdint.h>
#ifdef __GNUC__
__BEGIN_DECLS
lib/libc/include/generic-netbsd/i386/cpu.h
Vendored
+15 -4
View File
@@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.183 2021/11/02 11:26:04 ryo Exp $ */
/* $NetBSD: cpu.h,v 1.185 2023/09/04 20:58:52 mrg Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -45,12 +45,20 @@
static struct cpu_info *x86_curcpu(void);
static lwp_t *x86_curlwp(void);
/*
* XXXGCC12 has:
* ./machine/cpu.h:57:9: error: array subscript 0 is outside array bounds of 'struct cpu_info * const[0]' [-Werror=array-bounds]
* 56 | __asm("movq %%gs:%1, %0" :
*/
#pragma GCC push_options
#pragma GCC diagnostic ignored "-Warray-bounds"
__inline __always_inline static struct cpu_info * __unused
x86_curcpu(void)
{
struct cpu_info *ci;
__asm volatile("movl %%fs:%1, %0" :
__asm("movl %%fs:%1, %0" :
"=r" (ci) :
"m"
(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self)));
@@ -62,13 +70,16 @@ x86_curlwp(void)
{
lwp_t *l;
__asm volatile("movl %%fs:%1, %0" :
__asm("movl %%fs:%1, %0" :
"=r" (l) :
"m"
(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp)));
return l;
}
#endif
#pragma GCC pop_options
#endif /* __GNUC__ && !_MODULE */
#ifdef XENPV
#define CLKF_USERMODE(frame) (curcpu()->ci_xen_clockf_usermode)
lib/libc/include/generic-netbsd/i386/elf_machdep.h
Vendored
+2 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: elf_machdep.h,v 1.13 2017/11/06 03:47:46 christos Exp $ */
/* $NetBSD: elf_machdep.h,v 1.14 2025/02/11 12:27:58 jkoshy Exp $ */
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
#define ELF32_MACHDEP_ID_CASES \
@@ -24,6 +24,7 @@
#define R_386_COPY 5
#define R_386_GLOB_DAT 6
#define R_386_JMP_SLOT 7
#define R_386_JUMP_SLOT 7 /* psABI spelling. */
#define R_386_RELATIVE 8
#define R_386_GOTOFF 9
#define R_386_GOTPC 10
lib/libc/include/generic-netbsd/i386/lwp_private.h
Vendored
+3
View File
@@ -0,0 +1,3 @@
/* $NetBSD: lwp_private.h,v 1.1 2024/11/30 01:04:10 christos Exp $ */
#include <x86/lwp_private.h>
lib/libc/include/generic-netbsd/i386/mcontext.h
Vendored
+6 -24
View File
@@ -1,4 +1,4 @@
/* $NetBSD: mcontext.h,v 1.15 2019/12/27 00:32:17 kamil Exp $ */
/* $NetBSD: mcontext.h,v 1.19 2024/11/30 01:04:10 christos Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -36,10 +36,10 @@
/*
* mcontext extensions to handle signal delivery.
*/
#define _UC_SETSTACK 0x00010000
#define _UC_CLRSTACK 0x00020000
#define _UC_VM 0x00040000
#define _UC_TLSBASE 0x00080000
#define _UC_SETSTACK _UC_MD_BIT16
#define _UC_CLRSTACK _UC_MD_BIT17
#define _UC_VM _UC_MD_BIT18
#define _UC_TLSBASE _UC_MD_BIT19
/*
* Layout of mcontext_t according to the System V Application Binary Interface,
@@ -96,7 +96,7 @@ typedef struct {
__greg_t _mc_tlsbase;
} mcontext_t;
#define _UC_FXSAVE 0x20 /* FP state is in FXSAVE format in XMM space */
#define _UC_FXSAVE _UC_MD_BIT5 /* FP state is in FXSAVE format in XMM space */
#define _UC_MACHINE_PAD 4 /* Padding appended to ucontext_t */
@@ -113,22 +113,4 @@ typedef struct {
#define __UCONTEXT_SIZE 776
#if defined(_RTLD_SOURCE) || defined(_LIBC_SOURCE) || \
defined(__LIBPTHREAD_SOURCE__)
#include <sys/tls.h>
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
void *__tmp;
__asm volatile("movl %%gs:0, %0" : "=r" (__tmp));
return __tmp;
}
__END_DECLS
#endif
#endif /* !_I386_MCONTEXT_H_ */
lib/libc/include/generic-netbsd/i386/param.h
Vendored
+9 -1
View File
@@ -1,4 +1,4 @@
/* $NetBSD: param.h,v 1.88 2021/05/31 14:38:55 simonb Exp $ */
/* $NetBSD: param.h,v 1.89 2025/04/20 22:33:13 riastradh Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -65,6 +65,14 @@
#define ALIGNED_POINTER(p,t) 1
#define ALIGNED_POINTER_LOAD(q,p,t) memcpy((q), (p), sizeof(t))
/*
* Stack alignment is 4-byte, following the traditional i386 SysV ABI
* published by SCO. Note: Parts of the Linux world have altered the
* ABI to guarantee 16-byte alignment, which is convenient for SSE2,
* but an incompatible ABI change which we do not follow.
*/
#define STACK_ALIGNBYTES (4 - 1)
#define PGSHIFT 12 /* LOG2(NBPG) */
#define NBPG (1 << PGSHIFT) /* bytes/page */
#define PGOFSET (NBPG-1) /* byte offset into page */

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