许杰友 Jieyou Xu (Joe)
ab4588a619
Fix target_feature handling in freg of LoongArch inline assembly In LoongArch inline assembly, freg currently always accepts f32/f64 as input/output. https://github.com/rust-lang/rust/blob/9b4d7c6a40b328d212095c28670c629facf1557d/compiler/rustc_target/src/asm/loongarch.rs#L41 However, these types actually require f/d target features as in RISC-V. Otherwise, an (ugly) compile error will occur: https://godbolt.org/z/K61Gq1E9E f32/f64 without f: ``` error: couldn't allocate output register for constraint '{$f1}' --> <source>:12:11 | 12 | asm!("", in("$f1") x, lateout("$f1") y); | ^ ``` f64 with f but without d: ``` error: scalar-to-vector conversion failed, possible invalid constraint for vector type --> <source>:19:11 | 19 | asm!("", in("$f1") x, lateout("$f1") y); | ^ ``` cc ``@heiher`` r? ``@Amanieu`` ``@rustbot`` label +O-LoongArch +A-inline-assembly
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