gwenn 90c0c9be20 Avx (#109) ...

* avx: _mm256_loadu_pd

* avx: _mm256_storeu_pd

* avx: _mm256_loadu_ps

* avx: _mm256_storeu_ps

* avx: fix _mm256_storeu_pd and _mm256_storeu_ps

* avx: _mm256_loadu_si256

* avx: _mm256_undefined_si256

* avx: _mm256_maskload_pd

* avx: _mm256_maskstore_pd

* Attempt to fix CI (#108)

Need to bring codegen units back to only one for now

* [x86] sse4.2 add docs for _SIDD_EQUAL_RANGES (#107)

- Add docs for the _SIDD_EQUAL_RANGES mode

* Add _MM_TRANSPOSE4_PS pseudo-macro. (#106)

This adds a strange macro, which I've replaced with a function, because it
seems there are not many better alternatives.

Also adds a test, and `#[allow(non_snake_case)]` to `#[simd_test]`.

* Fix i586 tests

* Implement bitwise SSE ops & _mm_cmp*_ss  (#103)

* Add _mm_{and,andnot,or,xor}_ps

* Add _mm_cmpeq_ss

* Add _mm_cmplt_ss

* Add _mm_cmple_ss

* Add _mm_cmpgt_ss

* Add _mm_cmpge_ss

* Add _mm_cmpneq_ss

* Add _mm_cmpnlt_ss

* Add _mm_cmpnle_ss

* Add _mm_cmpngt_ss

* Add _mm_cmpnge_ss

* Add _mm_cmpord_ss

* Add _mm_cmpunord_ss

* Fix _mm_{and,andnot,or,xor}_ps tests for i586

LLVM for i586 doesn't seem to generate `andps`, and instead generates 4
`and`s. Similar for the other operations.

* avx: _mm_maskload_pd

* avx: _mm_maskstore_pd

* avx: _mm256_maskload_ps

* avx: _mm256_maskstore_ps

* avx: _mm_maskload_ps, _mm_maskstore_ps

* avx: _mm256_movehdup_ps

* avx: _mm256_moveldup_ps

2017-10-14 10:12:57 -04:00

library/stdarch

Avx (#109)

2017-10-14 10:12:57 -04:00

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