Merge commit '70ae207ff5dcd67931c0e67cb62ebceec75a7436' into subtree-update_cg_gcc_2026-02-14

compiler/rustc_codegen_gcc/.cspell.json

@@ -18,6 +18,7 @@
     ],
     "ignorePaths": [
         "src/intrinsic/archs.rs",
+        "src/intrinsic/old_archs.rs",
         "src/intrinsic/llvm.rs"
     ],
     "ignoreRegExpList": [

compiler/rustc_codegen_gcc/.github/workflows/ci.yml

@@ -113,6 +113,10 @@ jobs:
         git config --global user.name "User"
         ./y.sh prepare
 
+    - name: Add more failing tests for GCC without 128-bit integers support
+      if: ${{ matrix.libgccjit_version.gcc == 'gcc-15-without-int128.deb' }}
+      run: cat tests/failing-ui-tests-without-128bit-integers.txt >> tests/failing-ui-tests.txt
+
     - name: Run tests
       run: |
         ./y.sh test --release --clean --build-sysroot ${{ matrix.commands }}

compiler/rustc_codegen_gcc/.github/workflows/m68k.yml

@@ -83,7 +83,7 @@ jobs:
       run: |
         ./y.sh prepare --only-libcore --cross
         ./y.sh build --sysroot --target-triple m68k-unknown-linux-gnu --target ${{ github.workspace }}/target_specs/m68k-unknown-linux-gnu.json
-        CG_RUSTFLAGS="-Clinker=m68k-unknown-linux-gnu-gcc" ./y.sh cargo build --manifest-path=./tests/hello-world/Cargo.toml --target ${{ github.workspace }}/target_specs/m68k-unknown-linux-gnu.json
+        CG_RUSTFLAGS="-Clinker=m68k-unknown-linux-gnu-gcc" ./y.sh cargo build -Zjson-target-spec --manifest-path=./tests/hello-world/Cargo.toml --target ${{ github.workspace }}/target_specs/m68k-unknown-linux-gnu.json
         ./y.sh clean all
 
     - name: Build

compiler/rustc_codegen_gcc/Cargo.lock

@@ -56,18 +56,18 @@ dependencies = [
 
 [[package]]
 name = "gccjit"
-version = "3.1.1"
+version = "3.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ff80f4d6d0749eab3a69122210b3a1fdd52edb6162781aadd7c4842e26983683"
+checksum = "26b73d18b642ce16378af78f89664841d7eeafa113682ff5d14573424eb0232a"
 dependencies = [
  "gccjit_sys",
 ]
 
 [[package]]
 name = "gccjit_sys"
-version = "1.1.2"
+version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4f81d901767ddba371a619fa9bba657066a4d3c5607ee69bbb557c1c5ba9bf85"
+checksum = "ee689456c013616942d5aef9a84d613cefcc3b335340d036f3650fc1a7459e15"
 dependencies = [
  "libc",
 ]

compiler/rustc_codegen_gcc/Cargo.toml

@@ -24,7 +24,7 @@ default = ["master"]
 [dependencies]
 object = { version = "0.37.0", default-features = false, features = ["std", "read"] }
 tempfile = "3.20"
-gccjit = { version = "3.1.1", features = ["dlopen"] }
+gccjit = { version = "3.3.0", features = ["dlopen"] }
 #gccjit = { git = "https://github.com/rust-lang/gccjit.rs", branch = "error-dlopen", features = ["dlopen"] }
 
 # Local copy.

compiler/rustc_codegen_gcc/Readme.md

@@ -45,12 +45,12 @@ The default configuration (see below in the [Quick start](#quick-start) section)
    ./y.sh test --release
    ```
 
-If don't need to test GCC patches you wrote in our GCC fork, then the default configuration should
+If you don't need to test GCC patches you wrote in our GCC fork, then the default configuration should
 be all you need. You can update the `rustc_codegen_gcc` without worrying about GCC.
 
 ### Building with your own GCC version
 
-If you wrote a patch for GCC and want to test it without this backend, you will need
+If you wrote a patch for GCC and want to test it with this backend, you will need
 to do a few more things.
 
 To build it (most of these instructions come from [here](https://gcc.gnu.org/onlinedocs/jit/internals/index.html), so don't hesitate to take a look there if you encounter an issue):
@@ -127,7 +127,7 @@ You have to run these commands, in the corresponding order:
 $ ./y.sh prepare
 $ ./y.sh build --sysroot
 ```
-To check if all is  working correctly, run:
+To check if all is working correctly, run:
 
  ```bash
 $ ./y.sh cargo build --manifest-path tests/hello-world/Cargo.toml

compiler/rustc_codegen_gcc/_typos.toml

@@ -6,4 +6,4 @@ seh = "seh"
 typ = "typ"
 
 [files]
-extend-exclude = ["src/intrinsic/archs.rs"]
+extend-exclude = ["src/intrinsic/archs.rs", "src/intrinsic/old_archs.rs"]

compiler/rustc_codegen_gcc/build_system/src/build.rs

@@ -141,6 +141,10 @@ pub fn build_sysroot(env: &HashMap<String, String>, config: &ConfigInfo) -> Resu
     }
 
     let mut args: Vec<&dyn AsRef<OsStr>> = vec![&"cargo", &"build", &"--target", &config.target];
+    if config.target.ends_with(".json") {
+        args.push(&"-Zjson-target-spec");
+    }
+
     for feature in &config.features {
         args.push(&"--features");
         args.push(feature);

compiler/rustc_codegen_gcc/build_system/src/test.rs

@@ -679,10 +679,10 @@ fn test_projects(env: &Env, args: &TestArg) -> Result<(), String> {
     create_dir(projects_path)?;
 
     let nb_parts = args.nb_parts.unwrap_or(0);
-    if nb_parts > 0 {
+    if let Some(count) = projects.len().checked_div(nb_parts) {
         // We increment the number of tests by one because if this is an odd number, we would skip
         // one test.
-        let count = projects.len() / nb_parts + 1;
+        let count = count + 1;
         let current_part = args.current_part.unwrap();
         let start = current_part * count;
         // We remove the projects we don't want to test.

compiler/rustc_codegen_gcc/doc/debugging.md

@@ -2,9 +2,9 @@
 
 ## How to debug GCC LTO
 
-Run do the command with `-v -save-temps` and then extract the `lto1` line from the output and run that under the debugger.
+Run the command with `-v -save-temps` and then extract the `lto1` line from the output and run that under the debugger.
 
-## How to debug stdarch tests that cannot be ran locally
+## How to debug stdarch tests that cannot be run locally
 
 First, run the tests normally:
 

compiler/rustc_codegen_gcc/doc/errors.md

@@ -15,7 +15,7 @@ That can be caused by the fact that you try to compile with `lto = "fat"`, but y
 
 ### ld: cannot find crtbegin.o
 
-When compiling an executable with libgccijt, if setting the `*LIBRARY_PATH` variables to the install directory, you will get the following errors:
+When compiling an executable with libgccjit, if setting the `*LIBRARY_PATH` variables to the install directory, you will get the following errors:
 
 ```
 ld: cannot find crtbegin.o: No such file or directory

compiler/rustc_codegen_gcc/doc/gimple.md

@@ -3,7 +3,7 @@
 You can see the full documentation about what GIMPLE is [here](https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html). In this document we will explain how to generate it.
 
 First, we'll copy the content from `gcc/gcc/testsuite/jit.dg/test-const-attribute.c` into a
-file named `local.c` and remove the content we're not interested into:
+file named `local.c` and remove the content we're not interested in:
 
 ```diff
 - /* { dg-do compile { target x86_64-*-* } } */

compiler/rustc_codegen_gcc/doc/tips.md

@@ -53,7 +53,7 @@ If you wish to build a custom sysroot, pass the path of your sysroot source to `
 
 ### How to use [mem-trace](https://github.com/antoyo/mem-trace)
 
-`rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't a chance to intercept the calls to `malloc`.
+`rustc` needs to be built without `jemalloc` so that `mem-trace` can overload `malloc` since `jemalloc` is linked statically, so a `LD_PRELOAD`-ed library won't have a chance to intercept the calls to `malloc`.
 
 ### How to generate GIMPLE
 

compiler/rustc_codegen_gcc/libgccjit.version

@@ -1 +1 @@
-0081ca6631abdfa02bf42bc85aaf507b8a0e6beb
+896045775f7c40fafe48c6e398f6c53bf6af889e

compiler/rustc_codegen_gcc/rust-toolchain

@@ -1,3 +1,3 @@
 [toolchain]
-channel = "nightly-2025-12-20"
+channel = "nightly-2026-02-14"
 components = ["rust-src", "rustc-dev", "llvm-tools-preview"]

compiler/rustc_codegen_gcc/src/asm.rs

@@ -575,9 +575,7 @@ fn codegen_inline_asm(
         }
         if dest.is_none() && options.contains(InlineAsmOptions::NORETURN) {
             let builtin_unreachable = self.context.get_builtin_function("__builtin_unreachable");
-            let builtin_unreachable: RValue<'gcc> =
-                unsafe { std::mem::transmute(builtin_unreachable) };
-            self.call(self.type_void(), None, None, builtin_unreachable, &[], None, None);
+            self.llbb().add_eval(None, self.context.new_call(None, builtin_unreachable, &[]));
         }
 
         // Write results to outputs.

compiler/rustc_codegen_gcc/src/builder.rs

@@ -1495,6 +1495,8 @@ fn extract_element(&mut self, vec: RValue<'gcc>, idx: RValue<'gcc>) -> RValue<'g
 
     #[cfg(not(feature = "master"))]
     fn extract_element(&mut self, vec: RValue<'gcc>, idx: RValue<'gcc>) -> RValue<'gcc> {
+        use crate::context::new_array_type;
+
         let vector_type = vec
             .get_type()
             .unqualified()
@@ -1503,7 +1505,7 @@ fn extract_element(&mut self, vec: RValue<'gcc>, idx: RValue<'gcc>) -> RValue<'g
         let element_type = vector_type.get_element_type();
         let vec_num_units = vector_type.get_num_units();
         let array_type =
-            self.context.new_array_type(self.location, element_type, vec_num_units as u64);
+            new_array_type(self.context, self.location, element_type, vec_num_units as u64);
         let array = self.context.new_bitcast(self.location, vec, array_type).to_rvalue();
         self.context.new_array_access(self.location, array, idx).to_rvalue()
     }
@@ -1871,32 +1873,31 @@ fn fptoint_sat(
         // On the other hand, f_max works even if int_ty::MAX is greater than float_ty::MAX. Because
         // we're rounding towards zero, we just get float_ty::MAX (which is always an integer).
         // This already happens today with u128::MAX = 2^128 - 1 > f32::MAX.
-        let int_max = |signed: bool, int_width: u64| -> u128 {
+        fn int_max(signed: bool, int_width: u64) -> u128 {
             let shift_amount = 128 - int_width;
             if signed { i128::MAX as u128 >> shift_amount } else { u128::MAX >> shift_amount }
-        };
-        let int_min = |signed: bool, int_width: u64| -> i128 {
+        }
+        fn int_min(signed: bool, int_width: u64) -> i128 {
             if signed { i128::MIN >> (128 - int_width) } else { 0 }
-        };
+        }
 
-        let compute_clamp_bounds_single = |signed: bool, int_width: u64| -> (u128, u128) {
+        // TODO: rewrite using a generic function with <F: Float>.
+        let compute_clamp_bounds_half = |signed: bool, int_width: u64| -> (u128, u128) {
             let rounded_min =
-                ieee::Single::from_i128_r(int_min(signed, int_width), Round::TowardZero);
-            assert_eq!(rounded_min.status, Status::OK);
+                ieee::Half::from_i128_r(int_min(signed, int_width), Round::TowardZero);
+            //assert_eq!(rounded_min.status, Status::OK);
             let rounded_max =
-                ieee::Single::from_u128_r(int_max(signed, int_width), Round::TowardZero);
+                ieee::Half::from_u128_r(int_max(signed, int_width), Round::TowardZero);
             assert!(rounded_max.value.is_finite());
             (rounded_min.value.to_bits(), rounded_max.value.to_bits())
         };
-        let compute_clamp_bounds_double = |signed: bool, int_width: u64| -> (u128, u128) {
-            let rounded_min =
-                ieee::Double::from_i128_r(int_min(signed, int_width), Round::TowardZero);
+        fn compute_clamp_bounds<F: Float>(signed: bool, int_width: u64) -> (u128, u128) {
+            let rounded_min = F::from_i128_r(int_min(signed, int_width), Round::TowardZero);
             assert_eq!(rounded_min.status, Status::OK);
-            let rounded_max =
-                ieee::Double::from_u128_r(int_max(signed, int_width), Round::TowardZero);
+            let rounded_max = F::from_u128_r(int_max(signed, int_width), Round::TowardZero);
             assert!(rounded_max.value.is_finite());
             (rounded_min.value.to_bits(), rounded_max.value.to_bits())
-        };
+        }
         // To implement saturation, we perform the following steps:
         //
         // 1. Cast val to an integer with fpto[su]i. This may result in undef.
@@ -1926,15 +1927,19 @@ fn fptoint_sat(
 
         let float_bits_to_llval = |bx: &mut Self, bits| {
             let bits_llval = match float_width {
+                16 => bx.cx().const_u16(bits as u16),
                 32 => bx.cx().const_u32(bits as u32),
                 64 => bx.cx().const_u64(bits as u64),
+                128 => bx.cx().const_u128(bits),
                 n => bug!("unsupported float width {}", n),
             };
             bx.bitcast(bits_llval, float_ty)
         };
         let (f_min, f_max) = match float_width {
-            32 => compute_clamp_bounds_single(signed, int_width),
-            64 => compute_clamp_bounds_double(signed, int_width),
+            16 => compute_clamp_bounds_half(signed, int_width),
+            32 => compute_clamp_bounds::<ieee::Single>(signed, int_width),
+            64 => compute_clamp_bounds::<ieee::Double>(signed, int_width),
+            128 => compute_clamp_bounds::<ieee::Quad>(signed, int_width),
             n => bug!("unsupported float width {}", n),
         };
         let f_min = float_bits_to_llval(self, f_min);

compiler/rustc_codegen_gcc/src/common.rs

@@ -8,7 +8,7 @@
 use rustc_middle::mir::interpret::{ConstAllocation, GlobalAlloc, PointerArithmetic, Scalar};
 use rustc_middle::ty::layout::LayoutOf;
 
-use crate::context::CodegenCx;
+use crate::context::{CodegenCx, new_array_type};
 use crate::type_of::LayoutGccExt;
 
 impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
@@ -20,6 +20,10 @@ pub fn const_bytes(&self, bytes: &[u8]) -> RValue<'gcc> {
         bytes_in_context(self, bytes)
     }
 
+    pub fn const_u16(&self, i: u16) -> RValue<'gcc> {
+        self.const_uint(self.type_u16(), i as u64)
+    }
+
     fn global_string(&self, string: &str) -> LValue<'gcc> {
         // TODO(antoyo): handle non-null-terminated strings.
         let string = self.context.new_string_literal(string);
@@ -55,7 +59,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
         0 => {
             let context = &cx.context;
             let byte_type = context.new_type::<u64>();
-            let typ = context.new_array_type(None, byte_type, bytes.len() as u64 / 8);
+            let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 8);
             let elements: Vec<_> = bytes
                 .chunks_exact(8)
                 .map(|arr| {
@@ -76,7 +80,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
         4 => {
             let context = &cx.context;
             let byte_type = context.new_type::<u32>();
-            let typ = context.new_array_type(None, byte_type, bytes.len() as u64 / 4);
+            let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 4);
             let elements: Vec<_> = bytes
                 .chunks_exact(4)
                 .map(|arr| {
@@ -95,7 +99,7 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
         _ => {
             let context = cx.context;
             let byte_type = context.new_type::<u8>();
-            let typ = context.new_array_type(None, byte_type, bytes.len() as u64);
+            let typ = new_array_type(context, None, byte_type, bytes.len() as u64);
             let elements: Vec<_> = bytes
                 .iter()
                 .map(|&byte| context.new_rvalue_from_int(byte_type, byte as i32))

compiler/rustc_codegen_gcc/src/context.rs

@@ -19,6 +19,8 @@
 };
 use rustc_middle::ty::{self, ExistentialTraitRef, Instance, Ty, TyCtxt};
 use rustc_session::Session;
+#[cfg(feature = "master")]
+use rustc_session::config::DebugInfo;
 use rustc_span::source_map::respan;
 use rustc_span::{DUMMY_SP, Span};
 use rustc_target::spec::{HasTargetSpec, HasX86AbiOpt, Target, TlsModel, X86Abi};
@@ -145,6 +147,11 @@ pub fn new(
         supports_f64_type: bool,
         supports_f128_type: bool,
     ) -> Self {
+        #[cfg(feature = "master")]
+        if tcx.sess.opts.debuginfo != DebugInfo::None {
+            context.set_filename(codegen_unit.name().as_str());
+        }
+
         let create_type = |ctype, rust_type| {
             let layout = tcx
                 .layout_of(ty::TypingEnv::fully_monomorphized().as_query_input(rust_type))
@@ -194,8 +201,8 @@ pub fn new(
 
             // TODO(antoyo): re-enable the alignment when libgccjit fixed the issue in
             // gcc_jit_context_new_array_constructor (it should not use reinterpret_cast).
-            let i128_type = context.new_array_type(None, i64_type, 2)/*.get_aligned(i128_align)*/;
-            let u128_type = context.new_array_type(None, u64_type, 2)/*.get_aligned(u128_align)*/;
+            let i128_type = new_array_type(context, None, i64_type, 2)/*.get_aligned(i128_align)*/;
+            let u128_type = new_array_type(context, None, u64_type, 2)/*.get_aligned(u128_align)*/;
             (i128_type, u128_type)
         };
 
@@ -601,3 +608,17 @@ fn to_gcc_tls_mode(tls_model: TlsModel) -> gccjit::TlsModel {
         TlsModel::Emulated => gccjit::TlsModel::GlobalDynamic,
     }
 }
+
+pub fn new_array_type<'gcc>(
+    context: &'gcc Context<'gcc>,
+    location: Option<Location<'gcc>>,
+    typ: Type<'gcc>,
+    size: u64,
+) -> Type<'gcc> {
+    #[cfg(feature = "master")]
+    {
+        context.new_array_type_u64(location, typ, size)
+    }
+    #[cfg(not(feature = "master"))]
+    context.new_array_type(location, typ, size)
+}

compiler/rustc_codegen_gcc/src/int.rs

@@ -942,7 +942,7 @@ pub fn gcc_uint_to_float_cast(
     fn float_to_int_cast(
         &self,
         signed: bool,
-        value: RValue<'gcc>,
+        mut value: RValue<'gcc>,
         dest_typ: Type<'gcc>,
     ) -> RValue<'gcc> {
         let value_type = value.get_type();
@@ -951,16 +951,22 @@ fn float_to_int_cast(
         }
 
         debug_assert!(dest_typ.dyncast_array().is_some());
+        let (dest_type, param_type) = match self.type_kind(value_type) {
+            TypeKind::Half => (Some(self.float_type), self.float_type),
+            _ => (None, value_type),
+        };
         let name_suffix = match self.type_kind(value_type) {
             // cSpell:disable
-            TypeKind::Float => "sfti",
+            // Since we will cast Half to a float, we use sfti for both.
+            TypeKind::Half | TypeKind::Float => "sfti",
             TypeKind::Double => "dfti",
+            TypeKind::FP128 => "tfti",
             // cSpell:enable
             kind => panic!("cannot cast a {:?} to non-native integer", kind),
         };
         let sign = if signed { "" } else { "uns" };
         let func_name = format!("__fix{}{}", sign, name_suffix);
-        let param = self.context.new_parameter(None, value_type, "n");
+        let param = self.context.new_parameter(None, param_type, "n");
         let func = self.context.new_function(
             None,
             FunctionType::Extern,
@@ -969,6 +975,9 @@ fn float_to_int_cast(
             func_name,
             false,
         );
+        if let Some(dest_type) = dest_type {
+            value = self.context.new_cast(None, value, dest_type);
+        }
         self.context.new_call(None, func, &[value])
     }
 

compiler/rustc_codegen_gcc/src/intrinsic/archs.rs

@@ -6,47 +6,13 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
         unimplemented!("***** unsupported LLVM intrinsic {}", full_name)
     };
     let Some((arch, name)) = name.split_once('.') else {
-        unimplemented!("***** unsupported LLVM intrinsic {}", name)
+        unimplemented!("***** unsupported LLVM intrinsic llvm.{}", name)
     };
+    let old_arch_res = old_archs(arch, name);
+    if let ArchCheckResult::Ok(res) = old_arch_res {
+        return res;
+    }
     match arch {
-        "AMDGPU" => {
-            #[expect(non_snake_case)]
-            fn AMDGPU(name: &str, full_name: &str) -> &'static str {
-                match name {
-                    // AMDGPU
-                    "div.fixup.f32" => "__builtin_amdgpu_div_fixup",
-                    "div.fixup.f64" => "__builtin_amdgpu_div_fixup",
-                    "div.fixup.v2f64" => "__builtin_amdgpu_div_fixup",
-                    "div.fixup.v4f32" => "__builtin_amdgpu_div_fixup",
-                    "div.fmas.f32" => "__builtin_amdgpu_div_fmas",
-                    "div.fmas.f64" => "__builtin_amdgpu_div_fmas",
-                    "div.fmas.v2f64" => "__builtin_amdgpu_div_fmas",
-                    "div.fmas.v4f32" => "__builtin_amdgpu_div_fmas",
-                    "ldexp.f32" => "__builtin_amdgpu_ldexp",
-                    "ldexp.f64" => "__builtin_amdgpu_ldexp",
-                    "ldexp.v2f64" => "__builtin_amdgpu_ldexp",
-                    "ldexp.v4f32" => "__builtin_amdgpu_ldexp",
-                    "rcp.f32" => "__builtin_amdgpu_rcp",
-                    "rcp.f64" => "__builtin_amdgpu_rcp",
-                    "rcp.v2f64" => "__builtin_amdgpu_rcp",
-                    "rcp.v4f32" => "__builtin_amdgpu_rcp",
-                    "rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped",
-                    "rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped",
-                    "rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped",
-                    "rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped",
-                    "rsq.f32" => "__builtin_amdgpu_rsq",
-                    "rsq.f64" => "__builtin_amdgpu_rsq",
-                    "rsq.v2f64" => "__builtin_amdgpu_rsq",
-                    "rsq.v4f32" => "__builtin_amdgpu_rsq",
-                    "trig.preop.f32" => "__builtin_amdgpu_trig_preop",
-                    "trig.preop.f64" => "__builtin_amdgpu_trig_preop",
-                    "trig.preop.v2f64" => "__builtin_amdgpu_trig_preop",
-                    "trig.preop.v4f32" => "__builtin_amdgpu_trig_preop",
-                    _ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
-                }
-            }
-            AMDGPU(name, full_name)
-        }
         "aarch64" => {
             fn aarch64(name: &str, full_name: &str) -> &'static str {
                 match name {
@@ -58,6 +24,7 @@ fn aarch64(name: &str, full_name: &str) -> &'static str {
                     "gcsss" => "__builtin_arm_gcsss",
                     "isb" => "__builtin_arm_isb",
                     "prefetch" => "__builtin_arm_prefetch",
+                    "range.prefetch" => "__builtin_arm_range_prefetch",
                     "sme.in.streaming.mode" => "__builtin_arm_in_streaming_mode",
                     "sve.aesd" => "__builtin_sve_svaesd_u8",
                     "sve.aese" => "__builtin_sve_svaese_u8",
@@ -448,6 +415,7 @@ fn amdgcn(name: &str, full_name: &str) -> &'static str {
                     "s.wait.event.export.ready" => "__builtin_amdgcn_s_wait_event_export_ready",
                     "s.wait.tensorcnt" => "__builtin_amdgcn_s_wait_tensorcnt",
                     "s.waitcnt" => "__builtin_amdgcn_s_waitcnt",
+                    "s.wakeup.barrier" => "__builtin_amdgcn_s_wakeup_barrier",
                     "sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8",
                     "sad.u16" => "__builtin_amdgcn_sad_u16",
                     "sad.u8" => "__builtin_amdgcn_sad_u8",
@@ -537,8 +505,6 @@ fn arm(name: &str, full_name: &str) -> &'static str {
                     "ldcl" => "__builtin_arm_ldcl",
                     "mcr" => "__builtin_arm_mcr",
                     "mcr2" => "__builtin_arm_mcr2",
-                    "mcrr" => "__builtin_arm_mcrr",
-                    "mcrr2" => "__builtin_arm_mcrr2",
                     "mrc" => "__builtin_arm_mrc",
                     "mrc2" => "__builtin_arm_mrc2",
                     "qadd" => "__builtin_arm_qadd",
@@ -595,7 +561,6 @@ fn arm(name: &str, full_name: &str) -> &'static str {
                     "stcl" => "__builtin_arm_stcl",
                     "sxtab16" => "__builtin_arm_sxtab16",
                     "sxtb16" => "__builtin_arm_sxtb16",
-                    "thread.pointer" => "__builtin_thread_pointer",
                     "uadd16" => "__builtin_arm_uadd16",
                     "uadd8" => "__builtin_arm_uadd8",
                     "uasx" => "__builtin_arm_uasx",
@@ -646,16 +611,6 @@ fn bpf(name: &str, full_name: &str) -> &'static str {
             }
             bpf(name, full_name)
         }
-        "cuda" => {
-            fn cuda(name: &str, full_name: &str) -> &'static str {
-                match name {
-                    // cuda
-                    "syncthreads" => "__syncthreads",
-                    _ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
-                }
-            }
-            cuda(name, full_name)
-        }
         "hexagon" => {
             fn hexagon(name: &str, full_name: &str) -> &'static str {
                 match name {
@@ -959,19 +914,10 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge",
                     "F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt",
                     "F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo",
-                    "F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd",
-                    "F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn",
-                    "F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr",
-                    "F2.dffma" => "__builtin_HEXAGON_F2_dffma",
-                    "F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib",
-                    "F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc",
-                    "F2.dffms" => "__builtin_HEXAGON_F2_dffms",
-                    "F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib",
                     "F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n",
                     "F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p",
                     "F2.dfmax" => "__builtin_HEXAGON_F2_dfmax",
                     "F2.dfmin" => "__builtin_HEXAGON_F2_dfmin",
-                    "F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy",
                     "F2.dfmpyfix" => "__builtin_HEXAGON_F2_dfmpyfix",
                     "F2.dfmpyhh" => "__builtin_HEXAGON_F2_dfmpyhh",
                     "F2.dfmpylh" => "__builtin_HEXAGON_F2_dfmpylh",
@@ -1398,7 +1344,6 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw",
                     "S2.brev" => "__builtin_HEXAGON_S2_brev",
                     "S2.brevp" => "__builtin_HEXAGON_S2_brevp",
-                    "S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin",
                     "S2.cl0" => "__builtin_HEXAGON_S2_cl0",
                     "S2.cl0p" => "__builtin_HEXAGON_S2_cl0p",
                     "S2.cl1" => "__builtin_HEXAGON_S2_cl1",
@@ -1569,7 +1514,6 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "S6.vsplatrbp" => "__builtin_HEXAGON_S6_vsplatrbp",
                     "S6.vtrunehb.ppp" => "__builtin_HEXAGON_S6_vtrunehb_ppp",
                     "S6.vtrunohb.ppp" => "__builtin_HEXAGON_S6_vtrunohb_ppp",
-                    "SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh",
                     "V6.extractw" => "__builtin_HEXAGON_V6_extractw",
                     "V6.extractw.128B" => "__builtin_HEXAGON_V6_extractw_128B",
                     "V6.get.qfext" => "__builtin_HEXAGON_V6_get_qfext",
@@ -2160,14 +2104,6 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "V6.vlsrwv.128B" => "__builtin_HEXAGON_V6_vlsrwv_128B",
                     "V6.vlut4" => "__builtin_HEXAGON_V6_vlut4",
                     "V6.vlut4.128B" => "__builtin_HEXAGON_V6_vlut4_128B",
-                    "V6.vlutb" => "__builtin_HEXAGON_V6_vlutb",
-                    "V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B",
-                    "V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc",
-                    "V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B",
-                    "V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv",
-                    "V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B",
-                    "V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc",
-                    "V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B",
                     "V6.vlutvvb" => "__builtin_HEXAGON_V6_vlutvvb",
                     "V6.vlutvvb.128B" => "__builtin_HEXAGON_V6_vlutvvb_128B",
                     "V6.vlutvvb.nm" => "__builtin_HEXAGON_V6_vlutvvb_nm",
@@ -2669,17 +2605,6 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "Y6.dmresume" => "__builtin_HEXAGON_Y6_dmresume",
                     "Y6.dmstart" => "__builtin_HEXAGON_Y6_dmstart",
                     "Y6.dmwait" => "__builtin_HEXAGON_Y6_dmwait",
-                    "brev.ldb" => "__builtin_brev_ldb",
-                    "brev.ldd" => "__builtin_brev_ldd",
-                    "brev.ldh" => "__builtin_brev_ldh",
-                    "brev.ldub" => "__builtin_brev_ldub",
-                    "brev.lduh" => "__builtin_brev_lduh",
-                    "brev.ldw" => "__builtin_brev_ldw",
-                    "brev.stb" => "__builtin_brev_stb",
-                    "brev.std" => "__builtin_brev_std",
-                    "brev.sth" => "__builtin_brev_sth",
-                    "brev.sthhi" => "__builtin_brev_sthhi",
-                    "brev.stw" => "__builtin_brev_stw",
                     "circ.ldb" => "__builtin_circ_ldb",
                     "circ.ldd" => "__builtin_circ_ldd",
                     "circ.ldh" => "__builtin_circ_ldh",
@@ -2691,7 +2616,6 @@ fn hexagon(name: &str, full_name: &str) -> &'static str {
                     "circ.sth" => "__builtin_circ_sth",
                     "circ.sthhi" => "__builtin_circ_sthhi",
                     "circ.stw" => "__builtin_circ_stw",
-                    "mm256i.vaddw" => "__builtin__mm256i_vaddw",
                     "prefetch" => "__builtin_HEXAGON_prefetch",
                     "vmemcpy" => "__builtin_hexagon_vmemcpy",
                     "vmemset" => "__builtin_hexagon_vmemset",
@@ -4910,45 +4834,37 @@ fn mips(name: &str, full_name: &str) -> &'static str {
             fn nvvm(name: &str, full_name: &str) -> &'static str {
                 match name {
                     // nvvm
-                    "abs.i" => "__nvvm_abs_i",
-                    "abs.ll" => "__nvvm_abs_ll",
                     "activemask" => "__nvvm_activemask",
                     "add.rm.d" => "__nvvm_add_rm_d",
                     "add.rm.f" => "__nvvm_add_rm_f",
                     "add.rm.ftz.f" => "__nvvm_add_rm_ftz_f",
+                    "add.rm.ftz.sat.f" => "__nvvm_add_rm_ftz_sat_f",
+                    "add.rm.sat.f" => "__nvvm_add_rm_sat_f",
                     "add.rn.d" => "__nvvm_add_rn_d",
                     "add.rn.f" => "__nvvm_add_rn_f",
                     "add.rn.ftz.f" => "__nvvm_add_rn_ftz_f",
+                    "add.rn.ftz.sat.f" => "__nvvm_add_rn_ftz_sat_f",
+                    "add.rn.sat.f" => "__nvvm_add_rn_sat_f",
                     "add.rp.d" => "__nvvm_add_rp_d",
                     "add.rp.f" => "__nvvm_add_rp_f",
                     "add.rp.ftz.f" => "__nvvm_add_rp_ftz_f",
+                    "add.rp.ftz.sat.f" => "__nvvm_add_rp_ftz_sat_f",
+                    "add.rp.sat.f" => "__nvvm_add_rp_sat_f",
                     "add.rz.d" => "__nvvm_add_rz_d",
                     "add.rz.f" => "__nvvm_add_rz_f",
                     "add.rz.ftz.f" => "__nvvm_add_rz_ftz_f",
-                    "bar.sync" => "__nvvm_bar_sync",
+                    "add.rz.ftz.sat.f" => "__nvvm_add_rz_ftz_sat_f",
+                    "add.rz.sat.f" => "__nvvm_add_rz_sat_f",
                     "bar.warp.sync" => "__nvvm_bar_warp_sync",
-                    "barrier0" => "__nvvm_bar0",
-                    // [DUPLICATE]: "barrier0" => "__syncthreads",
-                    "barrier0.and" => "__nvvm_bar0_and",
-                    "barrier0.or" => "__nvvm_bar0_or",
-                    "barrier0.popc" => "__nvvm_bar0_popc",
                     "bf16x2.to.ue8m0x2.rp" => "__nvvm_bf16x2_to_ue8m0x2_rp",
                     "bf16x2.to.ue8m0x2.rp.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rp_satfinite",
                     "bf16x2.to.ue8m0x2.rz" => "__nvvm_bf16x2_to_ue8m0x2_rz",
                     "bf16x2.to.ue8m0x2.rz.satfinite" => "__nvvm_bf16x2_to_ue8m0x2_rz_satfinite",
                     "bf2h.rn" => "__nvvm_bf2h_rn",
                     "bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz",
-                    "bitcast.d2ll" => "__nvvm_bitcast_d2ll",
-                    "bitcast.f2i" => "__nvvm_bitcast_f2i",
-                    "bitcast.i2f" => "__nvvm_bitcast_i2f",
-                    "bitcast.ll2d" => "__nvvm_bitcast_ll2d",
-                    "brev32" => "__nvvm_brev32",
-                    "brev64" => "__nvvm_brev64",
                     "ceil.d" => "__nvvm_ceil_d",
                     "ceil.f" => "__nvvm_ceil_f",
                     "ceil.ftz.f" => "__nvvm_ceil_ftz_f",
-                    "clz.i" => "__nvvm_clz_i",
-                    "clz.ll" => "__nvvm_clz_ll",
                     "cos.approx.f" => "__nvvm_cos_approx_f",
                     "cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f",
                     "cp.async.commit.group" => "__nvvm_cp_async_commit_group",
@@ -5012,9 +4928,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "e4m3x2.to.f16x2.rn.relu" => "__nvvm_e4m3x2_to_f16x2_rn_relu",
                     "e5m2x2.to.f16x2.rn" => "__nvvm_e5m2x2_to_f16x2_rn",
                     "e5m2x2.to.f16x2.rn.relu" => "__nvvm_e5m2x2_to_f16x2_rn_relu",
-                    "ex2.approx.d" => "__nvvm_ex2_approx_d",
-                    "ex2.approx.f" => "__nvvm_ex2_approx_f",
-                    "ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f",
                     "exit" => "__nvvm_exit",
                     "f16x2.to.e4m3x2.rn" => "__nvvm_f16x2_to_e4m3x2_rn",
                     "f16x2.to.e4m3x2.rn.relu" => "__nvvm_f16x2_to_e4m3x2_rn_relu",
@@ -5100,9 +5013,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                         "__nvvm_f32x4_to_e5m2x4_rs_relu_satfinite"
                     }
                     "f32x4.to.e5m2x4.rs.satfinite" => "__nvvm_f32x4_to_e5m2x4_rs_satfinite",
-                    "fabs.d" => "__nvvm_fabs_d",
-                    "fabs.f" => "__nvvm_fabs_f",
-                    "fabs.ftz.f" => "__nvvm_fabs_ftz_f",
                     "ff.to.e2m1x2.rn.relu.satfinite" => "__nvvm_ff_to_e2m1x2_rn_relu_satfinite",
                     "ff.to.e2m1x2.rn.satfinite" => "__nvvm_ff_to_e2m1x2_rn_satfinite",
                     "ff.to.e2m3x2.rn.relu.satfinite" => "__nvvm_ff_to_e2m3x2_rn_relu_satfinite",
@@ -5147,6 +5057,8 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "fma.rm.d" => "__nvvm_fma_rm_d",
                     "fma.rm.f" => "__nvvm_fma_rm_f",
                     "fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f",
+                    "fma.rm.ftz.sat.f" => "__nvvm_fma_rm_ftz_sat_f",
+                    "fma.rm.sat.f" => "__nvvm_fma_rm_sat_f",
                     "fma.rn.bf16" => "__nvvm_fma_rn_bf16",
                     "fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2",
                     "fma.rn.d" => "__nvvm_fma_rn_d",
@@ -5158,16 +5070,22 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "fma.rn.ftz.relu.bf16x2" => "__nvvm_fma_rn_ftz_relu_bf16x2",
                     "fma.rn.ftz.sat.bf16" => "__nvvm_fma_rn_ftz_sat_bf16",
                     "fma.rn.ftz.sat.bf16x2" => "__nvvm_fma_rn_ftz_sat_bf16x2",
+                    "fma.rn.ftz.sat.f" => "__nvvm_fma_rn_ftz_sat_f",
                     "fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16",
                     "fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2",
                     "fma.rn.sat.bf16" => "__nvvm_fma_rn_sat_bf16",
                     "fma.rn.sat.bf16x2" => "__nvvm_fma_rn_sat_bf16x2",
+                    "fma.rn.sat.f" => "__nvvm_fma_rn_sat_f",
                     "fma.rp.d" => "__nvvm_fma_rp_d",
                     "fma.rp.f" => "__nvvm_fma_rp_f",
                     "fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f",
+                    "fma.rp.ftz.sat.f" => "__nvvm_fma_rp_ftz_sat_f",
+                    "fma.rp.sat.f" => "__nvvm_fma_rp_sat_f",
                     "fma.rz.d" => "__nvvm_fma_rz_d",
                     "fma.rz.f" => "__nvvm_fma_rz_f",
                     "fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f",
+                    "fma.rz.ftz.sat.f" => "__nvvm_fma_rz_ftz_sat_f",
+                    "fma.rz.sat.f" => "__nvvm_fma_rz_sat_f",
                     "fmax.bf16" => "__nvvm_fmax_bf16",
                     "fmax.bf16x2" => "__nvvm_fmax_bf16x2",
                     "fmax.d" => "__nvvm_fmax_d",
@@ -5219,7 +5137,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2",
                     "fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f",
                     "fns" => "__nvvm_fns",
-                    "h2f" => "__nvvm_h2f",
                     "i2d.rm" => "__nvvm_i2d_rm",
                     "i2d.rn" => "__nvvm_i2d_rn",
                     "i2d.rp" => "__nvvm_i2d_rp",
@@ -5250,10 +5167,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "lohi.i2d" => "__nvvm_lohi_i2d",
                     "match.any.sync.i32" => "__nvvm_match_any_sync_i32",
                     "match.any.sync.i64" => "__nvvm_match_any_sync_i64",
-                    "max.i" => "__nvvm_max_i",
-                    "max.ll" => "__nvvm_max_ll",
-                    "max.ui" => "__nvvm_max_ui",
-                    "max.ull" => "__nvvm_max_ull",
                     "mbarrier.arrive" => "__nvvm_mbarrier_arrive",
                     "mbarrier.arrive.drop" => "__nvvm_mbarrier_arrive_drop",
                     "mbarrier.arrive.drop.noComplete" => "__nvvm_mbarrier_arrive_drop_noComplete",
@@ -5276,10 +5189,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "membar.cta" => "__nvvm_membar_cta",
                     "membar.gl" => "__nvvm_membar_gl",
                     "membar.sys" => "__nvvm_membar_sys",
-                    "min.i" => "__nvvm_min_i",
-                    "min.ll" => "__nvvm_min_ll",
-                    "min.ui" => "__nvvm_min_ui",
-                    "min.ull" => "__nvvm_min_ull",
                     "mul.rm.d" => "__nvvm_mul_rm_d",
                     "mul.rm.f" => "__nvvm_mul_rm_f",
                     "mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f",
@@ -5304,8 +5213,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "neg.bf16" => "__nvvm_neg_bf16",
                     "neg.bf16x2" => "__nvvm_neg_bf16x2",
                     "pm.event.mask" => "__nvvm_pm_event_mask",
-                    "popc.i" => "__nvvm_popc_i",
-                    "popc.ll" => "__nvvm_popc_ll",
                     "prmt" => "__nvvm_prmt",
                     "rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d",
                     "rcp.approx.ftz.f" => "__nvvm_rcp_approx_ftz_f",
@@ -5322,9 +5229,7 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "rcp.rz.f" => "__nvvm_rcp_rz_f",
                     "rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f",
                     "read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_clock",
-                    // [DUPLICATE]: "read.ptx.sreg.clock" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_clock64",
-                    // [DUPLICATE]: "read.ptx.sreg.clock64" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.ctaid.w" => "__nvvm_read_ptx_sreg_ctaid_w",
                     "read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x",
                     "read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y",
@@ -5364,49 +5269,34 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "read.ptx.sreg.globaltimer" => "__nvvm_read_ptx_sreg_globaltimer",
                     "read.ptx.sreg.globaltimer.lo" => "__nvvm_read_ptx_sreg_globaltimer_lo",
                     "read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_gridid",
-                    // [DUPLICATE]: "read.ptx.sreg.gridid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_laneid",
-                    // [DUPLICATE]: "read.ptx.sreg.laneid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_lanemask_eq",
-                    // [DUPLICATE]: "read.ptx.sreg.lanemask.eq" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_lanemask_ge",
-                    // [DUPLICATE]: "read.ptx.sreg.lanemask.ge" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_lanemask_gt",
-                    // [DUPLICATE]: "read.ptx.sreg.lanemask.gt" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_lanemask_le",
-                    // [DUPLICATE]: "read.ptx.sreg.lanemask.le" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_lanemask_lt",
-                    // [DUPLICATE]: "read.ptx.sreg.lanemask.lt" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.nctaid.w" => "__nvvm_read_ptx_sreg_nctaid_w",
                     "read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x",
                     "read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y",
                     "read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z",
                     "read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_nsmid",
-                    // [DUPLICATE]: "read.ptx.sreg.nsmid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.ntid.w" => "__nvvm_read_ptx_sreg_ntid_w",
                     "read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x",
                     "read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y",
                     "read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z",
                     "read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_nwarpid",
-                    // [DUPLICATE]: "read.ptx.sreg.nwarpid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_pm0",
-                    // [DUPLICATE]: "read.ptx.sreg.pm0" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_pm1",
-                    // [DUPLICATE]: "read.ptx.sreg.pm1" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_pm2",
-                    // [DUPLICATE]: "read.ptx.sreg.pm2" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_pm3",
-                    // [DUPLICATE]: "read.ptx.sreg.pm3" => "__nvvm_read_ptx_sreg_",
+                    "read.ptx.sreg.pm4" => "__nvvm_read_ptx_sreg_pm4",
                     "read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_smid",
-                    // [DUPLICATE]: "read.ptx.sreg.smid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.tid.w" => "__nvvm_read_ptx_sreg_tid_w",
                     "read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x",
                     "read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y",
                     "read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z",
                     "read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_warpid",
-                    // [DUPLICATE]: "read.ptx.sreg.warpid" => "__nvvm_read_ptx_sreg_",
                     "read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize",
-                    // [DUPLICATE]: "read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_",
                     "redux.sync.add" => "__nvvm_redux_sync_add",
                     "redux.sync.and" => "__nvvm_redux_sync_and",
                     "redux.sync.fmax" => "__nvvm_redux_sync_fmax",
@@ -5424,9 +5314,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "redux.sync.umin" => "__nvvm_redux_sync_umin",
                     "redux.sync.xor" => "__nvvm_redux_sync_xor",
                     "reflect" => "__nvvm_reflect",
-                    "rotate.b32" => "__nvvm_rotate_b32",
-                    "rotate.b64" => "__nvvm_rotate_b64",
-                    "rotate.right.b64" => "__nvvm_rotate_right_b64",
                     "round.d" => "__nvvm_round_d",
                     "round.f" => "__nvvm_round_f",
                     "round.ftz.f" => "__nvvm_round_ftz_f",
@@ -5692,7 +5579,6 @@ fn nvvm(name: &str, full_name: &str) -> &'static str {
                     "sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap",
                     "sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap",
                     "sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap",
-                    "swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64",
                     "trunc.d" => "__nvvm_trunc_d",
                     "trunc.f" => "__nvvm_trunc_f",
                     "trunc.ftz.f" => "__nvvm_trunc_ftz_f",
@@ -6132,89 +6018,6 @@ fn ppc(name: &str, full_name: &str) -> &'static str {
                     "packed2zoned" => "__builtin_ppc_packed2zoned",
                     "pdepd" => "__builtin_pdepd",
                     "pextd" => "__builtin_pextd",
-                    "qpx.qvfabs" => "__builtin_qpx_qvfabs",
-                    "qpx.qvfadd" => "__builtin_qpx_qvfadd",
-                    "qpx.qvfadds" => "__builtin_qpx_qvfadds",
-                    "qpx.qvfcfid" => "__builtin_qpx_qvfcfid",
-                    "qpx.qvfcfids" => "__builtin_qpx_qvfcfids",
-                    "qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu",
-                    "qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus",
-                    "qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq",
-                    "qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt",
-                    "qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt",
-                    "qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn",
-                    "qpx.qvfctid" => "__builtin_qpx_qvfctid",
-                    "qpx.qvfctidu" => "__builtin_qpx_qvfctidu",
-                    "qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz",
-                    "qpx.qvfctidz" => "__builtin_qpx_qvfctidz",
-                    "qpx.qvfctiw" => "__builtin_qpx_qvfctiw",
-                    "qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu",
-                    "qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz",
-                    "qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz",
-                    "qpx.qvflogical" => "__builtin_qpx_qvflogical",
-                    "qpx.qvfmadd" => "__builtin_qpx_qvfmadd",
-                    "qpx.qvfmadds" => "__builtin_qpx_qvfmadds",
-                    "qpx.qvfmsub" => "__builtin_qpx_qvfmsub",
-                    "qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs",
-                    "qpx.qvfmul" => "__builtin_qpx_qvfmul",
-                    "qpx.qvfmuls" => "__builtin_qpx_qvfmuls",
-                    "qpx.qvfnabs" => "__builtin_qpx_qvfnabs",
-                    "qpx.qvfneg" => "__builtin_qpx_qvfneg",
-                    "qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd",
-                    "qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds",
-                    "qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub",
-                    "qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs",
-                    "qpx.qvfperm" => "__builtin_qpx_qvfperm",
-                    "qpx.qvfre" => "__builtin_qpx_qvfre",
-                    "qpx.qvfres" => "__builtin_qpx_qvfres",
-                    "qpx.qvfrim" => "__builtin_qpx_qvfrim",
-                    "qpx.qvfrin" => "__builtin_qpx_qvfrin",
-                    "qpx.qvfrip" => "__builtin_qpx_qvfrip",
-                    "qpx.qvfriz" => "__builtin_qpx_qvfriz",
-                    "qpx.qvfrsp" => "__builtin_qpx_qvfrsp",
-                    "qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte",
-                    "qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes",
-                    "qpx.qvfsel" => "__builtin_qpx_qvfsel",
-                    "qpx.qvfsub" => "__builtin_qpx_qvfsub",
-                    "qpx.qvfsubs" => "__builtin_qpx_qvfsubs",
-                    "qpx.qvftstnan" => "__builtin_qpx_qvftstnan",
-                    "qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd",
-                    "qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds",
-                    "qpx.qvfxmul" => "__builtin_qpx_qvfxmul",
-                    "qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls",
-                    "qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd",
-                    "qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds",
-                    "qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd",
-                    "qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds",
-                    "qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd",
-                    "qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds",
-                    "qpx.qvgpci" => "__builtin_qpx_qvgpci",
-                    "qpx.qvlfcd" => "__builtin_qpx_qvlfcd",
-                    "qpx.qvlfcda" => "__builtin_qpx_qvlfcda",
-                    "qpx.qvlfcs" => "__builtin_qpx_qvlfcs",
-                    "qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa",
-                    "qpx.qvlfd" => "__builtin_qpx_qvlfd",
-                    "qpx.qvlfda" => "__builtin_qpx_qvlfda",
-                    "qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa",
-                    "qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa",
-                    "qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz",
-                    "qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza",
-                    "qpx.qvlfs" => "__builtin_qpx_qvlfs",
-                    "qpx.qvlfsa" => "__builtin_qpx_qvlfsa",
-                    "qpx.qvlpcld" => "__builtin_qpx_qvlpcld",
-                    "qpx.qvlpcls" => "__builtin_qpx_qvlpcls",
-                    "qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd",
-                    "qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs",
-                    "qpx.qvstfcd" => "__builtin_qpx_qvstfcd",
-                    "qpx.qvstfcda" => "__builtin_qpx_qvstfcda",
-                    "qpx.qvstfcs" => "__builtin_qpx_qvstfcs",
-                    "qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa",
-                    "qpx.qvstfd" => "__builtin_qpx_qvstfd",
-                    "qpx.qvstfda" => "__builtin_qpx_qvstfda",
-                    "qpx.qvstfiw" => "__builtin_qpx_qvstfiw",
-                    "qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa",
-                    "qpx.qvstfs" => "__builtin_qpx_qvstfs",
-                    "qpx.qvstfsa" => "__builtin_qpx_qvstfsa",
                     "readflm" => "__builtin_readflm",
                     "rlwimi" => "__builtin_ppc_rlwimi",
                     "rlwnm" => "__builtin_ppc_rlwnm",
@@ -6329,33 +6132,6 @@ fn ppc(name: &str, full_name: &str) -> &'static str {
             }
             ppc(name, full_name)
         }
-        "ptx" => {
-            fn ptx(name: &str, full_name: &str) -> &'static str {
-                match name {
-                    // ptx
-                    "bar.sync" => "__builtin_ptx_bar_sync",
-                    "read.clock" => "__builtin_ptx_read_clock",
-                    "read.clock64" => "__builtin_ptx_read_clock64",
-                    "read.gridid" => "__builtin_ptx_read_gridid",
-                    "read.laneid" => "__builtin_ptx_read_laneid",
-                    "read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq",
-                    "read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge",
-                    "read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt",
-                    "read.lanemask.le" => "__builtin_ptx_read_lanemask_le",
-                    "read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt",
-                    "read.nsmid" => "__builtin_ptx_read_nsmid",
-                    "read.nwarpid" => "__builtin_ptx_read_nwarpid",
-                    "read.pm0" => "__builtin_ptx_read_pm0",
-                    "read.pm1" => "__builtin_ptx_read_pm1",
-                    "read.pm2" => "__builtin_ptx_read_pm2",
-                    "read.pm3" => "__builtin_ptx_read_pm3",
-                    "read.smid" => "__builtin_ptx_read_smid",
-                    "read.warpid" => "__builtin_ptx_read_warpid",
-                    _ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
-                }
-            }
-            ptx(name, full_name)
-        }
         "r600" => {
             fn r600(name: &str, full_name: &str) -> &'static str {
                 match name {
@@ -6610,6 +6386,7 @@ fn s390(name: &str, full_name: &str) -> &'static str {
             fn spv(name: &str, full_name: &str) -> &'static str {
                 match name {
                     // spv
+                    "group.memory.barrier.with.group.sync" => "__builtin_spirv_group_barrier",
                     "num.subgroups" => "__builtin_spirv_num_subgroups",
                     "subgroup.id" => "__builtin_spirv_subgroup_id",
                     "subgroup.local.invocation.id" => {
@@ -6617,6 +6394,7 @@ fn spv(name: &str, full_name: &str) -> &'static str {
                     }
                     "subgroup.max.size" => "__builtin_spirv_subgroup_max_size",
                     "subgroup.size" => "__builtin_spirv_subgroup_size",
+                    "wave.ballot" => "__builtin_spirv_subgroup_ballot",
                     _ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
                 }
             }
@@ -7902,10 +7680,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "aadd64" => "__builtin_ia32_aadd64",
                     "aand32" => "__builtin_ia32_aand32",
                     "aand64" => "__builtin_ia32_aand64",
-                    "addcarry.u32" => "__builtin_ia32_addcarry_u32",
-                    "addcarry.u64" => "__builtin_ia32_addcarry_u64",
-                    "addcarryx.u32" => "__builtin_ia32_addcarryx_u32",
-                    "addcarryx.u64" => "__builtin_ia32_addcarryx_u64",
                     "aesni.aesdec" => "__builtin_ia32_aesdec128",
                     "aesni.aesdec.256" => "__builtin_ia32_aesdec256",
                     "aesni.aesdec.512" => "__builtin_ia32_aesdec512",
@@ -7924,18 +7698,11 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "aor64" => "__builtin_ia32_aor64",
                     "avx.addsub.pd.256" => "__builtin_ia32_addsubpd256",
                     "avx.addsub.ps.256" => "__builtin_ia32_addsubps256",
-                    "avx.blend.pd.256" => "__builtin_ia32_blendpd256",
-                    "avx.blend.ps.256" => "__builtin_ia32_blendps256",
                     "avx.blendv.pd.256" => "__builtin_ia32_blendvpd256",
                     "avx.blendv.ps.256" => "__builtin_ia32_blendvps256",
-                    "avx.cmp.pd.256" => "__builtin_ia32_cmppd256",
-                    "avx.cmp.ps.256" => "__builtin_ia32_cmpps256",
                     "avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256",
                     "avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256",
-                    "avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256",
                     "avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256",
-                    "avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256",
-                    "avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256",
                     "avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256",
                     "avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256",
                     "avx.dp.ps.256" => "__builtin_ia32_dpps256",
@@ -7962,25 +7729,7 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx.ptestnzc.256" => "__builtin_ia32_ptestnzc256",
                     "avx.ptestz.256" => "__builtin_ia32_ptestz256",
                     "avx.rcp.ps.256" => "__builtin_ia32_rcpps256",
-                    "avx.round.pd.256" => "__builtin_ia32_roundpd256",
-                    "avx.round.ps.256" => "__builtin_ia32_roundps256",
                     "avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256",
-                    "avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256",
-                    "avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256",
-                    "avx.storeu.dq.256" => "__builtin_ia32_storedqu256",
-                    "avx.storeu.pd.256" => "__builtin_ia32_storeupd256",
-                    "avx.storeu.ps.256" => "__builtin_ia32_storeups256",
-                    "avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256",
-                    "avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256",
-                    "avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256",
-                    "avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256",
-                    "avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256",
-                    "avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256",
-                    "avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256",
-                    "avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256",
-                    "avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256",
-                    "avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256",
-                    "avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256",
                     "avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd",
                     "avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256",
                     "avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps",
@@ -8265,33 +8014,14 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx2.maskstore.d.256" => "__builtin_ia32_maskstored256",
                     "avx2.maskstore.q" => "__builtin_ia32_maskstoreq",
                     "avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256",
-                    "avx2.movntdqa" => "__builtin_ia32_movntdqa256",
                     "avx2.mpsadbw" => "__builtin_ia32_mpsadbw256",
-                    "avx2.pabs.b" => "__builtin_ia32_pabsb256",
-                    "avx2.pabs.d" => "__builtin_ia32_pabsd256",
-                    "avx2.pabs.w" => "__builtin_ia32_pabsw256",
                     "avx2.packssdw" => "__builtin_ia32_packssdw256",
                     "avx2.packsswb" => "__builtin_ia32_packsswb256",
                     "avx2.packusdw" => "__builtin_ia32_packusdw256",
                     "avx2.packuswb" => "__builtin_ia32_packuswb256",
-                    "avx2.padds.b" => "__builtin_ia32_paddsb256",
-                    "avx2.padds.w" => "__builtin_ia32_paddsw256",
-                    "avx2.paddus.b" => "__builtin_ia32_paddusb256",
-                    "avx2.paddus.w" => "__builtin_ia32_paddusw256",
                     "avx2.pavg.b" => "__builtin_ia32_pavgb256",
                     "avx2.pavg.w" => "__builtin_ia32_pavgw256",
-                    "avx2.pblendd.128" => "__builtin_ia32_pblendd128",
-                    "avx2.pblendd.256" => "__builtin_ia32_pblendd256",
                     "avx2.pblendvb" => "__builtin_ia32_pblendvb256",
-                    "avx2.pblendw" => "__builtin_ia32_pblendw256",
-                    "avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128",
-                    "avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256",
-                    "avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128",
-                    "avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256",
-                    "avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128",
-                    "avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256",
-                    "avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128",
-                    "avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256",
                     "avx2.permd" => "__builtin_ia32_permvarsi256",
                     "avx2.permps" => "__builtin_ia32_permvarsf256",
                     "avx2.phadd.d" => "__builtin_ia32_phaddd256",
@@ -8302,44 +8032,16 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx2.phsub.w" => "__builtin_ia32_phsubw256",
                     "avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256",
                     "avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256",
-                    "avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256",
-                    "avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256",
-                    "avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256",
-                    "avx2.pmaxu.b" => "__builtin_ia32_pmaxub256",
-                    "avx2.pmaxu.d" => "__builtin_ia32_pmaxud256",
-                    "avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256",
-                    "avx2.pmins.b" => "__builtin_ia32_pminsb256",
-                    "avx2.pmins.d" => "__builtin_ia32_pminsd256",
-                    "avx2.pmins.w" => "__builtin_ia32_pminsw256",
-                    "avx2.pminu.b" => "__builtin_ia32_pminub256",
-                    "avx2.pminu.d" => "__builtin_ia32_pminud256",
-                    "avx2.pminu.w" => "__builtin_ia32_pminuw256",
                     "avx2.pmovmskb" => "__builtin_ia32_pmovmskb256",
-                    "avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256",
-                    "avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256",
-                    "avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256",
-                    "avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256",
-                    "avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256",
-                    "avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256",
-                    "avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256",
-                    "avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256",
-                    "avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256",
-                    "avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256",
-                    "avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256",
-                    "avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256",
-                    "avx2.pmul.dq" => "__builtin_ia32_pmuldq256",
                     "avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256",
                     "avx2.pmulh.w" => "__builtin_ia32_pmulhw256",
                     "avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256",
-                    "avx2.pmulu.dq" => "__builtin_ia32_pmuludq256",
                     "avx2.psad.bw" => "__builtin_ia32_psadbw256",
                     "avx2.pshuf.b" => "__builtin_ia32_pshufb256",
                     "avx2.psign.b" => "__builtin_ia32_psignb256",
                     "avx2.psign.d" => "__builtin_ia32_psignd256",
                     "avx2.psign.w" => "__builtin_ia32_psignw256",
                     "avx2.psll.d" => "__builtin_ia32_pslld256",
-                    "avx2.psll.dq" => "__builtin_ia32_pslldqi256",
-                    "avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift",
                     "avx2.psll.q" => "__builtin_ia32_psllq256",
                     "avx2.psll.w" => "__builtin_ia32_psllw256",
                     "avx2.pslli.d" => "__builtin_ia32_pslldi256",
@@ -8356,8 +8058,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx2.psrav.d" => "__builtin_ia32_psrav4si",
                     "avx2.psrav.d.256" => "__builtin_ia32_psrav8si",
                     "avx2.psrl.d" => "__builtin_ia32_psrld256",
-                    "avx2.psrl.dq" => "__builtin_ia32_psrldqi256",
-                    "avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift",
                     "avx2.psrl.q" => "__builtin_ia32_psrlq256",
                     "avx2.psrl.w" => "__builtin_ia32_psrlw256",
                     "avx2.psrli.d" => "__builtin_ia32_psrldi256",
@@ -8367,15 +8067,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si",
                     "avx2.psrlv.q" => "__builtin_ia32_psrlv2di",
                     "avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di",
-                    "avx2.psubs.b" => "__builtin_ia32_psubsb256",
-                    "avx2.psubs.w" => "__builtin_ia32_psubsw256",
-                    "avx2.psubus.b" => "__builtin_ia32_psubusb256",
-                    "avx2.psubus.w" => "__builtin_ia32_psubusw256",
-                    "avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256",
-                    "avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps",
-                    "avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256",
-                    "avx2.vextracti128" => "__builtin_ia32_extract128i256",
-                    "avx2.vinserti128" => "__builtin_ia32_insert128i256",
                     "avx2.vpdpbssd.128" => "__builtin_ia32_vpdpbssd128",
                     "avx2.vpdpbssd.256" => "__builtin_ia32_vpdpbssd256",
                     "avx2.vpdpbssds.128" => "__builtin_ia32_vpdpbssds128",
@@ -8400,7 +8091,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256",
                     "avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128",
                     "avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256",
-                    "avx2.vperm2i128" => "__builtin_ia32_permti256",
                     "avx512.add.pd.512" => "__builtin_ia32_addpd512",
                     "avx512.add.ps.512" => "__builtin_ia32_addps512",
                     "avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128",
@@ -8415,194 +8105,32 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128",
                     "avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256",
                     "avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512",
-                    "avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128",
-                    "avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256",
-                    "avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512",
-                    "avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128",
-                    "avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256",
-                    "avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512",
-                    "avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128",
-                    "avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256",
-                    "avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512",
-                    "avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128",
-                    "avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256",
-                    "avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512",
-                    "avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128",
-                    "avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256",
-                    "avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512",
-                    "avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128",
-                    "avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256",
-                    "avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512",
-                    "avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128",
-                    "avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256",
-                    "avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512",
-                    "avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi",
-                    "avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64",
-                    "avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32",
                     "avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64",
                     "avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32",
                     "avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64",
-                    "avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi",
-                    "avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64",
                     "avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32",
                     "avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64",
                     "avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32",
-                    // [DUPLICATE]: "avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi",
                     "avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64",
-                    // [DUPLICATE]: "avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64",
                     "avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32",
                     "avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64",
                     "avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32",
-                    // [DUPLICATE]: "avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi",
                     "avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64",
-                    // [DUPLICATE]: "avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64",
-                    "avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd",
-                    // [DUPLICATE]: "avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd32",
                     "avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32",
-                    // [DUPLICATE]: "avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss",
                     "avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64",
-                    // [DUPLICATE]: "avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd",
                     "avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64",
-                    // [DUPLICATE]: "avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss",
-                    "avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128",
-                    "avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256",
-                    "avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512",
                     "avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128",
                     "avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256",
                     "avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512",
                     "avx512.div.pd.512" => "__builtin_ia32_divpd512",
                     "avx512.div.ps.512" => "__builtin_ia32_divps512",
-                    "avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask",
-                    "avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask",
-                    "avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df",
-                    "avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si",
-                    "avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di",
-                    "avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf",
-                    "avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df",
-                    "avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si",
-                    "avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di",
-                    "avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf",
-                    "avx512.gather3div2.df" => "__builtin_ia32_gather3div2df",
-                    "avx512.gather3div2.di" => "__builtin_ia32_gather3div2di",
-                    "avx512.gather3div4.df" => "__builtin_ia32_gather3div4df",
-                    "avx512.gather3div4.di" => "__builtin_ia32_gather3div4di",
-                    "avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf",
-                    "avx512.gather3div4.si" => "__builtin_ia32_gather3div4si",
-                    "avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf",
-                    "avx512.gather3div8.si" => "__builtin_ia32_gather3div8si",
-                    "avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df",
-                    "avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di",
-                    "avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df",
-                    "avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di",
-                    "avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf",
-                    "avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si",
-                    "avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf",
-                    "avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si",
-                    "avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd",
-                    "avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps",
-                    "avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd",
-                    "avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps",
-                    "avx512.kand.w" => "__builtin_ia32_kandhi",
-                    "avx512.kandn.w" => "__builtin_ia32_kandnhi",
-                    "avx512.knot.w" => "__builtin_ia32_knothi",
-                    "avx512.kor.w" => "__builtin_ia32_korhi",
-                    "avx512.kortestc.w" => "__builtin_ia32_kortestchi",
-                    "avx512.kortestz.w" => "__builtin_ia32_kortestzhi",
-                    "avx512.kunpck.bw" => "__builtin_ia32_kunpckhi",
-                    "avx512.kunpck.dq" => "__builtin_ia32_kunpckdi",
-                    "avx512.kunpck.wd" => "__builtin_ia32_kunpcksi",
-                    "avx512.kxnor.w" => "__builtin_ia32_kxnorhi",
-                    "avx512.kxor.w" => "__builtin_ia32_kxorhi",
-                    "avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask",
-                    "avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask",
-                    "avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask",
-                    "avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask",
-                    "avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask",
-                    "avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask",
-                    "avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask",
-                    "avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask",
-                    "avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask",
-                    "avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask",
-                    "avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask",
-                    "avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask",
-                    "avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask",
-                    "avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask",
-                    "avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask",
-                    "avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask",
-                    "avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask",
-                    "avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask",
-                    "avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask",
-                    "avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask",
-                    "avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask",
-                    "avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask",
-                    "avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask",
-                    "avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask",
-                    "avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask",
-                    "avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512",
-                    "avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask",
-                    "avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask",
-                    "avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask",
-                    "avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512",
-                    "avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask",
-                    "avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask",
-                    "avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask",
-                    "avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask",
-                    "avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512",
-                    "avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask",
-                    "avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask",
-                    "avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask",
-                    "avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512",
-                    "avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask",
-                    "avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask",
-                    "avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask",
-                    "avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask",
-                    "avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask",
-                    "avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask",
                     "avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask",
                     "avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask",
-                    "avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask",
-                    "avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask",
-                    "avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask",
-                    "avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask",
-                    "avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask",
-                    "avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask",
-                    "avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask",
-                    "avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask",
-                    "avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask",
-                    "avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask",
-                    "avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask",
-                    "avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask",
-                    "avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask",
-                    "avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask",
-                    "avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask",
-                    "avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask",
-                    "avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask",
-                    "avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask",
-                    "avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask",
-                    "avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask",
-                    "avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask",
-                    "avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask",
-                    "avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask",
-                    "avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask",
-                    "avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask",
-                    "avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask",
-                    "avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask",
-                    "avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask",
-                    "avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask",
-                    "avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask",
-                    "avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask",
-                    "avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask",
-                    "avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask",
-                    "avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask",
-                    "avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask",
-                    "avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask",
                     "avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask",
-                    "avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask",
                     "avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask",
                     "avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask",
-                    "avx512.mask.cvtpd2ps.256" => "__builtin_ia32_cvtpd2ps256_mask",
                     "avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask",
                     "avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask",
                     "avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask",
@@ -8616,8 +8144,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask",
                     "avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask",
                     "avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask",
-                    "avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask",
-                    "avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask",
                     "avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask",
                     "avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask",
                     "avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask",
@@ -8628,16 +8154,10 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask",
                     "avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask",
                     "avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask",
-                    "avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask",
-                    "avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask",
-                    "avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask",
                     "avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask",
-                    "avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask",
-                    "avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask",
                     "avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask",
-                    "avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask",
                     "avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask",
                     "avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask",
                     "avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask",
@@ -8648,8 +8168,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask",
                     "avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask",
                     "avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask",
-                    "avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask",
-                    "avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask",
                     "avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask",
                     "avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask",
                     "avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask",
@@ -8660,53 +8178,9 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask",
                     "avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask",
                     "avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask",
-                    "avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask",
-                    "avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask",
-                    "avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask",
-                    "avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask",
-                    "avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask",
-                    "avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask",
-                    "avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask",
-                    "avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask",
-                    "avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask",
                     "avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask",
-                    "avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask",
-                    "avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask",
-                    "avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask",
-                    "avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask",
-                    "avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask",
-                    "avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask",
-                    "avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask",
-                    "avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask",
-                    "avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask",
-                    "avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask",
-                    "avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask",
-                    "avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask",
-                    "avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask",
-                    "avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask",
-                    "avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask",
-                    "avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask",
-                    "avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask",
-                    "avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask",
-                    "avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask",
-                    "avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask",
-                    "avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask",
-                    "avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask",
-                    "avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask",
-                    "avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask",
-                    "avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask",
-                    "avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask",
-                    "avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask",
-                    "avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask",
-                    "avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask",
-                    "avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask",
-                    "avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask",
-                    "avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask",
-                    "avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask",
-                    "avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask",
-                    "avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask",
                     "avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask",
                     "avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask",
                     "avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask",
@@ -8715,12 +8189,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask",
                     "avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask",
                     "avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask",
-                    "avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask",
-                    "avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask",
-                    "avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask",
-                    "avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask",
-                    "avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask",
-                    "avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask",
                     "avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask",
                     "avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask",
                     "avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask",
@@ -8739,226 +8207,19 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask",
-                    "avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask",
-                    "avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask",
-                    "avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask",
-                    "avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask",
-                    "avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask",
-                    "avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask",
-                    "avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask",
-                    "avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask",
-                    "avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask",
-                    "avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask",
-                    "avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask",
-                    "avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask",
-                    "avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask",
-                    "avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask",
-                    "avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask",
-                    "avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask",
-                    "avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask",
-                    "avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask",
-                    "avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask",
-                    "avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask",
-                    "avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask",
-                    "avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask",
-                    "avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask",
-                    "avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask",
-                    "avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask",
-                    "avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask",
-                    "avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask",
-                    "avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask",
-                    "avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask",
-                    "avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask",
-                    "avx512.mask.move.sd" => "__builtin_ia32_movsd_mask",
-                    "avx512.mask.move.ss" => "__builtin_ia32_movss_mask",
-                    "avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask",
-                    "avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask",
-                    "avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask",
-                    "avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask",
-                    "avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask",
-                    "avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask",
-                    "avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask",
-                    "avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask",
-                    "avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask",
-                    "avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask",
-                    "avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask",
-                    "avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask",
-                    "avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask",
-                    "avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask",
-                    "avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask",
-                    "avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask",
-                    "avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask",
-                    "avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask",
-                    "avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask",
-                    "avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask",
-                    "avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask",
-                    "avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask",
-                    "avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask",
-                    "avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask",
-                    "avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask",
-                    "avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask",
-                    "avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask",
-                    "avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask",
-                    "avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask",
-                    "avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask",
-                    "avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask",
-                    "avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask",
-                    "avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask",
-                    "avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask",
-                    "avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask",
-                    "avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask",
-                    "avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask",
-                    "avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask",
-                    "avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask",
-                    "avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask",
-                    "avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask",
-                    "avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask",
-                    "avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask",
-                    "avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask",
-                    "avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask",
-                    "avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask",
-                    "avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask",
-                    "avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask",
-                    "avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask",
-                    "avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask",
-                    "avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask",
-                    "avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask",
-                    "avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask",
-                    "avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask",
-                    "avx512.mask.paddus.b.128" => "__builtin_ia32_paddusb128_mask",
-                    "avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask",
-                    "avx512.mask.paddus.b.512" => "__builtin_ia32_paddusb512_mask",
-                    "avx512.mask.paddus.w.128" => "__builtin_ia32_paddusw128_mask",
-                    "avx512.mask.paddus.w.256" => "__builtin_ia32_paddusw256_mask",
-                    "avx512.mask.paddus.w.512" => "__builtin_ia32_paddusw512_mask",
-                    "avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask",
-                    "avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask",
-                    "avx512.mask.pavg.b.128" => "__builtin_ia32_pavgb128_mask",
-                    "avx512.mask.pavg.b.256" => "__builtin_ia32_pavgb256_mask",
-                    "avx512.mask.pavg.b.512" => "__builtin_ia32_pavgb512_mask",
-                    "avx512.mask.pavg.w.128" => "__builtin_ia32_pavgw128_mask",
-                    "avx512.mask.pavg.w.256" => "__builtin_ia32_pavgw256_mask",
-                    "avx512.mask.pavg.w.512" => "__builtin_ia32_pavgw512_mask",
-                    "avx512.mask.pbroadcast.b.gpr.128" => "__builtin_ia32_pbroadcastb128_gpr_mask",
-                    "avx512.mask.pbroadcast.b.gpr.256" => "__builtin_ia32_pbroadcastb256_gpr_mask",
-                    "avx512.mask.pbroadcast.b.gpr.512" => "__builtin_ia32_pbroadcastb512_gpr_mask",
-                    "avx512.mask.pbroadcast.d.gpr.128" => "__builtin_ia32_pbroadcastd128_gpr_mask",
-                    "avx512.mask.pbroadcast.d.gpr.256" => "__builtin_ia32_pbroadcastd256_gpr_mask",
-                    "avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask",
-                    "avx512.mask.pbroadcast.q.gpr.128" => "__builtin_ia32_pbroadcastq128_gpr_mask",
-                    "avx512.mask.pbroadcast.q.gpr.256" => "__builtin_ia32_pbroadcastq256_gpr_mask",
-                    "avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask",
-                    "avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask",
-                    "avx512.mask.pbroadcast.w.gpr.128" => "__builtin_ia32_pbroadcastw128_gpr_mask",
-                    "avx512.mask.pbroadcast.w.gpr.256" => "__builtin_ia32_pbroadcastw256_gpr_mask",
-                    "avx512.mask.pbroadcast.w.gpr.512" => "__builtin_ia32_pbroadcastw512_gpr_mask",
-                    "avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask",
-                    "avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask",
-                    "avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask",
-                    "avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask",
-                    "avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask",
-                    "avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask",
-                    "avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask",
-                    "avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask",
-                    "avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask",
-                    "avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask",
-                    "avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask",
-                    "avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask",
-                    "avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask",
-                    "avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask",
-                    "avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask",
-                    "avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask",
-                    "avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask",
-                    "avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask",
-                    "avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask",
-                    "avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask",
-                    "avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask",
-                    "avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask",
-                    "avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask",
-                    "avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask",
-                    "avx512.mask.permvar.df.256" => "__builtin_ia32_permvardf256_mask",
-                    "avx512.mask.permvar.df.512" => "__builtin_ia32_permvardf512_mask",
-                    "avx512.mask.permvar.di.256" => "__builtin_ia32_permvardi256_mask",
-                    "avx512.mask.permvar.di.512" => "__builtin_ia32_permvardi512_mask",
-                    "avx512.mask.permvar.hi.128" => "__builtin_ia32_permvarhi128_mask",
-                    "avx512.mask.permvar.hi.256" => "__builtin_ia32_permvarhi256_mask",
-                    "avx512.mask.permvar.hi.512" => "__builtin_ia32_permvarhi512_mask",
-                    "avx512.mask.permvar.qi.128" => "__builtin_ia32_permvarqi128_mask",
-                    "avx512.mask.permvar.qi.256" => "__builtin_ia32_permvarqi256_mask",
-                    "avx512.mask.permvar.qi.512" => "__builtin_ia32_permvarqi512_mask",
-                    "avx512.mask.permvar.sf.256" => "__builtin_ia32_permvarsf256_mask",
-                    "avx512.mask.permvar.sf.512" => "__builtin_ia32_permvarsf512_mask",
-                    "avx512.mask.permvar.si.256" => "__builtin_ia32_permvarsi256_mask",
-                    "avx512.mask.permvar.si.512" => "__builtin_ia32_permvarsi512_mask",
-                    "avx512.mask.pmaddubs.w.128" => "__builtin_ia32_pmaddubsw128_mask",
-                    "avx512.mask.pmaddubs.w.256" => "__builtin_ia32_pmaddubsw256_mask",
-                    "avx512.mask.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512_mask",
-                    "avx512.mask.pmaddw.d.128" => "__builtin_ia32_pmaddwd128_mask",
-                    "avx512.mask.pmaddw.d.256" => "__builtin_ia32_pmaddwd256_mask",
-                    "avx512.mask.pmaddw.d.512" => "__builtin_ia32_pmaddwd512_mask",
-                    "avx512.mask.pmaxs.b.128" => "__builtin_ia32_pmaxsb128_mask",
-                    "avx512.mask.pmaxs.b.256" => "__builtin_ia32_pmaxsb256_mask",
-                    "avx512.mask.pmaxs.b.512" => "__builtin_ia32_pmaxsb512_mask",
-                    "avx512.mask.pmaxs.d.128" => "__builtin_ia32_pmaxsd128_mask",
-                    "avx512.mask.pmaxs.d.256" => "__builtin_ia32_pmaxsd256_mask",
-                    "avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask",
-                    "avx512.mask.pmaxs.q.128" => "__builtin_ia32_pmaxsq128_mask",
-                    "avx512.mask.pmaxs.q.256" => "__builtin_ia32_pmaxsq256_mask",
-                    "avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask",
-                    "avx512.mask.pmaxs.w.128" => "__builtin_ia32_pmaxsw128_mask",
-                    "avx512.mask.pmaxs.w.256" => "__builtin_ia32_pmaxsw256_mask",
-                    "avx512.mask.pmaxs.w.512" => "__builtin_ia32_pmaxsw512_mask",
-                    "avx512.mask.pmaxu.b.128" => "__builtin_ia32_pmaxub128_mask",
-                    "avx512.mask.pmaxu.b.256" => "__builtin_ia32_pmaxub256_mask",
-                    "avx512.mask.pmaxu.b.512" => "__builtin_ia32_pmaxub512_mask",
-                    "avx512.mask.pmaxu.d.128" => "__builtin_ia32_pmaxud128_mask",
-                    "avx512.mask.pmaxu.d.256" => "__builtin_ia32_pmaxud256_mask",
-                    "avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask",
-                    "avx512.mask.pmaxu.q.128" => "__builtin_ia32_pmaxuq128_mask",
-                    "avx512.mask.pmaxu.q.256" => "__builtin_ia32_pmaxuq256_mask",
-                    "avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask",
-                    "avx512.mask.pmaxu.w.128" => "__builtin_ia32_pmaxuw128_mask",
-                    "avx512.mask.pmaxu.w.256" => "__builtin_ia32_pmaxuw256_mask",
-                    "avx512.mask.pmaxu.w.512" => "__builtin_ia32_pmaxuw512_mask",
-                    "avx512.mask.pmins.b.128" => "__builtin_ia32_pminsb128_mask",
-                    "avx512.mask.pmins.b.256" => "__builtin_ia32_pminsb256_mask",
-                    "avx512.mask.pmins.b.512" => "__builtin_ia32_pminsb512_mask",
-                    "avx512.mask.pmins.d.128" => "__builtin_ia32_pminsd128_mask",
-                    "avx512.mask.pmins.d.256" => "__builtin_ia32_pminsd256_mask",
-                    "avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask",
-                    "avx512.mask.pmins.q.128" => "__builtin_ia32_pminsq128_mask",
-                    "avx512.mask.pmins.q.256" => "__builtin_ia32_pminsq256_mask",
-                    "avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask",
-                    "avx512.mask.pmins.w.128" => "__builtin_ia32_pminsw128_mask",
-                    "avx512.mask.pmins.w.256" => "__builtin_ia32_pminsw256_mask",
-                    "avx512.mask.pmins.w.512" => "__builtin_ia32_pminsw512_mask",
-                    "avx512.mask.pminu.b.128" => "__builtin_ia32_pminub128_mask",
-                    "avx512.mask.pminu.b.256" => "__builtin_ia32_pminub256_mask",
-                    "avx512.mask.pminu.b.512" => "__builtin_ia32_pminub512_mask",
-                    "avx512.mask.pminu.d.128" => "__builtin_ia32_pminud128_mask",
-                    "avx512.mask.pminu.d.256" => "__builtin_ia32_pminud256_mask",
-                    "avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask",
-                    "avx512.mask.pminu.q.128" => "__builtin_ia32_pminuq128_mask",
-                    "avx512.mask.pminu.q.256" => "__builtin_ia32_pminuq256_mask",
-                    "avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask",
-                    "avx512.mask.pminu.w.128" => "__builtin_ia32_pminuw128_mask",
-                    "avx512.mask.pminu.w.256" => "__builtin_ia32_pminuw256_mask",
-                    "avx512.mask.pminu.w.512" => "__builtin_ia32_pminuw512_mask",
                     "avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask",
                     "avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask",
-                    "avx512.mask.pmov.db.512" => "__builtin_ia32_pmovdb512_mask",
                     "avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask",
                     "avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask",
                     "avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask",
                     "avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask",
                     "avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask",
-                    "avx512.mask.pmov.dw.512" => "__builtin_ia32_pmovdw512_mask",
                     "avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask",
                     "avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask",
                     "avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask",
@@ -8969,20 +8230,15 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask",
                     "avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask",
                     "avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask",
-                    "avx512.mask.pmov.qd.256" => "__builtin_ia32_pmovqd256_mask",
-                    "avx512.mask.pmov.qd.512" => "__builtin_ia32_pmovqd512_mask",
                     "avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask",
                     "avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask",
                     "avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask",
                     "avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask",
                     "avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask",
-                    "avx512.mask.pmov.qw.512" => "__builtin_ia32_pmovqw512_mask",
                     "avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask",
                     "avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask",
                     "avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask",
                     "avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask",
-                    "avx512.mask.pmov.wb.256" => "__builtin_ia32_pmovwb256_mask",
-                    "avx512.mask.pmov.wb.512" => "__builtin_ia32_pmovwb512_mask",
                     "avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask",
                     "avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask",
                     "avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask",
@@ -9022,24 +8278,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask",
                     "avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask",
                     "avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask",
-                    "avx512.mask.pmovsxb.d.128" => "__builtin_ia32_pmovsxbd128_mask",
-                    "avx512.mask.pmovsxb.d.256" => "__builtin_ia32_pmovsxbd256_mask",
-                    "avx512.mask.pmovsxb.d.512" => "__builtin_ia32_pmovsxbd512_mask",
-                    "avx512.mask.pmovsxb.q.128" => "__builtin_ia32_pmovsxbq128_mask",
-                    "avx512.mask.pmovsxb.q.256" => "__builtin_ia32_pmovsxbq256_mask",
-                    "avx512.mask.pmovsxb.q.512" => "__builtin_ia32_pmovsxbq512_mask",
-                    "avx512.mask.pmovsxb.w.128" => "__builtin_ia32_pmovsxbw128_mask",
-                    "avx512.mask.pmovsxb.w.256" => "__builtin_ia32_pmovsxbw256_mask",
-                    "avx512.mask.pmovsxb.w.512" => "__builtin_ia32_pmovsxbw512_mask",
-                    "avx512.mask.pmovsxd.q.128" => "__builtin_ia32_pmovsxdq128_mask",
-                    "avx512.mask.pmovsxd.q.256" => "__builtin_ia32_pmovsxdq256_mask",
-                    "avx512.mask.pmovsxd.q.512" => "__builtin_ia32_pmovsxdq512_mask",
-                    "avx512.mask.pmovsxw.d.128" => "__builtin_ia32_pmovsxwd128_mask",
-                    "avx512.mask.pmovsxw.d.256" => "__builtin_ia32_pmovsxwd256_mask",
-                    "avx512.mask.pmovsxw.d.512" => "__builtin_ia32_pmovsxwd512_mask",
-                    "avx512.mask.pmovsxw.q.128" => "__builtin_ia32_pmovsxwq128_mask",
-                    "avx512.mask.pmovsxw.q.256" => "__builtin_ia32_pmovsxwq256_mask",
-                    "avx512.mask.pmovsxw.q.512" => "__builtin_ia32_pmovsxwq512_mask",
                     "avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask",
                     "avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask",
                     "avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask",
@@ -9076,191 +8314,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask",
                     "avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask",
                     "avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask",
-                    "avx512.mask.pmovzxb.d.128" => "__builtin_ia32_pmovzxbd128_mask",
-                    "avx512.mask.pmovzxb.d.256" => "__builtin_ia32_pmovzxbd256_mask",
-                    "avx512.mask.pmovzxb.d.512" => "__builtin_ia32_pmovzxbd512_mask",
-                    "avx512.mask.pmovzxb.q.128" => "__builtin_ia32_pmovzxbq128_mask",
-                    "avx512.mask.pmovzxb.q.256" => "__builtin_ia32_pmovzxbq256_mask",
-                    "avx512.mask.pmovzxb.q.512" => "__builtin_ia32_pmovzxbq512_mask",
-                    "avx512.mask.pmovzxb.w.128" => "__builtin_ia32_pmovzxbw128_mask",
-                    "avx512.mask.pmovzxb.w.256" => "__builtin_ia32_pmovzxbw256_mask",
-                    "avx512.mask.pmovzxb.w.512" => "__builtin_ia32_pmovzxbw512_mask",
-                    "avx512.mask.pmovzxd.q.128" => "__builtin_ia32_pmovzxdq128_mask",
-                    "avx512.mask.pmovzxd.q.256" => "__builtin_ia32_pmovzxdq256_mask",
-                    "avx512.mask.pmovzxd.q.512" => "__builtin_ia32_pmovzxdq512_mask",
-                    "avx512.mask.pmovzxw.d.128" => "__builtin_ia32_pmovzxwd128_mask",
-                    "avx512.mask.pmovzxw.d.256" => "__builtin_ia32_pmovzxwd256_mask",
-                    "avx512.mask.pmovzxw.d.512" => "__builtin_ia32_pmovzxwd512_mask",
-                    "avx512.mask.pmovzxw.q.128" => "__builtin_ia32_pmovzxwq128_mask",
-                    "avx512.mask.pmovzxw.q.256" => "__builtin_ia32_pmovzxwq256_mask",
-                    "avx512.mask.pmovzxw.q.512" => "__builtin_ia32_pmovzxwq512_mask",
-                    "avx512.mask.pmul.dq.128" => "__builtin_ia32_pmuldq128_mask",
-                    "avx512.mask.pmul.dq.256" => "__builtin_ia32_pmuldq256_mask",
-                    "avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask",
-                    "avx512.mask.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128_mask",
-                    "avx512.mask.pmul.hr.sw.256" => "__builtin_ia32_pmulhrsw256_mask",
-                    "avx512.mask.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512_mask",
-                    "avx512.mask.pmulh.w.128" => "__builtin_ia32_pmulhw128_mask",
-                    "avx512.mask.pmulh.w.256" => "__builtin_ia32_pmulhw256_mask",
-                    "avx512.mask.pmulh.w.512" => "__builtin_ia32_pmulhw512_mask",
-                    "avx512.mask.pmulhu.w.128" => "__builtin_ia32_pmulhuw128_mask",
-                    "avx512.mask.pmulhu.w.256" => "__builtin_ia32_pmulhuw256_mask",
-                    "avx512.mask.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask",
-                    "avx512.mask.pmull.d.128" => "__builtin_ia32_pmulld128_mask",
-                    "avx512.mask.pmull.d.256" => "__builtin_ia32_pmulld256_mask",
-                    "avx512.mask.pmull.d.512" => "__builtin_ia32_pmulld512_mask",
-                    "avx512.mask.pmull.q.128" => "__builtin_ia32_pmullq128_mask",
-                    "avx512.mask.pmull.q.256" => "__builtin_ia32_pmullq256_mask",
-                    "avx512.mask.pmull.q.512" => "__builtin_ia32_pmullq512_mask",
-                    "avx512.mask.pmull.w.128" => "__builtin_ia32_pmullw128_mask",
-                    "avx512.mask.pmull.w.256" => "__builtin_ia32_pmullw256_mask",
-                    "avx512.mask.pmull.w.512" => "__builtin_ia32_pmullw512_mask",
-                    "avx512.mask.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128_mask",
-                    "avx512.mask.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256_mask",
-                    "avx512.mask.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512_mask",
-                    "avx512.mask.pmulu.dq.128" => "__builtin_ia32_pmuludq128_mask",
-                    "avx512.mask.pmulu.dq.256" => "__builtin_ia32_pmuludq256_mask",
-                    "avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask",
-                    "avx512.mask.prol.d.128" => "__builtin_ia32_prold128_mask",
-                    "avx512.mask.prol.d.256" => "__builtin_ia32_prold256_mask",
-                    "avx512.mask.prol.d.512" => "__builtin_ia32_prold512_mask",
-                    "avx512.mask.prol.q.128" => "__builtin_ia32_prolq128_mask",
-                    "avx512.mask.prol.q.256" => "__builtin_ia32_prolq256_mask",
-                    "avx512.mask.prol.q.512" => "__builtin_ia32_prolq512_mask",
-                    "avx512.mask.prolv.d.128" => "__builtin_ia32_prolvd128_mask",
-                    "avx512.mask.prolv.d.256" => "__builtin_ia32_prolvd256_mask",
-                    "avx512.mask.prolv.d.512" => "__builtin_ia32_prolvd512_mask",
-                    "avx512.mask.prolv.q.128" => "__builtin_ia32_prolvq128_mask",
-                    "avx512.mask.prolv.q.256" => "__builtin_ia32_prolvq256_mask",
-                    "avx512.mask.prolv.q.512" => "__builtin_ia32_prolvq512_mask",
-                    "avx512.mask.pror.d.128" => "__builtin_ia32_prord128_mask",
-                    "avx512.mask.pror.d.256" => "__builtin_ia32_prord256_mask",
-                    "avx512.mask.pror.d.512" => "__builtin_ia32_prord512_mask",
-                    "avx512.mask.pror.q.128" => "__builtin_ia32_prorq128_mask",
-                    "avx512.mask.pror.q.256" => "__builtin_ia32_prorq256_mask",
-                    "avx512.mask.pror.q.512" => "__builtin_ia32_prorq512_mask",
-                    "avx512.mask.prorv.d.128" => "__builtin_ia32_prorvd128_mask",
-                    "avx512.mask.prorv.d.256" => "__builtin_ia32_prorvd256_mask",
-                    "avx512.mask.prorv.d.512" => "__builtin_ia32_prorvd512_mask",
-                    "avx512.mask.prorv.q.128" => "__builtin_ia32_prorvq128_mask",
-                    "avx512.mask.prorv.q.256" => "__builtin_ia32_prorvq256_mask",
-                    "avx512.mask.prorv.q.512" => "__builtin_ia32_prorvq512_mask",
-                    "avx512.mask.pshuf.b.128" => "__builtin_ia32_pshufb128_mask",
-                    "avx512.mask.pshuf.b.256" => "__builtin_ia32_pshufb256_mask",
-                    "avx512.mask.pshuf.b.512" => "__builtin_ia32_pshufb512_mask",
-                    "avx512.mask.psll.d" => "__builtin_ia32_pslld512_mask",
-                    "avx512.mask.psll.d.128" => "__builtin_ia32_pslld128_mask",
-                    "avx512.mask.psll.d.256" => "__builtin_ia32_pslld256_mask",
-                    "avx512.mask.psll.di.128" => "__builtin_ia32_pslldi128_mask",
-                    "avx512.mask.psll.di.256" => "__builtin_ia32_pslldi256_mask",
-                    "avx512.mask.psll.di.512" => "__builtin_ia32_pslldi512_mask",
-                    "avx512.mask.psll.q" => "__builtin_ia32_psllq512_mask",
-                    "avx512.mask.psll.q.128" => "__builtin_ia32_psllq128_mask",
-                    "avx512.mask.psll.q.256" => "__builtin_ia32_psllq256_mask",
-                    "avx512.mask.psll.qi.128" => "__builtin_ia32_psllqi128_mask",
-                    "avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask",
-                    "avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask",
-                    "avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask",
-                    "avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask",
-                    "avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask",
-                    "avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask",
-                    "avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask",
-                    "avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask",
-                    "avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask",
-                    "avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask",
-                    "avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask",
-                    "avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask",
-                    "avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask",
-                    "avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask",
-                    "avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask",
-                    "avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask",
-                    "avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask",
-                    "avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask",
-                    "avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask",
-                    "avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask",
-                    "avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask",
-                    "avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask",
-                    "avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask",
-                    "avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask",
-                    "avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask",
-                    "avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask",
-                    "avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask",
-                    "avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask",
-                    "avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask",
-                    "avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask",
-                    "avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask",
-                    "avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask",
-                    "avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask",
-                    "avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask",
-                    "avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask",
-                    "avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask",
-                    "avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask",
-                    "avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask",
-                    "avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask",
-                    "avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask",
-                    "avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask",
-                    "avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask",
-                    "avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask",
-                    "avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask",
-                    "avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask",
-                    "avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask",
-                    "avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask",
-                    "avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask",
-                    "avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask",
-                    "avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask",
-                    "avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask",
-                    "avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask",
-                    "avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask",
-                    "avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask",
-                    "avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask",
-                    "avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask",
-                    "avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask",
-                    "avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask",
-                    "avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask",
-                    "avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask",
-                    "avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask",
-                    "avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask",
-                    "avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask",
-                    "avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask",
-                    "avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask",
-                    "avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask",
-                    "avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask",
-                    "avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask",
-                    "avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask",
-                    "avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask",
-                    "avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask",
-                    "avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask",
-                    "avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask",
-                    "avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask",
-                    "avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask",
-                    "avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask",
-                    "avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask",
-                    "avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask",
-                    "avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask",
-                    "avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask",
-                    "avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask",
-                    "avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask",
-                    "avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask",
-                    "avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask",
-                    "avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask",
-                    "avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask",
-                    "avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask",
-                    "avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask",
-                    "avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask",
-                    "avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask",
-                    "avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask",
-                    "avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask",
-                    "avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask",
-                    "avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask",
-                    "avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask",
-                    "avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask",
-                    "avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask",
-                    "avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask",
-                    "avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask",
-                    "avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask",
-                    "avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask",
-                    "avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512",
-                    "avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512",
                     "avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask",
                     "avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask",
                     "avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask",
@@ -9293,181 +8346,11 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask",
-                    "avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask",
-                    "avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask",
-                    "avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask",
-                    "avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask",
-                    "avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask",
-                    "avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask",
-                    "avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask",
-                    "avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask",
-                    "avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask",
-                    "avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask",
-                    "avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask",
-                    "avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask",
-                    "avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask",
-                    "avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask",
-                    "avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask",
-                    "avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask",
-                    "avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
-                    "avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask",
-                    "avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask",
-                    "avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
-                    // [INVALID CONVERSION]: "avx512.mask.sqrt.sd" => "__builtin_ia32_sqrtsd_round_mask",
-                    // [INVALID CONVERSION]: "avx512.mask.sqrt.ss" => "__builtin_ia32_sqrtss_round_mask",
-                    "avx512.mask.store.ss" => "__builtin_ia32_storess_mask",
-                    "avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask",
-                    "avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask",
-                    "avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask",
-                    "avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask",
-                    "avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask",
-                    "avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask",
-                    "avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask",
-                    "avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask",
-                    "avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask",
-                    "avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask",
                     // [INVALID CONVERSION]: "avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask",
                     // [INVALID CONVERSION]: "avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask",
-                    "avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask",
-                    "avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask",
-                    "avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask",
-                    "avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask",
-                    "avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask",
-                    "avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask",
-                    "avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask",
-                    "avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask",
-                    "avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask",
                     "avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask",
                     "avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask",
                     "avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask",
-                    "avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask",
-                    "avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask",
-                    "avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask",
-                    "avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask",
-                    "avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask",
-                    "avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask",
-                    "avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask",
-                    "avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask",
-                    "avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask",
-                    "avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask",
-                    "avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask",
-                    "avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask",
-                    "avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask",
-                    "avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask",
-                    "avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
-                    "avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask",
-                    "avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask",
-                    "avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
-                    "avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask",
-                    "avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask",
-                    "avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask",
-                    "avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask",
-                    "avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
-                    "avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask",
-                    "avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask",
-                    "avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
-                    "avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask",
-                    "avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask",
-                    "avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
-                    "avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask",
-                    "avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask",
-                    "avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
-                    "avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask",
-                    "avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask",
-                    "avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
-                    "avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask",
-                    "avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask",
-                    "avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
-                    "avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask",
-                    "avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask",
-                    "avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask",
-                    "avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask",
-                    "avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask",
-                    "avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask",
-                    "avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask",
-                    "avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask",
-                    "avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask",
-                    "avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask",
-                    "avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask",
-                    "avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask",
-                    "avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask",
-                    "avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask",
-                    "avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask",
-                    "avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask",
-                    "avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask",
-                    "avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask",
-                    "avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask",
-                    "avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask",
-                    "avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask",
-                    "avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask",
-                    "avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask",
-                    "avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask",
-                    "avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask",
-                    "avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
-                    "avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
-                    "avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask",
-                    "avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask",
-                    "avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask",
-                    "avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask",
-                    "avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask",
-                    "avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask",
-                    "avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask",
-                    "avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask",
-                    "avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask",
-                    "avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
-                    "avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask",
-                    "avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask",
-                    "avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
-                    "avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask",
-                    "avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask",
-                    "avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask",
-                    "avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask",
-                    "avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask",
-                    "avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask",
-                    "avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask",
-                    "avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask",
-                    "avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask",
-                    "avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask",
-                    "avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask",
-                    "avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask",
-                    "avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask",
-                    "avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask",
-                    "avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask",
-                    "avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask",
-                    "avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask",
-                    "avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask",
-                    "avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3",
-                    "avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3",
-                    "avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3",
-                    "avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3",
-                    "avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3",
-                    "avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3",
-                    "avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3",
-                    "avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3",
-                    "avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3",
-                    "avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3",
-                    "avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3",
-                    "avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3",
-                    "avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3",
-                    "avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3",
-                    "avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3",
-                    "avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3",
-                    "avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3",
-                    "avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3",
-                    "avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3",
-                    "avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3",
-                    "avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3",
-                    "avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3",
-                    "avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3",
-                    "avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3",
-                    "avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3",
-                    "avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3",
-                    "avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3",
-                    "avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3",
-                    "avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3",
-                    "avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3",
-                    "avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3",
-                    "avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3",
                     "avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz",
                     "avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz",
                     "avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz",
@@ -9476,55 +8359,10 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz",
                     "avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz",
                     "avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz",
-                    "avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz",
-                    "avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz",
-                    "avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz",
-                    "avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz",
-                    "avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz",
-                    "avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz",
-                    "avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz",
-                    "avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz",
-                    "avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz",
-                    "avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz",
-                    "avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz",
-                    "avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz",
-                    "avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz",
-                    "avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz",
-                    "avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz",
-                    "avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz",
-                    "avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz",
-                    "avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz",
-                    "avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz",
-                    "avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz",
-                    "avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz",
-                    "avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz",
-                    "avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz",
-                    "avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz",
-                    "avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz",
-                    "avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz",
-                    "avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz",
-                    "avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz",
-                    "avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz",
-                    "avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz",
-                    "avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz",
-                    "avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz",
-                    "avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz",
-                    "avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz",
-                    "avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz",
-                    "avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz",
-                    "avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz",
-                    "avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz",
-                    "avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz",
-                    "avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz",
-                    "avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz",
-                    "avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz",
-                    "avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz",
-                    "avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz",
                     "avx512.max.pd.512" => "__builtin_ia32_maxpd512",
                     "avx512.max.ps.512" => "__builtin_ia32_maxps512",
                     "avx512.min.pd.512" => "__builtin_ia32_minpd512",
                     "avx512.min.ps.512" => "__builtin_ia32_minps512",
-                    "avx512.movntdqa" => "__builtin_ia32_movntdqa512",
                     "avx512.mul.pd.512" => "__builtin_ia32_mulpd512",
                     "avx512.mul.ps.512" => "__builtin_ia32_mulps512",
                     "avx512.packssdw.512" => "__builtin_ia32_packssdw512",
@@ -9533,8 +8371,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.packuswb.512" => "__builtin_ia32_packuswb512",
                     "avx512.pavg.b.512" => "__builtin_ia32_pavgb512",
                     "avx512.pavg.w.512" => "__builtin_ia32_pavgw512",
-                    "avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512",
-                    "avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512",
                     "avx512.permvar.df.256" => "__builtin_ia32_permvardf256",
                     "avx512.permvar.df.512" => "__builtin_ia32_permvardf512",
                     "avx512.permvar.di.256" => "__builtin_ia32_permvardi256",
@@ -9549,11 +8385,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.permvar.si.512" => "__builtin_ia32_permvarsi512",
                     "avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512",
                     "avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512",
-                    "avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512",
-                    "avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512",
-                    "avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512",
-                    "avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512",
-                    "avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512",
                     "avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512",
                     "avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512",
                     "avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512",
@@ -9563,8 +8394,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.psad.bw.512" => "__builtin_ia32_psadbw512",
                     "avx512.pshuf.b.512" => "__builtin_ia32_pshufb512",
                     "avx512.psll.d.512" => "__builtin_ia32_pslld512",
-                    "avx512.psll.dq" => "__builtin_ia32_pslldqi512",
-                    "avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift",
                     "avx512.psll.q.512" => "__builtin_ia32_psllq512",
                     "avx512.psll.w.512" => "__builtin_ia32_psllw512",
                     "avx512.pslli.d.512" => "__builtin_ia32_pslldi512",
@@ -9593,8 +8422,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.psrav.w.256" => "__builtin_ia32_psrav16hi",
                     "avx512.psrav.w.512" => "__builtin_ia32_psrav32hi",
                     "avx512.psrl.d.512" => "__builtin_ia32_psrld512",
-                    "avx512.psrl.dq" => "__builtin_ia32_psrldqi512",
-                    "avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift",
                     "avx512.psrl.q.512" => "__builtin_ia32_psrlq512",
                     "avx512.psrl.w.512" => "__builtin_ia32_psrlw512",
                     "avx512.psrli.d.512" => "__builtin_ia32_psrldi512",
@@ -9611,30 +8438,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128",
                     "avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256",
                     "avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512",
-                    "avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128",
-                    "avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256",
-                    "avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512",
-                    "avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128",
-                    "avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256",
-                    "avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512",
-                    "avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128",
-                    "avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256",
-                    "avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512",
-                    "avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128",
-                    "avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256",
-                    "avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512",
-                    "avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128",
-                    "avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256",
-                    "avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512",
-                    "avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128",
-                    "avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256",
-                    "avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512",
-                    "avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128",
-                    "avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256",
-                    "avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512",
-                    "avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128",
-                    "avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256",
-                    "avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512",
                     "avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask",
                     "avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask",
                     "avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask",
@@ -9643,14 +8446,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask",
                     "avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask",
                     "avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask",
-                    "avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask",
-                    "avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask",
-                    "avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask",
-                    // [DUPLICATE]: "avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask",
-                    "avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask",
-                    // [DUPLICATE]: "avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask",
-                    "avx512.rndscale.sd" => "__builtin_ia32_rndscalesd",
-                    "avx512.rndscale.ss" => "__builtin_ia32_rndscaless",
                     "avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask",
                     "avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask",
                     "avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask",
@@ -9659,50 +8454,8 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask",
                     "avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask",
                     "avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask",
-                    "avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask",
-                    "avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask",
-                    "avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask",
-                    // [DUPLICATE]: "avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask",
-                    "avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask",
-                    // [DUPLICATE]: "avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask",
-                    "avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df",
-                    "avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si",
-                    "avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di",
-                    "avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf",
-                    "avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df",
-                    "avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si",
-                    "avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di",
-                    "avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf",
-                    "avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df",
-                    "avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di",
-                    "avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df",
-                    "avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di",
-                    "avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf",
-                    "avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si",
-                    "avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf",
-                    "avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si",
-                    "avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd",
-                    "avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps",
-                    "avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd",
-                    "avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps",
-                    "avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df",
-                    "avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di",
-                    "avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df",
-                    "avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di",
-                    "avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf",
-                    "avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si",
-                    "avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf",
-                    "avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si",
-                    "avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
-                    "avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
-                    "avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd",
-                    "avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss",
                     "avx512.sub.pd.512" => "__builtin_ia32_subpd512",
                     "avx512.sub.ps.512" => "__builtin_ia32_subps512",
-                    "avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512",
-                    "avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512",
-                    "avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512",
-                    "avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512",
                     "avx512.vcomi.sd" => "__builtin_ia32_vcomisd",
                     "avx512.vcomi.ss" => "__builtin_ia32_vcomiss",
                     "avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32",
@@ -9928,50 +8681,10 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "flags.read.u64" => "__builtin_ia32_readeflags_u64",
                     "flags.write.u32" => "__builtin_ia32_writeeflags_u32",
                     "flags.write.u64" => "__builtin_ia32_writeeflags_u64",
-                    "fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
-                    "fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
-                    "fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
-                    "fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
-                    "fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask",
-                    "fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask",
-                    "fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask",
-                    "fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask",
-                    "fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
-                    "fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
-                    "fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
-                    "fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
-                    "fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd",
-                    "fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256",
-                    "fma.vfmadd.ps" => "__builtin_ia32_vfmaddps",
-                    "fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256",
-                    "fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd",
-                    "fma.vfmadd.ss" => "__builtin_ia32_vfmaddss",
                     "fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd",
                     "fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256",
                     "fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps",
                     "fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256",
-                    "fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd",
-                    "fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256",
-                    "fma.vfmsub.ps" => "__builtin_ia32_vfmsubps",
-                    "fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256",
-                    "fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd",
-                    "fma.vfmsub.ss" => "__builtin_ia32_vfmsubss",
-                    "fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd",
-                    "fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256",
-                    "fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps",
-                    "fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256",
-                    "fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd",
-                    "fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256",
-                    "fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps",
-                    "fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256",
-                    "fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd",
-                    "fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss",
-                    "fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd",
-                    "fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256",
-                    "fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps",
-                    "fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256",
-                    "fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd",
-                    "fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss",
                     "fxrstor" => "__builtin_ia32_fxrstor",
                     "fxrstor64" => "__builtin_ia32_fxrstor64",
                     "fxsave" => "__builtin_ia32_fxsave",
@@ -9988,7 +8701,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "lwpval32" => "__builtin_ia32_lwpval32",
                     "lwpval64" => "__builtin_ia32_lwpval64",
                     "mmx.emms" => "__builtin_ia32_emms",
-                    "mmx.femms" => "__builtin_ia32_femms",
                     "monitorx" => "__builtin_ia32_monitorx",
                     "movdir64b" => "__builtin_ia32_movdir64b",
                     "movrsdi" => "__builtin_ia32_movrsdi",
@@ -10013,7 +8725,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "rdsspd" => "__builtin_ia32_rdsspd",
                     "rdsspq" => "__builtin_ia32_rdsspq",
                     "rdtsc" => "__builtin_ia32_rdtsc",
-                    "rdtscp" => "__builtin_ia32_rdtscp",
                     "rstorssp" => "__builtin_ia32_rstorssp",
                     "saveprevssp" => "__builtin_ia32_saveprevssp",
                     "senduipi" => "__builtin_ia32_senduipi",
@@ -10027,8 +8738,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sha256msg2" => "__builtin_ia32_sha256msg2",
                     "sha256rnds2" => "__builtin_ia32_sha256rnds2",
                     "slwpcb" => "__builtin_ia32_slwpcb",
-                    "sse.add.ss" => "__builtin_ia32_addss",
-                    "sse.cmp.ps" => "__builtin_ia32_cmpps",
                     "sse.cmp.ss" => "__builtin_ia32_cmpss",
                     "sse.comieq.ss" => "__builtin_ia32_comieq",
                     "sse.comige.ss" => "__builtin_ia32_comige",
@@ -10036,37 +8745,27 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse.comile.ss" => "__builtin_ia32_comile",
                     "sse.comilt.ss" => "__builtin_ia32_comilt",
                     "sse.comineq.ss" => "__builtin_ia32_comineq",
-                    "sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss",
-                    "sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss",
                     "sse.cvtss2si" => "__builtin_ia32_cvtss2si",
                     "sse.cvtss2si64" => "__builtin_ia32_cvtss2si64",
                     "sse.cvttss2si" => "__builtin_ia32_cvttss2si",
                     "sse.cvttss2si64" => "__builtin_ia32_cvttss2si64",
-                    "sse.div.ss" => "__builtin_ia32_divss",
                     "sse.max.ps" => "__builtin_ia32_maxps",
                     "sse.max.ss" => "__builtin_ia32_maxss",
                     "sse.min.ps" => "__builtin_ia32_minps",
                     "sse.min.ss" => "__builtin_ia32_minss",
                     "sse.movmsk.ps" => "__builtin_ia32_movmskps",
-                    "sse.mul.ss" => "__builtin_ia32_mulss",
                     "sse.rcp.ps" => "__builtin_ia32_rcpps",
                     "sse.rcp.ss" => "__builtin_ia32_rcpss",
                     "sse.rsqrt.ps" => "__builtin_ia32_rsqrtps",
                     "sse.rsqrt.ss" => "__builtin_ia32_rsqrtss",
                     "sse.sfence" => "__builtin_ia32_sfence",
-                    "sse.sqrt.ps" => "__builtin_ia32_sqrtps",
-                    "sse.sqrt.ss" => "__builtin_ia32_sqrtss",
-                    "sse.storeu.ps" => "__builtin_ia32_storeups",
-                    "sse.sub.ss" => "__builtin_ia32_subss",
                     "sse.ucomieq.ss" => "__builtin_ia32_ucomieq",
                     "sse.ucomige.ss" => "__builtin_ia32_ucomige",
                     "sse.ucomigt.ss" => "__builtin_ia32_ucomigt",
                     "sse.ucomile.ss" => "__builtin_ia32_ucomile",
                     "sse.ucomilt.ss" => "__builtin_ia32_ucomilt",
                     "sse.ucomineq.ss" => "__builtin_ia32_ucomineq",
-                    "sse2.add.sd" => "__builtin_ia32_addsd",
                     "sse2.clflush" => "__builtin_ia32_clflush",
-                    "sse2.cmp.pd" => "__builtin_ia32_cmppd",
                     "sse2.cmp.sd" => "__builtin_ia32_cmpsd",
                     "sse2.comieq.sd" => "__builtin_ia32_comisdeq",
                     "sse2.comige.sd" => "__builtin_ia32_comisdge",
@@ -10074,23 +8773,16 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse2.comile.sd" => "__builtin_ia32_comisdle",
                     "sse2.comilt.sd" => "__builtin_ia32_comisdlt",
                     "sse2.comineq.sd" => "__builtin_ia32_comisdneq",
-                    "sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd",
-                    "sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps",
                     "sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq",
                     "sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps",
                     "sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq",
-                    "sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd",
                     "sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si",
                     "sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64",
                     "sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss",
-                    "sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd",
-                    "sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd",
-                    "sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd",
                     "sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq",
                     "sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq",
                     "sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si",
                     "sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64",
-                    "sse2.div.sd" => "__builtin_ia32_divsd",
                     "sse2.lfence" => "__builtin_ia32_lfence",
                     "sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu",
                     "sse2.max.pd" => "__builtin_ia32_maxpd",
@@ -10099,33 +8791,18 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse2.min.pd" => "__builtin_ia32_minpd",
                     "sse2.min.sd" => "__builtin_ia32_minsd",
                     "sse2.movmsk.pd" => "__builtin_ia32_movmskpd",
-                    "sse2.mul.sd" => "__builtin_ia32_mulsd",
                     "sse2.packssdw.128" => "__builtin_ia32_packssdw128",
                     "sse2.packsswb.128" => "__builtin_ia32_packsswb128",
                     "sse2.packuswb.128" => "__builtin_ia32_packuswb128",
-                    "sse2.padds.b" => "__builtin_ia32_paddsb128",
-                    "sse2.padds.w" => "__builtin_ia32_paddsw128",
-                    "sse2.paddus.b" => "__builtin_ia32_paddusb128",
-                    "sse2.paddus.w" => "__builtin_ia32_paddusw128",
                     "sse2.pause" => "__builtin_ia32_pause",
                     "sse2.pavg.b" => "__builtin_ia32_pavgb128",
                     "sse2.pavg.w" => "__builtin_ia32_pavgw128",
                     "sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128",
-                    "sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128",
-                    "sse2.pmaxu.b" => "__builtin_ia32_pmaxub128",
-                    "sse2.pmins.w" => "__builtin_ia32_pminsw128",
-                    "sse2.pminu.b" => "__builtin_ia32_pminub128",
                     "sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128",
                     "sse2.pmulh.w" => "__builtin_ia32_pmulhw128",
                     "sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128",
-                    "sse2.pmulu.dq" => "__builtin_ia32_pmuludq128",
                     "sse2.psad.bw" => "__builtin_ia32_psadbw128",
-                    "sse2.pshuf.d" => "__builtin_ia32_pshufd",
-                    "sse2.pshufh.w" => "__builtin_ia32_pshufhw",
-                    "sse2.pshufl.w" => "__builtin_ia32_pshuflw",
                     "sse2.psll.d" => "__builtin_ia32_pslld128",
-                    "sse2.psll.dq" => "__builtin_ia32_pslldqi128",
-                    "sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift",
                     "sse2.psll.q" => "__builtin_ia32_psllq128",
                     "sse2.psll.w" => "__builtin_ia32_psllw128",
                     "sse2.pslli.d" => "__builtin_ia32_pslldi128",
@@ -10136,23 +8813,11 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse2.psrai.d" => "__builtin_ia32_psradi128",
                     "sse2.psrai.w" => "__builtin_ia32_psrawi128",
                     "sse2.psrl.d" => "__builtin_ia32_psrld128",
-                    "sse2.psrl.dq" => "__builtin_ia32_psrldqi128",
-                    "sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift",
                     "sse2.psrl.q" => "__builtin_ia32_psrlq128",
                     "sse2.psrl.w" => "__builtin_ia32_psrlw128",
                     "sse2.psrli.d" => "__builtin_ia32_psrldi128",
                     "sse2.psrli.q" => "__builtin_ia32_psrlqi128",
                     "sse2.psrli.w" => "__builtin_ia32_psrlwi128",
-                    "sse2.psubs.b" => "__builtin_ia32_psubsb128",
-                    "sse2.psubs.w" => "__builtin_ia32_psubsw128",
-                    "sse2.psubus.b" => "__builtin_ia32_psubusb128",
-                    "sse2.psubus.w" => "__builtin_ia32_psubusw128",
-                    "sse2.sqrt.pd" => "__builtin_ia32_sqrtpd",
-                    "sse2.sqrt.sd" => "__builtin_ia32_sqrtsd",
-                    "sse2.storel.dq" => "__builtin_ia32_storelv4si",
-                    "sse2.storeu.dq" => "__builtin_ia32_storedqu",
-                    "sse2.storeu.pd" => "__builtin_ia32_storeupd",
-                    "sse2.sub.sd" => "__builtin_ia32_subsd",
                     "sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq",
                     "sse2.ucomige.sd" => "__builtin_ia32_ucomisdge",
                     "sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt",
@@ -10168,48 +8833,18 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse3.ldu.dq" => "__builtin_ia32_lddqu",
                     "sse3.monitor" => "__builtin_ia32_monitor",
                     "sse3.mwait" => "__builtin_ia32_mwait",
-                    "sse41.blendpd" => "__builtin_ia32_blendpd",
-                    "sse41.blendps" => "__builtin_ia32_blendps",
                     "sse41.blendvpd" => "__builtin_ia32_blendvpd",
                     "sse41.blendvps" => "__builtin_ia32_blendvps",
                     "sse41.dppd" => "__builtin_ia32_dppd",
                     "sse41.dpps" => "__builtin_ia32_dpps",
-                    "sse41.extractps" => "__builtin_ia32_extractps128",
                     "sse41.insertps" => "__builtin_ia32_insertps128",
-                    "sse41.movntdqa" => "__builtin_ia32_movntdqa",
                     "sse41.mpsadbw" => "__builtin_ia32_mpsadbw128",
                     "sse41.packusdw" => "__builtin_ia32_packusdw128",
                     "sse41.pblendvb" => "__builtin_ia32_pblendvb128",
-                    "sse41.pblendw" => "__builtin_ia32_pblendw128",
                     "sse41.phminposuw" => "__builtin_ia32_phminposuw128",
-                    "sse41.pmaxsb" => "__builtin_ia32_pmaxsb128",
-                    "sse41.pmaxsd" => "__builtin_ia32_pmaxsd128",
-                    "sse41.pmaxud" => "__builtin_ia32_pmaxud128",
-                    "sse41.pmaxuw" => "__builtin_ia32_pmaxuw128",
-                    "sse41.pminsb" => "__builtin_ia32_pminsb128",
-                    "sse41.pminsd" => "__builtin_ia32_pminsd128",
-                    "sse41.pminud" => "__builtin_ia32_pminud128",
-                    "sse41.pminuw" => "__builtin_ia32_pminuw128",
-                    "sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128",
-                    "sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128",
-                    "sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128",
-                    "sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128",
-                    "sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128",
-                    "sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128",
-                    "sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128",
-                    "sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128",
-                    "sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128",
-                    "sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128",
-                    "sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128",
-                    "sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128",
-                    "sse41.pmuldq" => "__builtin_ia32_pmuldq128",
                     "sse41.ptestc" => "__builtin_ia32_ptestc128",
                     "sse41.ptestnzc" => "__builtin_ia32_ptestnzc128",
                     "sse41.ptestz" => "__builtin_ia32_ptestz128",
-                    "sse41.round.pd" => "__builtin_ia32_roundpd",
-                    "sse41.round.ps" => "__builtin_ia32_roundps",
-                    "sse41.round.sd" => "__builtin_ia32_roundsd",
-                    "sse41.round.ss" => "__builtin_ia32_roundss",
                     "sse42.crc32.32.16" => "__builtin_ia32_crc32hi",
                     "sse42.crc32.32.32" => "__builtin_ia32_crc32si",
                     "sse42.crc32.32.8" => "__builtin_ia32_crc32qi",
@@ -10232,11 +8867,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "sse4a.extrqi" => "__builtin_ia32_extrqi",
                     "sse4a.insertq" => "__builtin_ia32_insertq",
                     "sse4a.insertqi" => "__builtin_ia32_insertqi",
-                    "sse4a.movnt.sd" => "__builtin_ia32_movntsd",
-                    "sse4a.movnt.ss" => "__builtin_ia32_movntss",
-                    "ssse3.pabs.b.128" => "__builtin_ia32_pabsb128",
-                    "ssse3.pabs.d.128" => "__builtin_ia32_pabsd128",
-                    "ssse3.pabs.w.128" => "__builtin_ia32_pabsw128",
                     "ssse3.phadd.d.128" => "__builtin_ia32_phaddd128",
                     "ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128",
                     "ssse3.phadd.w.128" => "__builtin_ia32_phaddw128",
@@ -10251,12 +8881,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "ssse3.psign.w.128" => "__builtin_ia32_psignw128",
                     "sttilecfg" => "__builtin_ia32_tile_storeconfig",
                     "stui" => "__builtin_ia32_stui",
-                    "subborrow.u32" => "__builtin_ia32_subborrow_u32",
-                    "subborrow.u64" => "__builtin_ia32_subborrow_u64",
-                    "t2rpntlvwz0rs" => "__builtin_ia32_t2rpntlvwz0rs",
-                    "t2rpntlvwz0rst1" => "__builtin_ia32_t2rpntlvwz0rst1",
-                    "t2rpntlvwz1rs" => "__builtin_ia32_t2rpntlvwz1rs",
-                    "t2rpntlvwz1rst1" => "__builtin_ia32_t2rpntlvwz1rst1",
                     "tbm.bextri.u32" => "__builtin_ia32_bextri_u32",
                     "tbm.bextri.u64" => "__builtin_ia32_bextri_u64",
                     "tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps",
@@ -10265,14 +8889,19 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal",
                     "tcvtrowd2ps" => "__builtin_ia32_tcvtrowd2ps",
                     "tcvtrowd2ps.internal" => "__builtin_ia32_tcvtrowd2ps_internal",
+                    "tcvtrowd2psi" => "__builtin_ia32_tcvtrowd2psi",
                     "tcvtrowps2bf16h" => "__builtin_ia32_tcvtrowps2bf16h",
                     "tcvtrowps2bf16h.internal" => "__builtin_ia32_tcvtrowps2bf16h_internal",
+                    "tcvtrowps2bf16hi" => "__builtin_ia32_tcvtrowps2bf16hi",
                     "tcvtrowps2bf16l" => "__builtin_ia32_tcvtrowps2bf16l",
                     "tcvtrowps2bf16l.internal" => "__builtin_ia32_tcvtrowps2bf16l_internal",
+                    "tcvtrowps2bf16li" => "__builtin_ia32_tcvtrowps2bf16li",
                     "tcvtrowps2phh" => "__builtin_ia32_tcvtrowps2phh",
                     "tcvtrowps2phh.internal" => "__builtin_ia32_tcvtrowps2phh_internal",
+                    "tcvtrowps2phhi" => "__builtin_ia32_tcvtrowps2phhi",
                     "tcvtrowps2phl" => "__builtin_ia32_tcvtrowps2phl",
                     "tcvtrowps2phl.internal" => "__builtin_ia32_tcvtrowps2phl_internal",
+                    "tcvtrowps2phli" => "__builtin_ia32_tcvtrowps2phli",
                     "tdpbf16ps" => "__builtin_ia32_tdpbf16ps",
                     "tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal",
                     "tdpbf8ps" => "__builtin_ia32_tdpbf8ps",
@@ -10304,6 +8933,7 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal",
                     "tilemovrow" => "__builtin_ia32_tilemovrow",
                     "tilemovrow.internal" => "__builtin_ia32_tilemovrow_internal",
+                    "tilemovrowi" => "__builtin_ia32_tilemovrowi",
                     "tilerelease" => "__builtin_ia32_tilerelease",
                     "tilestored64" => "__builtin_ia32_tilestored64",
                     "tilestored64.internal" => "__builtin_ia32_tilestored64_internal",
@@ -10330,8 +8960,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "vcvtneoph2ps256" => "__builtin_ia32_vcvtneoph2ps256",
                     "vcvtneps2bf16128" => "__builtin_ia32_vcvtneps2bf16128",
                     "vcvtneps2bf16256" => "__builtin_ia32_vcvtneps2bf16256",
-                    "vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps",
-                    "vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256",
                     "vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph",
                     "vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256",
                     "vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi",
@@ -10375,16 +9003,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256",
                     "xop.vfrcz.sd" => "__builtin_ia32_vfrczsd",
                     "xop.vfrcz.ss" => "__builtin_ia32_vfrczss",
-                    "xop.vpcmov" => "__builtin_ia32_vpcmov",
-                    "xop.vpcmov.256" => "__builtin_ia32_vpcmov_256",
-                    "xop.vpcomb" => "__builtin_ia32_vpcomb",
-                    "xop.vpcomd" => "__builtin_ia32_vpcomd",
-                    "xop.vpcomq" => "__builtin_ia32_vpcomq",
-                    "xop.vpcomub" => "__builtin_ia32_vpcomub",
-                    "xop.vpcomud" => "__builtin_ia32_vpcomud",
-                    "xop.vpcomuq" => "__builtin_ia32_vpcomuq",
-                    "xop.vpcomuw" => "__builtin_ia32_vpcomuw",
-                    "xop.vpcomw" => "__builtin_ia32_vpcomw",
                     "xop.vpermil2pd" => "__builtin_ia32_vpermil2pd",
                     "xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256",
                     "xop.vpermil2ps" => "__builtin_ia32_vpermil2ps",
@@ -10417,14 +9035,6 @@ fn x86(name: &str, full_name: &str) -> &'static str {
                     "xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd",
                     "xop.vpmadcswd" => "__builtin_ia32_vpmadcswd",
                     "xop.vpperm" => "__builtin_ia32_vpperm",
-                    "xop.vprotb" => "__builtin_ia32_vprotb",
-                    "xop.vprotbi" => "__builtin_ia32_vprotbi",
-                    "xop.vprotd" => "__builtin_ia32_vprotd",
-                    "xop.vprotdi" => "__builtin_ia32_vprotdi",
-                    "xop.vprotq" => "__builtin_ia32_vprotq",
-                    "xop.vprotqi" => "__builtin_ia32_vprotqi",
-                    "xop.vprotw" => "__builtin_ia32_vprotw",
-                    "xop.vprotwi" => "__builtin_ia32_vprotwi",
                     "xop.vpshab" => "__builtin_ia32_vpshab",
                     "xop.vpshad" => "__builtin_ia32_vpshad",
                     "xop.vpshaq" => "__builtin_ia32_vpshaq",
@@ -10454,6 +9064,14 @@ fn xcore(name: &str, full_name: &str) -> &'static str {
             }
             xcore(name, full_name)
         }
-        _ => unimplemented!("***** unsupported LLVM architecture {arch}, intrinsic:{full_name}"),
+        _ => match old_arch_res {
+            ArchCheckResult::UnknownIntrinsic => {
+                unimplemented!("***** unsupported LLVM intrinsic {full_name}")
+            }
+            ArchCheckResult::UnknownArch => {
+                unimplemented!("***** unsupported LLVM architecture {arch}, intrinsic: {full_name}")
+            }
+            ArchCheckResult::Ok(_) => unreachable!(),
+        },
     }
 }

compiler/rustc_codegen_gcc/src/intrinsic/llvm.rs

@@ -4,7 +4,7 @@
 use rustc_codegen_ssa::traits::BuilderMethods;
 
 use crate::builder::Builder;
-use crate::context::CodegenCx;
+use crate::context::{CodegenCx, new_array_type};
 
 fn encode_key_128_type<'a, 'gcc, 'tcx>(
     builder: &Builder<'a, 'gcc, 'tcx>,
@@ -585,7 +585,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
             "__builtin_ia32_encodekey128_u32" => {
                 let mut new_args = args.to_vec();
                 let m128i = builder.context.new_vector_type(builder.i64_type, 2);
-                let array_type = builder.context.new_array_type(None, m128i, 6);
+                let array_type = new_array_type(builder.context, None, m128i, 6);
                 let result = builder.current_func().new_local(None, array_type, "result");
                 new_args.push(result.get_address(None));
                 args = new_args.into();
@@ -593,7 +593,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
             "__builtin_ia32_encodekey256_u32" => {
                 let mut new_args = args.to_vec();
                 let m128i = builder.context.new_vector_type(builder.i64_type, 2);
-                let array_type = builder.context.new_array_type(None, m128i, 7);
+                let array_type = new_array_type(builder.context, None, m128i, 7);
                 let result = builder.current_func().new_local(None, array_type, "result");
                 new_args.push(result.get_address(None));
                 args = new_args.into();
@@ -620,7 +620,7 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
                 let first_value = old_args.swap_remove(0);
 
                 let element_type = first_value.get_type();
-                let array_type = builder.context.new_array_type(None, element_type, 8);
+                let array_type = new_array_type(builder.context, None, element_type, 8);
                 let result = builder.current_func().new_local(None, array_type, "result");
                 new_args.push(result.get_address(None));
 
@@ -869,7 +869,7 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(
             builder.llbb().add_assignment(None, field1, return_value);
             let field2 = result.access_field(None, field2);
             let field2_type = field2.to_rvalue().get_type();
-            let array_type = builder.context.new_array_type(None, field2_type, 6);
+            let array_type = new_array_type(builder.context, None, field2_type, 6);
             let ptr = builder.context.new_cast(None, args[2], array_type.make_pointer());
             let field2_ptr =
                 builder.context.new_cast(None, field2.get_address(None), array_type.make_pointer());
@@ -891,7 +891,7 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(
             builder.llbb().add_assignment(None, field1, return_value);
             let field2 = result.access_field(None, field2);
             let field2_type = field2.to_rvalue().get_type();
-            let array_type = builder.context.new_array_type(None, field2_type, 7);
+            let array_type = new_array_type(builder.context, None, field2_type, 7);
             let ptr = builder.context.new_cast(None, args[3], array_type.make_pointer());
             let field2_ptr =
                 builder.context.new_cast(None, field2.get_address(None), array_type.make_pointer());
@@ -937,7 +937,7 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(
             builder.llbb().add_assignment(None, field1, return_value);
             let field2 = result.access_field(None, field2);
             let field2_type = field2.to_rvalue().get_type();
-            let array_type = builder.context.new_array_type(None, field2_type, 8);
+            let array_type = new_array_type(builder.context, None, field2_type, 8);
             let ptr = builder.context.new_cast(None, args[0], array_type.make_pointer());
             let field2_ptr =
                 builder.context.new_cast(None, field2.get_address(None), array_type.make_pointer());
@@ -1061,7 +1061,18 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
 
         "llvm.x86.xgetbv" => "__builtin_ia32_xgetbv",
         // NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html
+        // FIXME: Should handle other targets than `ia32`.
         "llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd",
+        // FIXME: Should handle other targets than `ia32`.
+        "llvm.sqrt.v4f32" => "__builtin_ia32_sqrtps",
+        "llvm.sqrt.f32" => {
+            let gcc_name = "__builtin_sqrtf";
+            let func = cx.context.get_builtin_function(gcc_name);
+            cx.functions.borrow_mut().insert(gcc_name.to_string(), func);
+            return func;
+        }
+        // FIXME: Should handle other targets than `ia32`.
+        "llvm.smax.v4i32" => "__builtin_ia32_pmaxsd128",
         "llvm.x86.avx512.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask",
         "llvm.x86.avx512.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask",
         "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512_mask",
@@ -1604,5 +1615,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
     func
 }
 
+#[cfg(feature = "master")]
+include!("old_archs.rs");
 #[cfg(feature = "master")]
 include!("archs.rs");

compiler/rustc_codegen_gcc/src/intrinsic/mod.rs

@@ -208,6 +208,7 @@ fn get_simple_function_f128<'gcc, 'tcx>(
     let f128_type = cx.type_f128();
     let func_name = match name {
         sym::ceilf128 => "ceilf128",
+        sym::fabsf128 => "fabsf128",
         sym::floorf128 => "floorf128",
         sym::truncf128 => "truncf128",
         sym::roundf128 => "roundf128",
@@ -262,6 +263,7 @@ fn f16_builtin<'gcc, 'tcx>(
     let builtin_name = match name {
         sym::ceilf16 => "__builtin_ceilf",
         sym::copysignf16 => "__builtin_copysignf",
+        sym::fabsf16 => "fabsf",
         sym::floorf16 => "__builtin_floorf",
         sym::fmaf16 => "fmaf",
         sym::maxnumf16 => "__builtin_fmaxf",
@@ -328,6 +330,7 @@ fn codegen_intrinsic_call(
             }
             sym::ceilf16
             | sym::copysignf16
+            | sym::fabsf16
             | sym::floorf16
             | sym::fmaf16
             | sym::maxnumf16
@@ -648,15 +651,15 @@ fn codegen_llvm_intrinsic_call(
         let fn_ptr = func.get_address(None);
         let fn_ty = fn_ptr.get_type();
 
-        let mut llargs = vec![];
+        let mut call_args = vec![];
 
         for arg in args {
             match arg.val {
                 OperandValue::ZeroSized => {}
-                OperandValue::Immediate(_) => llargs.push(arg.immediate()),
+                OperandValue::Immediate(_) => call_args.push(arg.immediate()),
                 OperandValue::Pair(a, b) => {
-                    llargs.push(a);
-                    llargs.push(b);
+                    call_args.push(a);
+                    call_args.push(b);
                 }
                 OperandValue::Ref(op_place_val) => {
                     let mut llval = op_place_val.llval;
@@ -673,13 +676,13 @@ fn codegen_llvm_intrinsic_call(
                         // We store bools as `i8` so we need to truncate to `i1`.
                         llval = self.to_immediate_scalar(llval, scalar);
                     }
-                    llargs.push(llval);
+                    call_args.push(llval);
                 }
             }
         }
 
         // FIXME directly use the llvm intrinsic adjustment functions here
-        let llret = self.call(fn_ty, None, None, fn_ptr, &llargs, None, None);
+        let llret = self.call(fn_ty, None, None, fn_ptr, &call_args, None, None);
         if is_cleanup {
             self.apply_attrs_to_cleanup_callsite(llret);
         }
@@ -720,7 +723,8 @@ fn va_start(&mut self, _va_list: RValue<'gcc>) -> RValue<'gcc> {
     }
 
     fn va_end(&mut self, _va_list: RValue<'gcc>) -> RValue<'gcc> {
-        unimplemented!();
+        // TODO(antoyo): implement.
+        self.context.new_rvalue_from_int(self.int_type, 0)
     }
 }
 

compiler/rustc_codegen_gcc/src/intrinsic/old_archs.rs

@@ -0,0 +1,1390 @@
+// All these translations used to be automatically generated in the past. However, since they never
+// changed, we decided to simplify the translation generation script to move them directly into this
+// file.
+//
+// So in short: avoid editing this file.
+
+pub(crate) enum ArchCheckResult {
+    Ok(&'static str),
+    UnknownIntrinsic,
+    UnknownArch,
+}
+
+pub(crate) fn old_archs(arch: &str, name: &str) -> ArchCheckResult {
+    ArchCheckResult::Ok(match arch {
+        "AMDGPU" => match name {
+            "div.fixup.f32" => "__builtin_amdgpu_div_fixup",
+            "div.fixup.f64" => "__builtin_amdgpu_div_fixup",
+            "div.fixup.v2f64" => "__builtin_amdgpu_div_fixup",
+            "div.fixup.v4f32" => "__builtin_amdgpu_div_fixup",
+            "div.fmas.f32" => "__builtin_amdgpu_div_fmas",
+            "div.fmas.f64" => "__builtin_amdgpu_div_fmas",
+            "div.fmas.v2f64" => "__builtin_amdgpu_div_fmas",
+            "div.fmas.v4f32" => "__builtin_amdgpu_div_fmas",
+            "ldexp.f32" => "__builtin_amdgpu_ldexp",
+            "ldexp.f64" => "__builtin_amdgpu_ldexp",
+            "ldexp.v2f64" => "__builtin_amdgpu_ldexp",
+            "ldexp.v4f32" => "__builtin_amdgpu_ldexp",
+            "rcp.f32" => "__builtin_amdgpu_rcp",
+            "rcp.f64" => "__builtin_amdgpu_rcp",
+            "rcp.v2f64" => "__builtin_amdgpu_rcp",
+            "rcp.v4f32" => "__builtin_amdgpu_rcp",
+            "rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped",
+            "rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped",
+            "rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped",
+            "rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped",
+            "rsq.f32" => "__builtin_amdgpu_rsq",
+            "rsq.f64" => "__builtin_amdgpu_rsq",
+            "rsq.v2f64" => "__builtin_amdgpu_rsq",
+            "rsq.v4f32" => "__builtin_amdgpu_rsq",
+            "trig.preop.f32" => "__builtin_amdgpu_trig_preop",
+            "trig.preop.f64" => "__builtin_amdgpu_trig_preop",
+            "trig.preop.v2f64" => "__builtin_amdgpu_trig_preop",
+            "trig.preop.v4f32" => "__builtin_amdgpu_trig_preop",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "arm" => match name {
+            "mcrr" => "__builtin_arm_mcrr",
+            "mcrr2" => "__builtin_arm_mcrr2",
+            "thread.pointer" => "__builtin_thread_pointer",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "cuda" => match name {
+            "syncthreads" => "__syncthreads",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "hexagon" => match name {
+            "F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd",
+            "F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn",
+            "F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr",
+            "F2.dffma" => "__builtin_HEXAGON_F2_dffma",
+            "F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib",
+            "F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc",
+            "F2.dffms" => "__builtin_HEXAGON_F2_dffms",
+            "F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib",
+            "F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy",
+            "S2.cabacencbin" => "__builtin_HEXAGON_S2_cabacencbin",
+            "SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh",
+            "V6.vlutb" => "__builtin_HEXAGON_V6_vlutb",
+            "V6.vlutb.128B" => "__builtin_HEXAGON_V6_vlutb_128B",
+            "V6.vlutb.acc" => "__builtin_HEXAGON_V6_vlutb_acc",
+            "V6.vlutb.acc.128B" => "__builtin_HEXAGON_V6_vlutb_acc_128B",
+            "V6.vlutb.dv" => "__builtin_HEXAGON_V6_vlutb_dv",
+            "V6.vlutb.dv.128B" => "__builtin_HEXAGON_V6_vlutb_dv_128B",
+            "V6.vlutb.dv.acc" => "__builtin_HEXAGON_V6_vlutb_dv_acc",
+            "V6.vlutb.dv.acc.128B" => "__builtin_HEXAGON_V6_vlutb_dv_acc_128B",
+            "brev.ldb" => "__builtin_brev_ldb",
+            "brev.ldd" => "__builtin_brev_ldd",
+            "brev.ldh" => "__builtin_brev_ldh",
+            "brev.ldub" => "__builtin_brev_ldub",
+            "brev.lduh" => "__builtin_brev_lduh",
+            "brev.ldw" => "__builtin_brev_ldw",
+            "brev.stb" => "__builtin_brev_stb",
+            "brev.std" => "__builtin_brev_std",
+            "brev.sth" => "__builtin_brev_sth",
+            "brev.sthhi" => "__builtin_brev_sthhi",
+            "brev.stw" => "__builtin_brev_stw",
+            "mm256i.vaddw" => "__builtin__mm256i_vaddw",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "nvvm" => match name {
+            "abs.i" => "__nvvm_abs_i",
+            "abs.ll" => "__nvvm_abs_ll",
+            "bar.sync" => "__nvvm_bar_sync",
+            "barrier0" => "__nvvm_bar0",
+            "bitcast.d2ll" => "__nvvm_bitcast_d2ll",
+            "bitcast.f2i" => "__nvvm_bitcast_f2i",
+            "bitcast.i2f" => "__nvvm_bitcast_i2f",
+            "bitcast.ll2d" => "__nvvm_bitcast_ll2d",
+            "brev32" => "__nvvm_brev32",
+            "brev64" => "__nvvm_brev64",
+            "clz.i" => "__nvvm_clz_i",
+            "clz.ll" => "__nvvm_clz_ll",
+            "ex2.approx.d" => "__nvvm_ex2_approx_d",
+            "ex2.approx.f" => "__nvvm_ex2_approx_f",
+            "ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f",
+            "fabs.d" => "__nvvm_fabs_d",
+            "fabs.f" => "__nvvm_fabs_f",
+            "fabs.ftz.f" => "__nvvm_fabs_ftz_f",
+            "h2f" => "__nvvm_h2f",
+            "max.i" => "__nvvm_max_i",
+            "max.ll" => "__nvvm_max_ll",
+            "max.ui" => "__nvvm_max_ui",
+            "max.ull" => "__nvvm_max_ull",
+            "min.i" => "__nvvm_min_i",
+            "min.ll" => "__nvvm_min_ll",
+            "min.ui" => "__nvvm_min_ui",
+            "min.ull" => "__nvvm_min_ull",
+            "popc.i" => "__nvvm_popc_i",
+            "popc.ll" => "__nvvm_popc_ll",
+            "rotate.b32" => "__nvvm_rotate_b32",
+            "rotate.b64" => "__nvvm_rotate_b64",
+            "rotate.right.b64" => "__nvvm_rotate_right_b64",
+            "swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "ppc" => match name {
+            "qpx.qvfabs" => "__builtin_qpx_qvfabs",
+            "qpx.qvfadd" => "__builtin_qpx_qvfadd",
+            "qpx.qvfadds" => "__builtin_qpx_qvfadds",
+            "qpx.qvfcfid" => "__builtin_qpx_qvfcfid",
+            "qpx.qvfcfids" => "__builtin_qpx_qvfcfids",
+            "qpx.qvfcfidu" => "__builtin_qpx_qvfcfidu",
+            "qpx.qvfcfidus" => "__builtin_qpx_qvfcfidus",
+            "qpx.qvfcmpeq" => "__builtin_qpx_qvfcmpeq",
+            "qpx.qvfcmpgt" => "__builtin_qpx_qvfcmpgt",
+            "qpx.qvfcmplt" => "__builtin_qpx_qvfcmplt",
+            "qpx.qvfcpsgn" => "__builtin_qpx_qvfcpsgn",
+            "qpx.qvfctid" => "__builtin_qpx_qvfctid",
+            "qpx.qvfctidu" => "__builtin_qpx_qvfctidu",
+            "qpx.qvfctiduz" => "__builtin_qpx_qvfctiduz",
+            "qpx.qvfctidz" => "__builtin_qpx_qvfctidz",
+            "qpx.qvfctiw" => "__builtin_qpx_qvfctiw",
+            "qpx.qvfctiwu" => "__builtin_qpx_qvfctiwu",
+            "qpx.qvfctiwuz" => "__builtin_qpx_qvfctiwuz",
+            "qpx.qvfctiwz" => "__builtin_qpx_qvfctiwz",
+            "qpx.qvflogical" => "__builtin_qpx_qvflogical",
+            "qpx.qvfmadd" => "__builtin_qpx_qvfmadd",
+            "qpx.qvfmadds" => "__builtin_qpx_qvfmadds",
+            "qpx.qvfmsub" => "__builtin_qpx_qvfmsub",
+            "qpx.qvfmsubs" => "__builtin_qpx_qvfmsubs",
+            "qpx.qvfmul" => "__builtin_qpx_qvfmul",
+            "qpx.qvfmuls" => "__builtin_qpx_qvfmuls",
+            "qpx.qvfnabs" => "__builtin_qpx_qvfnabs",
+            "qpx.qvfneg" => "__builtin_qpx_qvfneg",
+            "qpx.qvfnmadd" => "__builtin_qpx_qvfnmadd",
+            "qpx.qvfnmadds" => "__builtin_qpx_qvfnmadds",
+            "qpx.qvfnmsub" => "__builtin_qpx_qvfnmsub",
+            "qpx.qvfnmsubs" => "__builtin_qpx_qvfnmsubs",
+            "qpx.qvfperm" => "__builtin_qpx_qvfperm",
+            "qpx.qvfre" => "__builtin_qpx_qvfre",
+            "qpx.qvfres" => "__builtin_qpx_qvfres",
+            "qpx.qvfrim" => "__builtin_qpx_qvfrim",
+            "qpx.qvfrin" => "__builtin_qpx_qvfrin",
+            "qpx.qvfrip" => "__builtin_qpx_qvfrip",
+            "qpx.qvfriz" => "__builtin_qpx_qvfriz",
+            "qpx.qvfrsp" => "__builtin_qpx_qvfrsp",
+            "qpx.qvfrsqrte" => "__builtin_qpx_qvfrsqrte",
+            "qpx.qvfrsqrtes" => "__builtin_qpx_qvfrsqrtes",
+            "qpx.qvfsel" => "__builtin_qpx_qvfsel",
+            "qpx.qvfsub" => "__builtin_qpx_qvfsub",
+            "qpx.qvfsubs" => "__builtin_qpx_qvfsubs",
+            "qpx.qvftstnan" => "__builtin_qpx_qvftstnan",
+            "qpx.qvfxmadd" => "__builtin_qpx_qvfxmadd",
+            "qpx.qvfxmadds" => "__builtin_qpx_qvfxmadds",
+            "qpx.qvfxmul" => "__builtin_qpx_qvfxmul",
+            "qpx.qvfxmuls" => "__builtin_qpx_qvfxmuls",
+            "qpx.qvfxxcpnmadd" => "__builtin_qpx_qvfxxcpnmadd",
+            "qpx.qvfxxcpnmadds" => "__builtin_qpx_qvfxxcpnmadds",
+            "qpx.qvfxxmadd" => "__builtin_qpx_qvfxxmadd",
+            "qpx.qvfxxmadds" => "__builtin_qpx_qvfxxmadds",
+            "qpx.qvfxxnpmadd" => "__builtin_qpx_qvfxxnpmadd",
+            "qpx.qvfxxnpmadds" => "__builtin_qpx_qvfxxnpmadds",
+            "qpx.qvgpci" => "__builtin_qpx_qvgpci",
+            "qpx.qvlfcd" => "__builtin_qpx_qvlfcd",
+            "qpx.qvlfcda" => "__builtin_qpx_qvlfcda",
+            "qpx.qvlfcs" => "__builtin_qpx_qvlfcs",
+            "qpx.qvlfcsa" => "__builtin_qpx_qvlfcsa",
+            "qpx.qvlfd" => "__builtin_qpx_qvlfd",
+            "qpx.qvlfda" => "__builtin_qpx_qvlfda",
+            "qpx.qvlfiwa" => "__builtin_qpx_qvlfiwa",
+            "qpx.qvlfiwaa" => "__builtin_qpx_qvlfiwaa",
+            "qpx.qvlfiwz" => "__builtin_qpx_qvlfiwz",
+            "qpx.qvlfiwza" => "__builtin_qpx_qvlfiwza",
+            "qpx.qvlfs" => "__builtin_qpx_qvlfs",
+            "qpx.qvlfsa" => "__builtin_qpx_qvlfsa",
+            "qpx.qvlpcld" => "__builtin_qpx_qvlpcld",
+            "qpx.qvlpcls" => "__builtin_qpx_qvlpcls",
+            "qpx.qvlpcrd" => "__builtin_qpx_qvlpcrd",
+            "qpx.qvlpcrs" => "__builtin_qpx_qvlpcrs",
+            "qpx.qvstfcd" => "__builtin_qpx_qvstfcd",
+            "qpx.qvstfcda" => "__builtin_qpx_qvstfcda",
+            "qpx.qvstfcs" => "__builtin_qpx_qvstfcs",
+            "qpx.qvstfcsa" => "__builtin_qpx_qvstfcsa",
+            "qpx.qvstfd" => "__builtin_qpx_qvstfd",
+            "qpx.qvstfda" => "__builtin_qpx_qvstfda",
+            "qpx.qvstfiw" => "__builtin_qpx_qvstfiw",
+            "qpx.qvstfiwa" => "__builtin_qpx_qvstfiwa",
+            "qpx.qvstfs" => "__builtin_qpx_qvstfs",
+            "qpx.qvstfsa" => "__builtin_qpx_qvstfsa",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "ptx" => match name {
+            "bar.sync" => "__builtin_ptx_bar_sync",
+            "read.clock" => "__builtin_ptx_read_clock",
+            "read.clock64" => "__builtin_ptx_read_clock64",
+            "read.gridid" => "__builtin_ptx_read_gridid",
+            "read.laneid" => "__builtin_ptx_read_laneid",
+            "read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq",
+            "read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge",
+            "read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt",
+            "read.lanemask.le" => "__builtin_ptx_read_lanemask_le",
+            "read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt",
+            "read.nsmid" => "__builtin_ptx_read_nsmid",
+            "read.nwarpid" => "__builtin_ptx_read_nwarpid",
+            "read.pm0" => "__builtin_ptx_read_pm0",
+            "read.pm1" => "__builtin_ptx_read_pm1",
+            "read.pm2" => "__builtin_ptx_read_pm2",
+            "read.pm3" => "__builtin_ptx_read_pm3",
+            "read.smid" => "__builtin_ptx_read_smid",
+            "read.warpid" => "__builtin_ptx_read_warpid",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        "x86" => match name {
+            "addcarry.u32" => "__builtin_ia32_addcarry_u32",
+            "addcarry.u64" => "__builtin_ia32_addcarry_u64",
+            "addcarryx.u32" => "__builtin_ia32_addcarryx_u32",
+            "addcarryx.u64" => "__builtin_ia32_addcarryx_u64",
+            "avx.blend.pd.256" => "__builtin_ia32_blendpd256",
+            "avx.blend.ps.256" => "__builtin_ia32_blendps256",
+            "avx.cmp.pd.256" => "__builtin_ia32_cmppd256",
+            "avx.cmp.ps.256" => "__builtin_ia32_cmpps256",
+            "avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256",
+            "avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256",
+            "avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256",
+            "avx.round.pd.256" => "__builtin_ia32_roundpd256",
+            "avx.round.ps.256" => "__builtin_ia32_roundps256",
+            "avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256",
+            "avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256",
+            "avx.storeu.dq.256" => "__builtin_ia32_storedqu256",
+            "avx.storeu.pd.256" => "__builtin_ia32_storeupd256",
+            "avx.storeu.ps.256" => "__builtin_ia32_storeups256",
+            "avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256",
+            "avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256",
+            "avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256",
+            "avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256",
+            "avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256",
+            "avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256",
+            "avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256",
+            "avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256",
+            "avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256",
+            "avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256",
+            "avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256",
+            "avx2.movntdqa" => "__builtin_ia32_movntdqa256",
+            "avx2.pabs.b" => "__builtin_ia32_pabsb256",
+            "avx2.pabs.d" => "__builtin_ia32_pabsd256",
+            "avx2.pabs.w" => "__builtin_ia32_pabsw256",
+            "avx2.padds.b" => "__builtin_ia32_paddsb256",
+            "avx2.padds.w" => "__builtin_ia32_paddsw256",
+            "avx2.paddus.b" => "__builtin_ia32_paddusb256",
+            "avx2.paddus.w" => "__builtin_ia32_paddusw256",
+            "avx2.pblendd.128" => "__builtin_ia32_pblendd128",
+            "avx2.pblendd.256" => "__builtin_ia32_pblendd256",
+            "avx2.pblendw" => "__builtin_ia32_pblendw256",
+            "avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128",
+            "avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256",
+            "avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128",
+            "avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256",
+            "avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128",
+            "avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256",
+            "avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128",
+            "avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256",
+            "avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256",
+            "avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256",
+            "avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256",
+            "avx2.pmaxu.b" => "__builtin_ia32_pmaxub256",
+            "avx2.pmaxu.d" => "__builtin_ia32_pmaxud256",
+            "avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256",
+            "avx2.pmins.b" => "__builtin_ia32_pminsb256",
+            "avx2.pmins.d" => "__builtin_ia32_pminsd256",
+            "avx2.pmins.w" => "__builtin_ia32_pminsw256",
+            "avx2.pminu.b" => "__builtin_ia32_pminub256",
+            "avx2.pminu.d" => "__builtin_ia32_pminud256",
+            "avx2.pminu.w" => "__builtin_ia32_pminuw256",
+            "avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256",
+            "avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256",
+            "avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256",
+            "avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256",
+            "avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256",
+            "avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256",
+            "avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256",
+            "avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256",
+            "avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256",
+            "avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256",
+            "avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256",
+            "avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256",
+            "avx2.pmul.dq" => "__builtin_ia32_pmuldq256",
+            "avx2.pmulu.dq" => "__builtin_ia32_pmuludq256",
+            "avx2.psll.dq" => "__builtin_ia32_pslldqi256",
+            "avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift",
+            "avx2.psrl.dq" => "__builtin_ia32_psrldqi256",
+            "avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift",
+            "avx2.psubs.b" => "__builtin_ia32_psubsb256",
+            "avx2.psubs.w" => "__builtin_ia32_psubsw256",
+            "avx2.psubus.b" => "__builtin_ia32_psubusb256",
+            "avx2.psubus.w" => "__builtin_ia32_psubusw256",
+            "avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256",
+            "avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps",
+            "avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256",
+            "avx2.vextracti128" => "__builtin_ia32_extract128i256",
+            "avx2.vinserti128" => "__builtin_ia32_insert128i256",
+            "avx2.vperm2i128" => "__builtin_ia32_permti256",
+            "avx512.cvtb2mask.128" => "__builtin_ia32_cvtb2mask128",
+            "avx512.cvtb2mask.256" => "__builtin_ia32_cvtb2mask256",
+            "avx512.cvtb2mask.512" => "__builtin_ia32_cvtb2mask512",
+            "avx512.cvtd2mask.128" => "__builtin_ia32_cvtd2mask128",
+            "avx512.cvtd2mask.256" => "__builtin_ia32_cvtd2mask256",
+            "avx512.cvtd2mask.512" => "__builtin_ia32_cvtd2mask512",
+            "avx512.cvtmask2b.128" => "__builtin_ia32_cvtmask2b128",
+            "avx512.cvtmask2b.256" => "__builtin_ia32_cvtmask2b256",
+            "avx512.cvtmask2b.512" => "__builtin_ia32_cvtmask2b512",
+            "avx512.cvtmask2d.128" => "__builtin_ia32_cvtmask2d128",
+            "avx512.cvtmask2d.256" => "__builtin_ia32_cvtmask2d256",
+            "avx512.cvtmask2d.512" => "__builtin_ia32_cvtmask2d512",
+            "avx512.cvtmask2q.128" => "__builtin_ia32_cvtmask2q128",
+            "avx512.cvtmask2q.256" => "__builtin_ia32_cvtmask2q256",
+            "avx512.cvtmask2q.512" => "__builtin_ia32_cvtmask2q512",
+            "avx512.cvtmask2w.128" => "__builtin_ia32_cvtmask2w128",
+            "avx512.cvtmask2w.256" => "__builtin_ia32_cvtmask2w256",
+            "avx512.cvtmask2w.512" => "__builtin_ia32_cvtmask2w512",
+            "avx512.cvtq2mask.128" => "__builtin_ia32_cvtq2mask128",
+            "avx512.cvtq2mask.256" => "__builtin_ia32_cvtq2mask256",
+            "avx512.cvtq2mask.512" => "__builtin_ia32_cvtq2mask512",
+            "avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi",
+            "avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64",
+            "avx512.cvtsi2sd32" => "__builtin_ia32_cvtsi2sd32",
+            "avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi",
+            "avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64",
+            "avx512.cvtw2mask.128" => "__builtin_ia32_cvtw2mask128",
+            "avx512.cvtw2mask.256" => "__builtin_ia32_cvtw2mask256",
+            "avx512.cvtw2mask.512" => "__builtin_ia32_cvtw2mask512",
+            "avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask",
+            "avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask",
+            "avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df",
+            "avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si",
+            "avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di",
+            "avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf",
+            "avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df",
+            "avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si",
+            "avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di",
+            "avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf",
+            "avx512.gather3div2.df" => "__builtin_ia32_gather3div2df",
+            "avx512.gather3div2.di" => "__builtin_ia32_gather3div2di",
+            "avx512.gather3div4.df" => "__builtin_ia32_gather3div4df",
+            "avx512.gather3div4.di" => "__builtin_ia32_gather3div4di",
+            "avx512.gather3div4.sf" => "__builtin_ia32_gather3div4sf",
+            "avx512.gather3div4.si" => "__builtin_ia32_gather3div4si",
+            "avx512.gather3div8.sf" => "__builtin_ia32_gather3div8sf",
+            "avx512.gather3div8.si" => "__builtin_ia32_gather3div8si",
+            "avx512.gather3siv2.df" => "__builtin_ia32_gather3siv2df",
+            "avx512.gather3siv2.di" => "__builtin_ia32_gather3siv2di",
+            "avx512.gather3siv4.df" => "__builtin_ia32_gather3siv4df",
+            "avx512.gather3siv4.di" => "__builtin_ia32_gather3siv4di",
+            "avx512.gather3siv4.sf" => "__builtin_ia32_gather3siv4sf",
+            "avx512.gather3siv4.si" => "__builtin_ia32_gather3siv4si",
+            "avx512.gather3siv8.sf" => "__builtin_ia32_gather3siv8sf",
+            "avx512.gather3siv8.si" => "__builtin_ia32_gather3siv8si",
+            "avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd",
+            "avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps",
+            "avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd",
+            "avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps",
+            "avx512.kand.w" => "__builtin_ia32_kandhi",
+            "avx512.kandn.w" => "__builtin_ia32_kandnhi",
+            "avx512.knot.w" => "__builtin_ia32_knothi",
+            "avx512.kor.w" => "__builtin_ia32_korhi",
+            "avx512.kortestc.w" => "__builtin_ia32_kortestchi",
+            "avx512.kortestz.w" => "__builtin_ia32_kortestzhi",
+            "avx512.kunpck.bw" => "__builtin_ia32_kunpckhi",
+            "avx512.kunpck.dq" => "__builtin_ia32_kunpckdi",
+            "avx512.kunpck.wd" => "__builtin_ia32_kunpcksi",
+            "avx512.kxnor.w" => "__builtin_ia32_kxnorhi",
+            "avx512.kxor.w" => "__builtin_ia32_kxorhi",
+            "avx512.mask.add.pd.128" => "__builtin_ia32_addpd128_mask",
+            "avx512.mask.add.pd.256" => "__builtin_ia32_addpd256_mask",
+            "avx512.mask.add.pd.512" => "__builtin_ia32_addpd512_mask",
+            "avx512.mask.add.ps.128" => "__builtin_ia32_addps128_mask",
+            "avx512.mask.add.ps.256" => "__builtin_ia32_addps256_mask",
+            "avx512.mask.add.ps.512" => "__builtin_ia32_addps512_mask",
+            "avx512.mask.and.pd.128" => "__builtin_ia32_andpd128_mask",
+            "avx512.mask.and.pd.256" => "__builtin_ia32_andpd256_mask",
+            "avx512.mask.and.pd.512" => "__builtin_ia32_andpd512_mask",
+            "avx512.mask.and.ps.128" => "__builtin_ia32_andps128_mask",
+            "avx512.mask.and.ps.256" => "__builtin_ia32_andps256_mask",
+            "avx512.mask.and.ps.512" => "__builtin_ia32_andps512_mask",
+            "avx512.mask.andn.pd.128" => "__builtin_ia32_andnpd128_mask",
+            "avx512.mask.andn.pd.256" => "__builtin_ia32_andnpd256_mask",
+            "avx512.mask.andn.pd.512" => "__builtin_ia32_andnpd512_mask",
+            "avx512.mask.andn.ps.128" => "__builtin_ia32_andnps128_mask",
+            "avx512.mask.andn.ps.256" => "__builtin_ia32_andnps256_mask",
+            "avx512.mask.andn.ps.512" => "__builtin_ia32_andnps512_mask",
+            "avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask",
+            "avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask",
+            "avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask",
+            "avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask",
+            "avx512.mask.broadcastf32x2.256" => "__builtin_ia32_broadcastf32x2_256_mask",
+            "avx512.mask.broadcastf32x2.512" => "__builtin_ia32_broadcastf32x2_512_mask",
+            "avx512.mask.broadcastf32x4.256" => "__builtin_ia32_broadcastf32x4_256_mask",
+            "avx512.mask.broadcastf32x4.512" => "__builtin_ia32_broadcastf32x4_512",
+            "avx512.mask.broadcastf32x8.512" => "__builtin_ia32_broadcastf32x8_512_mask",
+            "avx512.mask.broadcastf64x2.256" => "__builtin_ia32_broadcastf64x2_256_mask",
+            "avx512.mask.broadcastf64x2.512" => "__builtin_ia32_broadcastf64x2_512_mask",
+            "avx512.mask.broadcastf64x4.512" => "__builtin_ia32_broadcastf64x4_512",
+            "avx512.mask.broadcasti32x2.128" => "__builtin_ia32_broadcasti32x2_128_mask",
+            "avx512.mask.broadcasti32x2.256" => "__builtin_ia32_broadcasti32x2_256_mask",
+            "avx512.mask.broadcasti32x2.512" => "__builtin_ia32_broadcasti32x2_512_mask",
+            "avx512.mask.broadcasti32x4.256" => "__builtin_ia32_broadcasti32x4_256_mask",
+            "avx512.mask.broadcasti32x4.512" => "__builtin_ia32_broadcasti32x4_512",
+            "avx512.mask.broadcasti32x8.512" => "__builtin_ia32_broadcasti32x8_512_mask",
+            "avx512.mask.broadcasti64x2.256" => "__builtin_ia32_broadcasti64x2_256_mask",
+            "avx512.mask.broadcasti64x2.512" => "__builtin_ia32_broadcasti64x2_512_mask",
+            "avx512.mask.broadcasti64x4.512" => "__builtin_ia32_broadcasti64x4_512",
+            "avx512.mask.cmp.pd.128" => "__builtin_ia32_cmppd128_mask",
+            "avx512.mask.cmp.pd.256" => "__builtin_ia32_cmppd256_mask",
+            "avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask",
+            "avx512.mask.cmp.ps.128" => "__builtin_ia32_cmpps128_mask",
+            "avx512.mask.cmp.ps.256" => "__builtin_ia32_cmpps256_mask",
+            "avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask",
+            "avx512.mask.compress.d.128" => "__builtin_ia32_compresssi128_mask",
+            "avx512.mask.compress.d.256" => "__builtin_ia32_compresssi256_mask",
+            "avx512.mask.compress.d.512" => "__builtin_ia32_compresssi512_mask",
+            "avx512.mask.compress.pd.128" => "__builtin_ia32_compressdf128_mask",
+            "avx512.mask.compress.pd.256" => "__builtin_ia32_compressdf256_mask",
+            "avx512.mask.compress.pd.512" => "__builtin_ia32_compressdf512_mask",
+            "avx512.mask.compress.ps.128" => "__builtin_ia32_compresssf128_mask",
+            "avx512.mask.compress.ps.256" => "__builtin_ia32_compresssf256_mask",
+            "avx512.mask.compress.ps.512" => "__builtin_ia32_compresssf512_mask",
+            "avx512.mask.compress.q.128" => "__builtin_ia32_compressdi128_mask",
+            "avx512.mask.compress.q.256" => "__builtin_ia32_compressdi256_mask",
+            "avx512.mask.compress.q.512" => "__builtin_ia32_compressdi512_mask",
+            "avx512.mask.compress.store.d.128" => "__builtin_ia32_compressstoresi128_mask",
+            "avx512.mask.compress.store.d.256" => "__builtin_ia32_compressstoresi256_mask",
+            "avx512.mask.compress.store.d.512" => "__builtin_ia32_compressstoresi512_mask",
+            "avx512.mask.compress.store.pd.128" => "__builtin_ia32_compressstoredf128_mask",
+            "avx512.mask.compress.store.pd.256" => "__builtin_ia32_compressstoredf256_mask",
+            "avx512.mask.compress.store.pd.512" => "__builtin_ia32_compressstoredf512_mask",
+            "avx512.mask.compress.store.ps.128" => "__builtin_ia32_compressstoresf128_mask",
+            "avx512.mask.compress.store.ps.256" => "__builtin_ia32_compressstoresf256_mask",
+            "avx512.mask.compress.store.ps.512" => "__builtin_ia32_compressstoresf512_mask",
+            "avx512.mask.compress.store.q.128" => "__builtin_ia32_compressstoredi128_mask",
+            "avx512.mask.compress.store.q.256" => "__builtin_ia32_compressstoredi256_mask",
+            "avx512.mask.compress.store.q.512" => "__builtin_ia32_compressstoredi512_mask",
+            "avx512.mask.conflict.d.128" => "__builtin_ia32_vpconflictsi_128_mask",
+            "avx512.mask.conflict.d.256" => "__builtin_ia32_vpconflictsi_256_mask",
+            "avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask",
+            "avx512.mask.conflict.q.128" => "__builtin_ia32_vpconflictdi_128_mask",
+            "avx512.mask.conflict.q.256" => "__builtin_ia32_vpconflictdi_256_mask",
+            "avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask",
+            "avx512.mask.cvtdq2pd.128" => "__builtin_ia32_cvtdq2pd128_mask",
+            "avx512.mask.cvtdq2pd.256" => "__builtin_ia32_cvtdq2pd256_mask",
+            "avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask",
+            "avx512.mask.cvtdq2ps.128" => "__builtin_ia32_cvtdq2ps128_mask",
+            "avx512.mask.cvtdq2ps.256" => "__builtin_ia32_cvtdq2ps256_mask",
+            "avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask",
+            "avx512.mask.cvtpd2dq.256" => "__builtin_ia32_cvtpd2dq256_mask",
+            "avx512.mask.cvtps2pd.128" => "__builtin_ia32_cvtps2pd128_mask",
+            "avx512.mask.cvtps2pd.256" => "__builtin_ia32_cvtps2pd256_mask",
+            "avx512.mask.cvtqq2pd.128" => "__builtin_ia32_cvtqq2pd128_mask",
+            "avx512.mask.cvtqq2pd.256" => "__builtin_ia32_cvtqq2pd256_mask",
+            "avx512.mask.cvtqq2pd.512" => "__builtin_ia32_cvtqq2pd512_mask",
+            "avx512.mask.cvtqq2ps.256" => "__builtin_ia32_cvtqq2ps256_mask",
+            "avx512.mask.cvtqq2ps.512" => "__builtin_ia32_cvtqq2ps512_mask",
+            "avx512.mask.cvttpd2dq.256" => "__builtin_ia32_cvttpd2dq256_mask",
+            "avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask",
+            "avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask",
+            "avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask",
+            "avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask",
+            "avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask",
+            "avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask",
+            "avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask",
+            "avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask",
+            "avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask",
+            "avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask",
+            "avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask",
+            "avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask",
+            "avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask",
+            "avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask",
+            "avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask",
+            "avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask",
+            "avx512.mask.div.pd.128" => "__builtin_ia32_divpd_mask",
+            "avx512.mask.div.pd.256" => "__builtin_ia32_divpd256_mask",
+            "avx512.mask.div.pd.512" => "__builtin_ia32_divpd512_mask",
+            "avx512.mask.div.ps.128" => "__builtin_ia32_divps_mask",
+            "avx512.mask.div.ps.256" => "__builtin_ia32_divps256_mask",
+            "avx512.mask.div.ps.512" => "__builtin_ia32_divps512_mask",
+            "avx512.mask.expand.d.128" => "__builtin_ia32_expandsi128_mask",
+            "avx512.mask.expand.d.256" => "__builtin_ia32_expandsi256_mask",
+            "avx512.mask.expand.d.512" => "__builtin_ia32_expandsi512_mask",
+            "avx512.mask.expand.load.d.128" => "__builtin_ia32_expandloadsi128_mask",
+            "avx512.mask.expand.load.d.256" => "__builtin_ia32_expandloadsi256_mask",
+            "avx512.mask.expand.load.d.512" => "__builtin_ia32_expandloadsi512_mask",
+            "avx512.mask.expand.load.pd.128" => "__builtin_ia32_expandloaddf128_mask",
+            "avx512.mask.expand.load.pd.256" => "__builtin_ia32_expandloaddf256_mask",
+            "avx512.mask.expand.load.pd.512" => "__builtin_ia32_expandloaddf512_mask",
+            "avx512.mask.expand.load.ps.128" => "__builtin_ia32_expandloadsf128_mask",
+            "avx512.mask.expand.load.ps.256" => "__builtin_ia32_expandloadsf256_mask",
+            "avx512.mask.expand.load.ps.512" => "__builtin_ia32_expandloadsf512_mask",
+            "avx512.mask.expand.load.q.128" => "__builtin_ia32_expandloaddi128_mask",
+            "avx512.mask.expand.load.q.256" => "__builtin_ia32_expandloaddi256_mask",
+            "avx512.mask.expand.load.q.512" => "__builtin_ia32_expandloaddi512_mask",
+            "avx512.mask.expand.pd.128" => "__builtin_ia32_expanddf128_mask",
+            "avx512.mask.expand.pd.256" => "__builtin_ia32_expanddf256_mask",
+            "avx512.mask.expand.pd.512" => "__builtin_ia32_expanddf512_mask",
+            "avx512.mask.expand.ps.128" => "__builtin_ia32_expandsf128_mask",
+            "avx512.mask.expand.ps.256" => "__builtin_ia32_expandsf256_mask",
+            "avx512.mask.expand.ps.512" => "__builtin_ia32_expandsf512_mask",
+            "avx512.mask.expand.q.128" => "__builtin_ia32_expanddi128_mask",
+            "avx512.mask.expand.q.256" => "__builtin_ia32_expanddi256_mask",
+            "avx512.mask.expand.q.512" => "__builtin_ia32_expanddi512_mask",
+            "avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask",
+            "avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask",
+            "avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask",
+            "avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask",
+            "avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask",
+            "avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask",
+            "avx512.mask.insertf32x4.256" => "__builtin_ia32_insertf32x4_256_mask",
+            "avx512.mask.insertf32x4.512" => "__builtin_ia32_insertf32x4_mask",
+            "avx512.mask.insertf32x8.512" => "__builtin_ia32_insertf32x8_mask",
+            "avx512.mask.insertf64x2.256" => "__builtin_ia32_insertf64x2_256_mask",
+            "avx512.mask.insertf64x2.512" => "__builtin_ia32_insertf64x2_512_mask",
+            "avx512.mask.insertf64x4.512" => "__builtin_ia32_insertf64x4_mask",
+            "avx512.mask.inserti32x4.256" => "__builtin_ia32_inserti32x4_256_mask",
+            "avx512.mask.inserti32x4.512" => "__builtin_ia32_inserti32x4_mask",
+            "avx512.mask.inserti32x8.512" => "__builtin_ia32_inserti32x8_mask",
+            "avx512.mask.inserti64x2.256" => "__builtin_ia32_inserti64x2_256_mask",
+            "avx512.mask.inserti64x2.512" => "__builtin_ia32_inserti64x2_512_mask",
+            "avx512.mask.inserti64x4.512" => "__builtin_ia32_inserti64x4_mask",
+            "avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask",
+            "avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask",
+            "avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask",
+            "avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask",
+            "avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask",
+            "avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask",
+            "avx512.mask.max.pd.128" => "__builtin_ia32_maxpd_mask",
+            "avx512.mask.max.pd.256" => "__builtin_ia32_maxpd256_mask",
+            "avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask",
+            "avx512.mask.max.ps.128" => "__builtin_ia32_maxps_mask",
+            "avx512.mask.max.ps.256" => "__builtin_ia32_maxps256_mask",
+            "avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask",
+            "avx512.mask.min.pd.128" => "__builtin_ia32_minpd_mask",
+            "avx512.mask.min.pd.256" => "__builtin_ia32_minpd256_mask",
+            "avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask",
+            "avx512.mask.min.ps.128" => "__builtin_ia32_minps_mask",
+            "avx512.mask.min.ps.256" => "__builtin_ia32_minps256_mask",
+            "avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask",
+            "avx512.mask.move.sd" => "__builtin_ia32_movsd_mask",
+            "avx512.mask.move.ss" => "__builtin_ia32_movss_mask",
+            "avx512.mask.mul.pd.128" => "__builtin_ia32_mulpd_mask",
+            "avx512.mask.mul.pd.256" => "__builtin_ia32_mulpd256_mask",
+            "avx512.mask.mul.pd.512" => "__builtin_ia32_mulpd512_mask",
+            "avx512.mask.mul.ps.128" => "__builtin_ia32_mulps_mask",
+            "avx512.mask.mul.ps.256" => "__builtin_ia32_mulps256_mask",
+            "avx512.mask.mul.ps.512" => "__builtin_ia32_mulps512_mask",
+            "avx512.mask.or.pd.128" => "__builtin_ia32_orpd128_mask",
+            "avx512.mask.or.pd.256" => "__builtin_ia32_orpd256_mask",
+            "avx512.mask.or.pd.512" => "__builtin_ia32_orpd512_mask",
+            "avx512.mask.or.ps.128" => "__builtin_ia32_orps128_mask",
+            "avx512.mask.or.ps.256" => "__builtin_ia32_orps256_mask",
+            "avx512.mask.or.ps.512" => "__builtin_ia32_orps512_mask",
+            "avx512.mask.pabs.b.128" => "__builtin_ia32_pabsb128_mask",
+            "avx512.mask.pabs.b.256" => "__builtin_ia32_pabsb256_mask",
+            "avx512.mask.pabs.b.512" => "__builtin_ia32_pabsb512_mask",
+            "avx512.mask.pabs.d.128" => "__builtin_ia32_pabsd128_mask",
+            "avx512.mask.pabs.d.256" => "__builtin_ia32_pabsd256_mask",
+            "avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask",
+            "avx512.mask.pabs.q.128" => "__builtin_ia32_pabsq128_mask",
+            "avx512.mask.pabs.q.256" => "__builtin_ia32_pabsq256_mask",
+            "avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask",
+            "avx512.mask.pabs.w.128" => "__builtin_ia32_pabsw128_mask",
+            "avx512.mask.pabs.w.256" => "__builtin_ia32_pabsw256_mask",
+            "avx512.mask.pabs.w.512" => "__builtin_ia32_pabsw512_mask",
+            "avx512.mask.packssdw.128" => "__builtin_ia32_packssdw128_mask",
+            "avx512.mask.packssdw.256" => "__builtin_ia32_packssdw256_mask",
+            "avx512.mask.packssdw.512" => "__builtin_ia32_packssdw512_mask",
+            "avx512.mask.packsswb.128" => "__builtin_ia32_packsswb128_mask",
+            "avx512.mask.packsswb.256" => "__builtin_ia32_packsswb256_mask",
+            "avx512.mask.packsswb.512" => "__builtin_ia32_packsswb512_mask",
+            "avx512.mask.packusdw.128" => "__builtin_ia32_packusdw128_mask",
+            "avx512.mask.packusdw.256" => "__builtin_ia32_packusdw256_mask",
+            "avx512.mask.packusdw.512" => "__builtin_ia32_packusdw512_mask",
+            "avx512.mask.packuswb.128" => "__builtin_ia32_packuswb128_mask",
+            "avx512.mask.packuswb.256" => "__builtin_ia32_packuswb256_mask",
+            "avx512.mask.packuswb.512" => "__builtin_ia32_packuswb512_mask",
+            "avx512.mask.padd.b.128" => "__builtin_ia32_paddb128_mask",
+            "avx512.mask.padd.b.256" => "__builtin_ia32_paddb256_mask",
+            "avx512.mask.padd.b.512" => "__builtin_ia32_paddb512_mask",
+            "avx512.mask.padd.d.128" => "__builtin_ia32_paddd128_mask",
+            "avx512.mask.padd.d.256" => "__builtin_ia32_paddd256_mask",
+            "avx512.mask.padd.d.512" => "__builtin_ia32_paddd512_mask",
+            "avx512.mask.padd.q.128" => "__builtin_ia32_paddq128_mask",
+            "avx512.mask.padd.q.256" => "__builtin_ia32_paddq256_mask",
+            "avx512.mask.padd.q.512" => "__builtin_ia32_paddq512_mask",
+            "avx512.mask.padd.w.128" => "__builtin_ia32_paddw128_mask",
+            "avx512.mask.padd.w.256" => "__builtin_ia32_paddw256_mask",
+            "avx512.mask.padd.w.512" => "__builtin_ia32_paddw512_mask",
+            "avx512.mask.padds.b.128" => "__builtin_ia32_paddsb128_mask",
+            "avx512.mask.padds.b.256" => "__builtin_ia32_paddsb256_mask",
+            "avx512.mask.padds.b.512" => "__builtin_ia32_paddsb512_mask",
+            "avx512.mask.padds.w.128" => "__builtin_ia32_paddsw128_mask",
+            "avx512.mask.padds.w.256" => "__builtin_ia32_paddsw256_mask",
+            "avx512.mask.padds.w.512" => "__builtin_ia32_paddsw512_mask",
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+            "avx512.mask.paddus.b.256" => "__builtin_ia32_paddusb256_mask",
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+            "avx512.mask.psll.qi.256" => "__builtin_ia32_psllqi256_mask",
+            "avx512.mask.psll.qi.512" => "__builtin_ia32_psllqi512_mask",
+            "avx512.mask.psll.w.128" => "__builtin_ia32_psllw128_mask",
+            "avx512.mask.psll.w.256" => "__builtin_ia32_psllw256_mask",
+            "avx512.mask.psll.w.512" => "__builtin_ia32_psllw512_mask",
+            "avx512.mask.psll.wi.128" => "__builtin_ia32_psllwi128_mask",
+            "avx512.mask.psll.wi.256" => "__builtin_ia32_psllwi256_mask",
+            "avx512.mask.psll.wi.512" => "__builtin_ia32_psllwi512_mask",
+            "avx512.mask.psllv.d" => "__builtin_ia32_psllv16si_mask",
+            "avx512.mask.psllv.q" => "__builtin_ia32_psllv8di_mask",
+            "avx512.mask.psllv16.hi" => "__builtin_ia32_psllv16hi_mask",
+            "avx512.mask.psllv2.di" => "__builtin_ia32_psllv2di_mask",
+            "avx512.mask.psllv32hi" => "__builtin_ia32_psllv32hi_mask",
+            "avx512.mask.psllv4.di" => "__builtin_ia32_psllv4di_mask",
+            "avx512.mask.psllv4.si" => "__builtin_ia32_psllv4si_mask",
+            "avx512.mask.psllv8.hi" => "__builtin_ia32_psllv8hi_mask",
+            "avx512.mask.psllv8.si" => "__builtin_ia32_psllv8si_mask",
+            "avx512.mask.psra.d" => "__builtin_ia32_psrad512_mask",
+            "avx512.mask.psra.d.128" => "__builtin_ia32_psrad128_mask",
+            "avx512.mask.psra.d.256" => "__builtin_ia32_psrad256_mask",
+            "avx512.mask.psra.di.128" => "__builtin_ia32_psradi128_mask",
+            "avx512.mask.psra.di.256" => "__builtin_ia32_psradi256_mask",
+            "avx512.mask.psra.di.512" => "__builtin_ia32_psradi512_mask",
+            "avx512.mask.psra.q" => "__builtin_ia32_psraq512_mask",
+            "avx512.mask.psra.q.128" => "__builtin_ia32_psraq128_mask",
+            "avx512.mask.psra.q.256" => "__builtin_ia32_psraq256_mask",
+            "avx512.mask.psra.qi.128" => "__builtin_ia32_psraqi128_mask",
+            "avx512.mask.psra.qi.256" => "__builtin_ia32_psraqi256_mask",
+            "avx512.mask.psra.qi.512" => "__builtin_ia32_psraqi512_mask",
+            "avx512.mask.psra.w.128" => "__builtin_ia32_psraw128_mask",
+            "avx512.mask.psra.w.256" => "__builtin_ia32_psraw256_mask",
+            "avx512.mask.psra.w.512" => "__builtin_ia32_psraw512_mask",
+            "avx512.mask.psra.wi.128" => "__builtin_ia32_psrawi128_mask",
+            "avx512.mask.psra.wi.256" => "__builtin_ia32_psrawi256_mask",
+            "avx512.mask.psra.wi.512" => "__builtin_ia32_psrawi512_mask",
+            "avx512.mask.psrav.d" => "__builtin_ia32_psrav16si_mask",
+            "avx512.mask.psrav.q" => "__builtin_ia32_psrav8di_mask",
+            "avx512.mask.psrav.q.128" => "__builtin_ia32_psravq128_mask",
+            "avx512.mask.psrav.q.256" => "__builtin_ia32_psravq256_mask",
+            "avx512.mask.psrav16.hi" => "__builtin_ia32_psrav16hi_mask",
+            "avx512.mask.psrav32.hi" => "__builtin_ia32_psrav32hi_mask",
+            "avx512.mask.psrav4.si" => "__builtin_ia32_psrav4si_mask",
+            "avx512.mask.psrav8.hi" => "__builtin_ia32_psrav8hi_mask",
+            "avx512.mask.psrav8.si" => "__builtin_ia32_psrav8si_mask",
+            "avx512.mask.psrl.d" => "__builtin_ia32_psrld512_mask",
+            "avx512.mask.psrl.d.128" => "__builtin_ia32_psrld128_mask",
+            "avx512.mask.psrl.d.256" => "__builtin_ia32_psrld256_mask",
+            "avx512.mask.psrl.di.128" => "__builtin_ia32_psrldi128_mask",
+            "avx512.mask.psrl.di.256" => "__builtin_ia32_psrldi256_mask",
+            "avx512.mask.psrl.di.512" => "__builtin_ia32_psrldi512_mask",
+            "avx512.mask.psrl.q" => "__builtin_ia32_psrlq512_mask",
+            "avx512.mask.psrl.q.128" => "__builtin_ia32_psrlq128_mask",
+            "avx512.mask.psrl.q.256" => "__builtin_ia32_psrlq256_mask",
+            "avx512.mask.psrl.qi.128" => "__builtin_ia32_psrlqi128_mask",
+            "avx512.mask.psrl.qi.256" => "__builtin_ia32_psrlqi256_mask",
+            "avx512.mask.psrl.qi.512" => "__builtin_ia32_psrlqi512_mask",
+            "avx512.mask.psrl.w.128" => "__builtin_ia32_psrlw128_mask",
+            "avx512.mask.psrl.w.256" => "__builtin_ia32_psrlw256_mask",
+            "avx512.mask.psrl.w.512" => "__builtin_ia32_psrlw512_mask",
+            "avx512.mask.psrl.wi.128" => "__builtin_ia32_psrlwi128_mask",
+            "avx512.mask.psrl.wi.256" => "__builtin_ia32_psrlwi256_mask",
+            "avx512.mask.psrl.wi.512" => "__builtin_ia32_psrlwi512_mask",
+            "avx512.mask.psrlv.d" => "__builtin_ia32_psrlv16si_mask",
+            "avx512.mask.psrlv.q" => "__builtin_ia32_psrlv8di_mask",
+            "avx512.mask.psrlv16.hi" => "__builtin_ia32_psrlv16hi_mask",
+            "avx512.mask.psrlv2.di" => "__builtin_ia32_psrlv2di_mask",
+            "avx512.mask.psrlv32hi" => "__builtin_ia32_psrlv32hi_mask",
+            "avx512.mask.psrlv4.di" => "__builtin_ia32_psrlv4di_mask",
+            "avx512.mask.psrlv4.si" => "__builtin_ia32_psrlv4si_mask",
+            "avx512.mask.psrlv8.hi" => "__builtin_ia32_psrlv8hi_mask",
+            "avx512.mask.psrlv8.si" => "__builtin_ia32_psrlv8si_mask",
+            "avx512.mask.psub.b.128" => "__builtin_ia32_psubb128_mask",
+            "avx512.mask.psub.b.256" => "__builtin_ia32_psubb256_mask",
+            "avx512.mask.psub.b.512" => "__builtin_ia32_psubb512_mask",
+            "avx512.mask.psub.d.128" => "__builtin_ia32_psubd128_mask",
+            "avx512.mask.psub.d.256" => "__builtin_ia32_psubd256_mask",
+            "avx512.mask.psub.d.512" => "__builtin_ia32_psubd512_mask",
+            "avx512.mask.psub.q.128" => "__builtin_ia32_psubq128_mask",
+            "avx512.mask.psub.q.256" => "__builtin_ia32_psubq256_mask",
+            "avx512.mask.psub.q.512" => "__builtin_ia32_psubq512_mask",
+            "avx512.mask.psub.w.128" => "__builtin_ia32_psubw128_mask",
+            "avx512.mask.psub.w.256" => "__builtin_ia32_psubw256_mask",
+            "avx512.mask.psub.w.512" => "__builtin_ia32_psubw512_mask",
+            "avx512.mask.psubs.b.128" => "__builtin_ia32_psubsb128_mask",
+            "avx512.mask.psubs.b.256" => "__builtin_ia32_psubsb256_mask",
+            "avx512.mask.psubs.b.512" => "__builtin_ia32_psubsb512_mask",
+            "avx512.mask.psubs.w.128" => "__builtin_ia32_psubsw128_mask",
+            "avx512.mask.psubs.w.256" => "__builtin_ia32_psubsw256_mask",
+            "avx512.mask.psubs.w.512" => "__builtin_ia32_psubsw512_mask",
+            "avx512.mask.psubus.b.128" => "__builtin_ia32_psubusb128_mask",
+            "avx512.mask.psubus.b.256" => "__builtin_ia32_psubusb256_mask",
+            "avx512.mask.psubus.b.512" => "__builtin_ia32_psubusb512_mask",
+            "avx512.mask.psubus.w.128" => "__builtin_ia32_psubusw128_mask",
+            "avx512.mask.psubus.w.256" => "__builtin_ia32_psubusw256_mask",
+            "avx512.mask.psubus.w.512" => "__builtin_ia32_psubusw512_mask",
+            "avx512.mask.pternlog.d.128" => "__builtin_ia32_pternlogd128_mask",
+            "avx512.mask.pternlog.d.256" => "__builtin_ia32_pternlogd256_mask",
+            "avx512.mask.pternlog.d.512" => "__builtin_ia32_pternlogd512_mask",
+            "avx512.mask.pternlog.q.128" => "__builtin_ia32_pternlogq128_mask",
+            "avx512.mask.pternlog.q.256" => "__builtin_ia32_pternlogq256_mask",
+            "avx512.mask.pternlog.q.512" => "__builtin_ia32_pternlogq512_mask",
+            "avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512",
+            "avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512",
+            "avx512.mask.shuf.f32x4" => "__builtin_ia32_shuf_f32x4_mask",
+            "avx512.mask.shuf.f32x4.256" => "__builtin_ia32_shuf_f32x4_256_mask",
+            "avx512.mask.shuf.f64x2" => "__builtin_ia32_shuf_f64x2_mask",
+            "avx512.mask.shuf.f64x2.256" => "__builtin_ia32_shuf_f64x2_256_mask",
+            "avx512.mask.shuf.i32x4" => "__builtin_ia32_shuf_i32x4_mask",
+            "avx512.mask.shuf.i32x4.256" => "__builtin_ia32_shuf_i32x4_256_mask",
+            "avx512.mask.shuf.i64x2" => "__builtin_ia32_shuf_i64x2_mask",
+            "avx512.mask.shuf.i64x2.256" => "__builtin_ia32_shuf_i64x2_256_mask",
+            "avx512.mask.shuf.pd.128" => "__builtin_ia32_shufpd128_mask",
+            "avx512.mask.shuf.pd.256" => "__builtin_ia32_shufpd256_mask",
+            "avx512.mask.shuf.pd.512" => "__builtin_ia32_shufpd512_mask",
+            "avx512.mask.shuf.ps.128" => "__builtin_ia32_shufps128_mask",
+            "avx512.mask.shuf.ps.256" => "__builtin_ia32_shufps256_mask",
+            "avx512.mask.shuf.ps.512" => "__builtin_ia32_shufps512_mask",
+            "avx512.mask.sqrt.pd.128" => "__builtin_ia32_sqrtpd128_mask",
+            "avx512.mask.sqrt.pd.256" => "__builtin_ia32_sqrtpd256_mask",
+            "avx512.mask.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
+            "avx512.mask.sqrt.ps.128" => "__builtin_ia32_sqrtps128_mask",
+            "avx512.mask.sqrt.ps.256" => "__builtin_ia32_sqrtps256_mask",
+            "avx512.mask.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
+            "avx512.mask.store.ss" => "__builtin_ia32_storess_mask",
+            "avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask",
+            "avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask",
+            "avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask",
+            "avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask",
+            "avx512.mask.sub.pd.128" => "__builtin_ia32_subpd128_mask",
+            "avx512.mask.sub.pd.256" => "__builtin_ia32_subpd256_mask",
+            "avx512.mask.sub.pd.512" => "__builtin_ia32_subpd512_mask",
+            "avx512.mask.sub.ps.128" => "__builtin_ia32_subps128_mask",
+            "avx512.mask.sub.ps.256" => "__builtin_ia32_subps256_mask",
+            "avx512.mask.sub.ps.512" => "__builtin_ia32_subps512_mask",
+            "avx512.mask.valign.d.128" => "__builtin_ia32_alignd128_mask",
+            "avx512.mask.valign.d.256" => "__builtin_ia32_alignd256_mask",
+            "avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask",
+            "avx512.mask.valign.q.128" => "__builtin_ia32_alignq128_mask",
+            "avx512.mask.valign.q.256" => "__builtin_ia32_alignq256_mask",
+            "avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask",
+            "avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask",
+            "avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask",
+            "avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask",
+            "avx512.mask.vextractf32x4.256" => "__builtin_ia32_extractf32x4_256_mask",
+            "avx512.mask.vextractf32x4.512" => "__builtin_ia32_extractf32x4_mask",
+            "avx512.mask.vextractf32x8.512" => "__builtin_ia32_extractf32x8_mask",
+            "avx512.mask.vextractf64x2.256" => "__builtin_ia32_extractf64x2_256_mask",
+            "avx512.mask.vextractf64x2.512" => "__builtin_ia32_extractf64x2_512_mask",
+            "avx512.mask.vextractf64x4.512" => "__builtin_ia32_extractf64x4_mask",
+            "avx512.mask.vextracti32x4.256" => "__builtin_ia32_extracti32x4_256_mask",
+            "avx512.mask.vextracti32x4.512" => "__builtin_ia32_extracti32x4_mask",
+            "avx512.mask.vextracti32x8.512" => "__builtin_ia32_extracti32x8_mask",
+            "avx512.mask.vextracti64x2.256" => "__builtin_ia32_extracti64x2_256_mask",
+            "avx512.mask.vextracti64x2.512" => "__builtin_ia32_extracti64x2_512_mask",
+            "avx512.mask.vextracti64x4.512" => "__builtin_ia32_extracti64x4_mask",
+            "avx512.mask.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask",
+            "avx512.mask.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask",
+            "avx512.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
+            "avx512.mask.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask",
+            "avx512.mask.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask",
+            "avx512.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
+            "avx512.mask.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask",
+            "avx512.mask.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask",
+            "avx512.mask.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask",
+            "avx512.mask.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask",
+            "avx512.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
+            "avx512.mask.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask",
+            "avx512.mask.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask",
+            "avx512.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
+            "avx512.mask.vfnmadd.pd.128" => "__builtin_ia32_vfnmaddpd128_mask",
+            "avx512.mask.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256_mask",
+            "avx512.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
+            "avx512.mask.vfnmadd.ps.128" => "__builtin_ia32_vfnmaddps128_mask",
+            "avx512.mask.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256_mask",
+            "avx512.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
+            "avx512.mask.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask",
+            "avx512.mask.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask",
+            "avx512.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
+            "avx512.mask.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask",
+            "avx512.mask.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask",
+            "avx512.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
+            "avx512.mask.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128_mask",
+            "avx512.mask.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256_mask",
+            "avx512.mask.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512_mask",
+            "avx512.mask.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128_mask",
+            "avx512.mask.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256_mask",
+            "avx512.mask.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512_mask",
+            "avx512.mask.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128_mask",
+            "avx512.mask.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256_mask",
+            "avx512.mask.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512_mask",
+            "avx512.mask.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128_mask",
+            "avx512.mask.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256_mask",
+            "avx512.mask.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512_mask",
+            "avx512.mask.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128_mask",
+            "avx512.mask.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256_mask",
+            "avx512.mask.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512_mask",
+            "avx512.mask.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128_mask",
+            "avx512.mask.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256_mask",
+            "avx512.mask.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512_mask",
+            "avx512.mask.vpermilvar.pd.128" => "__builtin_ia32_vpermilvarpd_mask",
+            "avx512.mask.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256_mask",
+            "avx512.mask.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512_mask",
+            "avx512.mask.vpermilvar.ps.128" => "__builtin_ia32_vpermilvarps_mask",
+            "avx512.mask.vpermilvar.ps.256" => "__builtin_ia32_vpermilvarps256_mask",
+            "avx512.mask.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512_mask",
+            "avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask",
+            "avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
+            "avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
+            "avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask",
+            "avx512.mask.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_mask",
+            "avx512.mask.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_mask",
+            "avx512.mask.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_mask",
+            "avx512.mask.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_mask",
+            "avx512.mask.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_mask",
+            "avx512.mask.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_mask",
+            "avx512.mask.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_mask",
+            "avx512.mask.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_mask",
+            "avx512.mask.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_mask",
+            "avx512.mask.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_mask",
+            "avx512.mask.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_mask",
+            "avx512.mask.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_mask",
+            "avx512.mask.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_mask",
+            "avx512.mask.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_mask",
+            "avx512.mask.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_mask",
+            "avx512.mask.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_mask",
+            "avx512.mask.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_mask",
+            "avx512.mask.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_mask",
+            "avx512.mask.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_mask",
+            "avx512.mask.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_mask",
+            "avx512.mask.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_mask",
+            "avx512.mask.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_mask",
+            "avx512.mask.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_mask",
+            "avx512.mask.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_mask",
+            "avx512.mask.xor.pd.128" => "__builtin_ia32_xorpd128_mask",
+            "avx512.mask.xor.pd.256" => "__builtin_ia32_xorpd256_mask",
+            "avx512.mask.xor.pd.512" => "__builtin_ia32_xorpd512_mask",
+            "avx512.mask.xor.ps.128" => "__builtin_ia32_xorps128_mask",
+            "avx512.mask.xor.ps.256" => "__builtin_ia32_xorps256_mask",
+            "avx512.mask.xor.ps.512" => "__builtin_ia32_xorps512_mask",
+            "avx512.mask3.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_mask3",
+            "avx512.mask3.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_mask3",
+            "avx512.mask3.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask3",
+            "avx512.mask3.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_mask3",
+            "avx512.mask3.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_mask3",
+            "avx512.mask3.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask3",
+            "avx512.mask3.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_mask3",
+            "avx512.mask3.vfmadd.ss" => "__builtin_ia32_vfmaddss3_mask3",
+            "avx512.mask3.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_mask3",
+            "avx512.mask3.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_mask3",
+            "avx512.mask3.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask3",
+            "avx512.mask3.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_mask3",
+            "avx512.mask3.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_mask3",
+            "avx512.mask3.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask3",
+            "avx512.mask3.vfmsub.pd.128" => "__builtin_ia32_vfmsubpd128_mask3",
+            "avx512.mask3.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256_mask3",
+            "avx512.mask3.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask3",
+            "avx512.mask3.vfmsub.ps.128" => "__builtin_ia32_vfmsubps128_mask3",
+            "avx512.mask3.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256_mask3",
+            "avx512.mask3.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask3",
+            "avx512.mask3.vfmsubadd.pd.128" => "__builtin_ia32_vfmsubaddpd128_mask3",
+            "avx512.mask3.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256_mask3",
+            "avx512.mask3.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask3",
+            "avx512.mask3.vfmsubadd.ps.128" => "__builtin_ia32_vfmsubaddps128_mask3",
+            "avx512.mask3.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256_mask3",
+            "avx512.mask3.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask3",
+            "avx512.mask3.vfnmsub.pd.128" => "__builtin_ia32_vfnmsubpd128_mask3",
+            "avx512.mask3.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256_mask3",
+            "avx512.mask3.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask3",
+            "avx512.mask3.vfnmsub.ps.128" => "__builtin_ia32_vfnmsubps128_mask3",
+            "avx512.mask3.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256_mask3",
+            "avx512.mask3.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask3",
+            "avx512.maskz.pternlog.d.128" => "__builtin_ia32_pternlogd128_maskz",
+            "avx512.maskz.pternlog.d.256" => "__builtin_ia32_pternlogd256_maskz",
+            "avx512.maskz.pternlog.d.512" => "__builtin_ia32_pternlogd512_maskz",
+            "avx512.maskz.pternlog.q.128" => "__builtin_ia32_pternlogq128_maskz",
+            "avx512.maskz.pternlog.q.256" => "__builtin_ia32_pternlogq256_maskz",
+            "avx512.maskz.pternlog.q.512" => "__builtin_ia32_pternlogq512_maskz",
+            "avx512.maskz.vfmadd.pd.128" => "__builtin_ia32_vfmaddpd128_maskz",
+            "avx512.maskz.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256_maskz",
+            "avx512.maskz.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_maskz",
+            "avx512.maskz.vfmadd.ps.128" => "__builtin_ia32_vfmaddps128_maskz",
+            "avx512.maskz.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256_maskz",
+            "avx512.maskz.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_maskz",
+            "avx512.maskz.vfmadd.sd" => "__builtin_ia32_vfmaddsd3_maskz",
+            "avx512.maskz.vfmadd.ss" => "__builtin_ia32_vfmaddss3_maskz",
+            "avx512.maskz.vfmaddsub.pd.128" => "__builtin_ia32_vfmaddsubpd128_maskz",
+            "avx512.maskz.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256_maskz",
+            "avx512.maskz.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_maskz",
+            "avx512.maskz.vfmaddsub.ps.128" => "__builtin_ia32_vfmaddsubps128_maskz",
+            "avx512.maskz.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256_maskz",
+            "avx512.maskz.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_maskz",
+            "avx512.maskz.vpermt2var.d.128" => "__builtin_ia32_vpermt2vard128_maskz",
+            "avx512.maskz.vpermt2var.d.256" => "__builtin_ia32_vpermt2vard256_maskz",
+            "avx512.maskz.vpermt2var.d.512" => "__builtin_ia32_vpermt2vard512_maskz",
+            "avx512.maskz.vpermt2var.hi.128" => "__builtin_ia32_vpermt2varhi128_maskz",
+            "avx512.maskz.vpermt2var.hi.256" => "__builtin_ia32_vpermt2varhi256_maskz",
+            "avx512.maskz.vpermt2var.hi.512" => "__builtin_ia32_vpermt2varhi512_maskz",
+            "avx512.maskz.vpermt2var.pd.128" => "__builtin_ia32_vpermt2varpd128_maskz",
+            "avx512.maskz.vpermt2var.pd.256" => "__builtin_ia32_vpermt2varpd256_maskz",
+            "avx512.maskz.vpermt2var.pd.512" => "__builtin_ia32_vpermt2varpd512_maskz",
+            "avx512.maskz.vpermt2var.ps.128" => "__builtin_ia32_vpermt2varps128_maskz",
+            "avx512.maskz.vpermt2var.ps.256" => "__builtin_ia32_vpermt2varps256_maskz",
+            "avx512.maskz.vpermt2var.ps.512" => "__builtin_ia32_vpermt2varps512_maskz",
+            "avx512.maskz.vpermt2var.q.128" => "__builtin_ia32_vpermt2varq128_maskz",
+            "avx512.maskz.vpermt2var.q.256" => "__builtin_ia32_vpermt2varq256_maskz",
+            "avx512.maskz.vpermt2var.q.512" => "__builtin_ia32_vpermt2varq512_maskz",
+            "avx512.maskz.vpermt2var.qi.128" => "__builtin_ia32_vpermt2varqi128_maskz",
+            "avx512.maskz.vpermt2var.qi.256" => "__builtin_ia32_vpermt2varqi256_maskz",
+            "avx512.maskz.vpermt2var.qi.512" => "__builtin_ia32_vpermt2varqi512_maskz",
+            "avx512.maskz.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128_maskz",
+            "avx512.maskz.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256_maskz",
+            "avx512.maskz.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512_maskz",
+            "avx512.maskz.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128_maskz",
+            "avx512.maskz.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256_maskz",
+            "avx512.maskz.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512_maskz",
+            "avx512.movntdqa" => "__builtin_ia32_movntdqa512",
+            "avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512",
+            "avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512",
+            "avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512",
+            "avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512",
+            "avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512",
+            "avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512",
+            "avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512",
+            "avx512.psll.dq" => "__builtin_ia32_pslldqi512",
+            "avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift",
+            "avx512.psrl.dq" => "__builtin_ia32_psrldqi512",
+            "avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift",
+            "avx512.ptestm.b.128" => "__builtin_ia32_ptestmb128",
+            "avx512.ptestm.b.256" => "__builtin_ia32_ptestmb256",
+            "avx512.ptestm.b.512" => "__builtin_ia32_ptestmb512",
+            "avx512.ptestm.d.128" => "__builtin_ia32_ptestmd128",
+            "avx512.ptestm.d.256" => "__builtin_ia32_ptestmd256",
+            "avx512.ptestm.d.512" => "__builtin_ia32_ptestmd512",
+            "avx512.ptestm.q.128" => "__builtin_ia32_ptestmq128",
+            "avx512.ptestm.q.256" => "__builtin_ia32_ptestmq256",
+            "avx512.ptestm.q.512" => "__builtin_ia32_ptestmq512",
+            "avx512.ptestm.w.128" => "__builtin_ia32_ptestmw128",
+            "avx512.ptestm.w.256" => "__builtin_ia32_ptestmw256",
+            "avx512.ptestm.w.512" => "__builtin_ia32_ptestmw512",
+            "avx512.ptestnm.b.128" => "__builtin_ia32_ptestnmb128",
+            "avx512.ptestnm.b.256" => "__builtin_ia32_ptestnmb256",
+            "avx512.ptestnm.b.512" => "__builtin_ia32_ptestnmb512",
+            "avx512.ptestnm.d.128" => "__builtin_ia32_ptestnmd128",
+            "avx512.ptestnm.d.256" => "__builtin_ia32_ptestnmd256",
+            "avx512.ptestnm.d.512" => "__builtin_ia32_ptestnmd512",
+            "avx512.ptestnm.q.128" => "__builtin_ia32_ptestnmq128",
+            "avx512.ptestnm.q.256" => "__builtin_ia32_ptestnmq256",
+            "avx512.ptestnm.q.512" => "__builtin_ia32_ptestnmq512",
+            "avx512.ptestnm.w.128" => "__builtin_ia32_ptestnmw128",
+            "avx512.ptestnm.w.256" => "__builtin_ia32_ptestnmw256",
+            "avx512.ptestnm.w.512" => "__builtin_ia32_ptestnmw512",
+            "avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask",
+            "avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask",
+            "avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask",
+            "avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask",
+            "avx512.rndscale.sd" => "__builtin_ia32_rndscalesd",
+            "avx512.rndscale.ss" => "__builtin_ia32_rndscaless",
+            "avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask",
+            "avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask",
+            "avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask",
+            "avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask",
+            "avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df",
+            "avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si",
+            "avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di",
+            "avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf",
+            "avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df",
+            "avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si",
+            "avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di",
+            "avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf",
+            "avx512.scatterdiv2.df" => "__builtin_ia32_scatterdiv2df",
+            "avx512.scatterdiv2.di" => "__builtin_ia32_scatterdiv2di",
+            "avx512.scatterdiv4.df" => "__builtin_ia32_scatterdiv4df",
+            "avx512.scatterdiv4.di" => "__builtin_ia32_scatterdiv4di",
+            "avx512.scatterdiv4.sf" => "__builtin_ia32_scatterdiv4sf",
+            "avx512.scatterdiv4.si" => "__builtin_ia32_scatterdiv4si",
+            "avx512.scatterdiv8.sf" => "__builtin_ia32_scatterdiv8sf",
+            "avx512.scatterdiv8.si" => "__builtin_ia32_scatterdiv8si",
+            "avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd",
+            "avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps",
+            "avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd",
+            "avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps",
+            "avx512.scattersiv2.df" => "__builtin_ia32_scattersiv2df",
+            "avx512.scattersiv2.di" => "__builtin_ia32_scattersiv2di",
+            "avx512.scattersiv4.df" => "__builtin_ia32_scattersiv4df",
+            "avx512.scattersiv4.di" => "__builtin_ia32_scattersiv4di",
+            "avx512.scattersiv4.sf" => "__builtin_ia32_scattersiv4sf",
+            "avx512.scattersiv4.si" => "__builtin_ia32_scattersiv4si",
+            "avx512.scattersiv8.sf" => "__builtin_ia32_scattersiv8sf",
+            "avx512.scattersiv8.si" => "__builtin_ia32_scattersiv8si",
+            "avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
+            "avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
+            "avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd",
+            "avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss",
+            "avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512",
+            "avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512",
+            "avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512",
+            "avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512",
+            "fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask",
+            "fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask",
+            "fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask",
+            "fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask",
+            "fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask",
+            "fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask",
+            "fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask",
+            "fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask",
+            "fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask",
+            "fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask",
+            "fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask",
+            "fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask",
+            "fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd",
+            "fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256",
+            "fma.vfmadd.ps" => "__builtin_ia32_vfmaddps",
+            "fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256",
+            "fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd",
+            "fma.vfmadd.ss" => "__builtin_ia32_vfmaddss",
+            "fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd",
+            "fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256",
+            "fma.vfmsub.ps" => "__builtin_ia32_vfmsubps",
+            "fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256",
+            "fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd",
+            "fma.vfmsub.ss" => "__builtin_ia32_vfmsubss",
+            "fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd",
+            "fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256",
+            "fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps",
+            "fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256",
+            "fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd",
+            "fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256",
+            "fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps",
+            "fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256",
+            "fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd",
+            "fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss",
+            "fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd",
+            "fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256",
+            "fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps",
+            "fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256",
+            "fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd",
+            "fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss",
+            "mmx.femms" => "__builtin_ia32_femms",
+            "rdtscp" => "__builtin_ia32_rdtscp",
+            "sse.add.ss" => "__builtin_ia32_addss",
+            "sse.cmp.ps" => "__builtin_ia32_cmpps",
+            "sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss",
+            "sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss",
+            "sse.div.ss" => "__builtin_ia32_divss",
+            "sse.mul.ss" => "__builtin_ia32_mulss",
+            "sse.sqrt.ps" => "__builtin_ia32_sqrtps",
+            "sse.sqrt.ss" => "__builtin_ia32_sqrtss",
+            "sse.storeu.ps" => "__builtin_ia32_storeups",
+            "sse.sub.ss" => "__builtin_ia32_subss",
+            "sse2.add.sd" => "__builtin_ia32_addsd",
+            "sse2.cmp.pd" => "__builtin_ia32_cmppd",
+            "sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd",
+            "sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps",
+            "sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd",
+            "sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd",
+            "sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd",
+            "sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd",
+            "sse2.div.sd" => "__builtin_ia32_divsd",
+            "sse2.mul.sd" => "__builtin_ia32_mulsd",
+            "sse2.padds.b" => "__builtin_ia32_paddsb128",
+            "sse2.padds.w" => "__builtin_ia32_paddsw128",
+            "sse2.paddus.b" => "__builtin_ia32_paddusb128",
+            "sse2.paddus.w" => "__builtin_ia32_paddusw128",
+            "sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128",
+            "sse2.pmaxu.b" => "__builtin_ia32_pmaxub128",
+            "sse2.pmins.w" => "__builtin_ia32_pminsw128",
+            "sse2.pminu.b" => "__builtin_ia32_pminub128",
+            "sse2.pmulu.dq" => "__builtin_ia32_pmuludq128",
+            "sse2.pshuf.d" => "__builtin_ia32_pshufd",
+            "sse2.pshufh.w" => "__builtin_ia32_pshufhw",
+            "sse2.pshufl.w" => "__builtin_ia32_pshuflw",
+            "sse2.psll.dq" => "__builtin_ia32_pslldqi128",
+            "sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift",
+            "sse2.psrl.dq" => "__builtin_ia32_psrldqi128",
+            "sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift",
+            "sse2.psubs.b" => "__builtin_ia32_psubsb128",
+            "sse2.psubs.w" => "__builtin_ia32_psubsw128",
+            "sse2.psubus.b" => "__builtin_ia32_psubusb128",
+            "sse2.psubus.w" => "__builtin_ia32_psubusw128",
+            "sse2.sqrt.pd" => "__builtin_ia32_sqrtpd",
+            "sse2.sqrt.sd" => "__builtin_ia32_sqrtsd",
+            "sse2.storel.dq" => "__builtin_ia32_storelv4si",
+            "sse2.storeu.dq" => "__builtin_ia32_storedqu",
+            "sse2.storeu.pd" => "__builtin_ia32_storeupd",
+            "sse2.sub.sd" => "__builtin_ia32_subsd",
+            "sse41.blendpd" => "__builtin_ia32_blendpd",
+            "sse41.blendps" => "__builtin_ia32_blendps",
+            "sse41.extractps" => "__builtin_ia32_extractps128",
+            "sse41.movntdqa" => "__builtin_ia32_movntdqa",
+            "sse41.pblendw" => "__builtin_ia32_pblendw128",
+            "sse41.pmaxsb" => "__builtin_ia32_pmaxsb128",
+            "sse41.pmaxsd" => "__builtin_ia32_pmaxsd128",
+            "sse41.pmaxud" => "__builtin_ia32_pmaxud128",
+            "sse41.pmaxuw" => "__builtin_ia32_pmaxuw128",
+            "sse41.pminsb" => "__builtin_ia32_pminsb128",
+            "sse41.pminsd" => "__builtin_ia32_pminsd128",
+            "sse41.pminud" => "__builtin_ia32_pminud128",
+            "sse41.pminuw" => "__builtin_ia32_pminuw128",
+            "sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128",
+            "sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128",
+            "sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128",
+            "sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128",
+            "sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128",
+            "sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128",
+            "sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128",
+            "sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128",
+            "sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128",
+            "sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128",
+            "sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128",
+            "sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128",
+            "sse41.pmuldq" => "__builtin_ia32_pmuldq128",
+            "sse41.round.pd" => "__builtin_ia32_roundpd",
+            "sse41.round.ps" => "__builtin_ia32_roundps",
+            "sse41.round.sd" => "__builtin_ia32_roundsd",
+            "sse41.round.ss" => "__builtin_ia32_roundss",
+            "sse4a.movnt.sd" => "__builtin_ia32_movntsd",
+            "sse4a.movnt.ss" => "__builtin_ia32_movntss",
+            "ssse3.pabs.b.128" => "__builtin_ia32_pabsb128",
+            "ssse3.pabs.d.128" => "__builtin_ia32_pabsd128",
+            "ssse3.pabs.w.128" => "__builtin_ia32_pabsw128",
+            "subborrow.u32" => "__builtin_ia32_subborrow_u32",
+            "subborrow.u64" => "__builtin_ia32_subborrow_u64",
+            "xop.vpcmov" => "__builtin_ia32_vpcmov",
+            "xop.vpcmov.256" => "__builtin_ia32_vpcmov_256",
+            "xop.vpcomb" => "__builtin_ia32_vpcomb",
+            "xop.vpcomd" => "__builtin_ia32_vpcomd",
+            "xop.vpcomq" => "__builtin_ia32_vpcomq",
+            "xop.vpcomub" => "__builtin_ia32_vpcomub",
+            "xop.vpcomud" => "__builtin_ia32_vpcomud",
+            "xop.vpcomuq" => "__builtin_ia32_vpcomuq",
+            "xop.vpcomuw" => "__builtin_ia32_vpcomuw",
+            "xop.vpcomw" => "__builtin_ia32_vpcomw",
+            "xop.vprotb" => "__builtin_ia32_vprotb",
+            "xop.vprotbi" => "__builtin_ia32_vprotbi",
+            "xop.vprotd" => "__builtin_ia32_vprotd",
+            "xop.vprotdi" => "__builtin_ia32_vprotdi",
+            "xop.vprotq" => "__builtin_ia32_vprotq",
+            "xop.vprotqi" => "__builtin_ia32_vprotqi",
+            "xop.vprotw" => "__builtin_ia32_vprotw",
+            "xop.vprotwi" => "__builtin_ia32_vprotwi",
+            _ => return ArchCheckResult::UnknownIntrinsic,
+        },
+        _ => return ArchCheckResult::UnknownArch,
+    })
+}

compiler/rustc_codegen_gcc/src/lib.rs

@@ -234,6 +234,8 @@ fn file_path(sysroot_path: &Path, sess: &Session) -> PathBuf {
 
         #[cfg(feature = "master")]
         {
+            gccjit::set_lang_name(c"GNU Rust");
+
             let target_cpu = target_cpu(sess);
 
             // Get the second TargetInfo with the correct CPU features by setting the arch.

compiler/rustc_codegen_gcc/src/type_.rs

@@ -13,7 +13,7 @@
 use rustc_middle::{bug, ty};
 
 use crate::common::TypeReflection;
-use crate::context::CodegenCx;
+use crate::context::{CodegenCx, new_array_type};
 use crate::type_of::LayoutGccExt;
 
 impl<'gcc, 'tcx> CodegenCx<'gcc, 'tcx> {
@@ -311,7 +311,7 @@ fn type_array(&self, ty: Type<'gcc>, mut len: u64) -> Type<'gcc> {
             len = 0;
         }
 
-        self.context.new_array_type(None, ty, len)
+        new_array_type(self.context, None, ty, len)
     }
 }
 

compiler/rustc_codegen_gcc/tests/failing-run-make-tests.txt

@@ -11,4 +11,4 @@ tests/run-make/foreign-exceptions/
 tests/run-make/glibc-staticlib-args/
 tests/run-make/lto-smoke-c/
 tests/run-make/return-non-c-like-enum/
-
+tests/run-make/short-ice

compiler/rustc_codegen_gcc/tests/failing-ui-tests-without-128bit-integers.txt

@@ -0,0 +1 @@
+tests/ui/simd/intrinsic/splat.rs

compiler/rustc_codegen_gcc/tests/failing-ui-tests.txt

@@ -89,11 +89,13 @@ tests/ui/thir-print/offset_of.rs
 tests/ui/iterators/rangefrom-overflow-debug.rs
 tests/ui/iterators/rangefrom-overflow-overflow-checks.rs
 tests/ui/iterators/iter-filter-count-debug-check.rs
-tests/ui/eii/codegen_single_crate.rs
-tests/ui/eii/codegen_cross_crate.rs
+tests/ui/eii/linking/codegen_single_crate.rs
+tests/ui/eii/linking/codegen_cross_crate.rs
 tests/ui/eii/default/local_crate.rs
-tests/ui/eii/multiple_impls.rs
+tests/ui/eii/duplicate/multiple_impls.rs
 tests/ui/eii/default/call_default.rs
-tests/ui/eii/same-symbol.rs
+tests/ui/eii/linking/same-symbol.rs
 tests/ui/eii/privacy1.rs
 tests/ui/eii/default/call_impl.rs
+tests/ui/c-variadic/copy.rs
+tests/ui/asm/x86_64/global_asm_escape.rs

compiler/rustc_codegen_gcc/tests/run/call-llvm-intrinsics.rs

@@ -0,0 +1,38 @@
+// Compiler:
+//
+// Run-time:
+//   status: 0
+
+// FIXME: Remove this test once rustc's `./tests/codegen/riscv-abi/call-llvm-intrinsics.rs`
+// stops ignoring GCC backend.
+
+#![feature(link_llvm_intrinsics)]
+#![allow(internal_features)]
+
+struct A;
+
+impl Drop for A {
+    fn drop(&mut self) {
+        println!("A");
+    }
+}
+
+extern "C" {
+    #[link_name = "llvm.sqrt.f32"]
+    fn sqrt(x: f32) -> f32;
+}
+
+pub fn do_call() {
+    let _a = A;
+
+    unsafe {
+        // Ensure that we `call` LLVM intrinsics instead of trying to `invoke` them
+        // CHECK: store float 4.000000e+00, float* %{{.}}, align 4
+        // CHECK: call float @llvm.sqrt.f32(float %{{.}}
+        sqrt(4.0);
+    }
+}
+
+fn main() {
+    do_call();
+}

compiler/rustc_codegen_gcc/tests/run/simd-ffi.rs

@@ -0,0 +1,102 @@
+// Compiler:
+//
+// Run-time:
+//   status: 0
+
+// FIXME: Remove this test once <tests/run-make/simd-ffi/simd.rs> stops
+// ignoring GCC backend.
+
+#![allow(internal_features, non_camel_case_types)]
+// we can compile to a variety of platforms, because we don't need
+// cross-compiled standard libraries.
+#![feature(no_core, auto_traits)]
+#![no_core]
+#![feature(repr_simd, simd_ffi, link_llvm_intrinsics, lang_items, rustc_attrs)]
+
+#[derive(Copy)]
+#[repr(simd)]
+pub struct f32x4([f32; 4]);
+
+extern "C" {
+    #[link_name = "llvm.sqrt.v4f32"]
+    fn vsqrt(x: f32x4) -> f32x4;
+}
+
+pub fn foo(x: f32x4) -> f32x4 {
+    unsafe { vsqrt(x) }
+}
+
+#[derive(Copy)]
+#[repr(simd)]
+pub struct i32x4([i32; 4]);
+
+extern "C" {
+    // _mm_sll_epi32
+    #[cfg(all(any(target_arch = "x86", target_arch = "x86-64"), target_feature = "sse2"))]
+    #[link_name = "llvm.x86.sse2.psll.d"]
+    fn integer(a: i32x4, b: i32x4) -> i32x4;
+
+    // vmaxq_s32
+    #[cfg(target_arch = "arm")]
+    #[link_name = "llvm.arm.neon.vmaxs.v4i32"]
+    fn integer(a: i32x4, b: i32x4) -> i32x4;
+    // vmaxq_s32
+    #[cfg(target_arch = "aarch64")]
+    #[link_name = "llvm.aarch64.neon.maxs.v4i32"]
+    fn integer(a: i32x4, b: i32x4) -> i32x4;
+
+    // Use a generic LLVM intrinsic to do type checking on other platforms
+    #[cfg(not(any(
+        all(any(target_arch = "x86", target_arch = "x86-64"), target_feature = "sse2"),
+        target_arch = "arm",
+        target_arch = "aarch64"
+    )))]
+    #[link_name = "llvm.smax.v4i32"]
+    fn integer(a: i32x4, b: i32x4) -> i32x4;
+}
+
+pub fn bar(a: i32x4, b: i32x4) -> i32x4 {
+    unsafe { integer(a, b) }
+}
+
+#[lang = "pointee_sized"]
+pub trait PointeeSized {}
+
+#[lang = "meta_sized"]
+pub trait MetaSized: PointeeSized {}
+
+#[lang = "sized"]
+pub trait Sized: MetaSized {}
+
+#[lang = "copy"]
+pub trait Copy {}
+
+impl Copy for f32 {}
+impl Copy for i32 {}
+impl Copy for [f32; 4] {}
+impl Copy for [i32; 4] {}
+
+pub mod marker {
+    pub use Copy;
+}
+
+#[lang = "freeze"]
+auto trait Freeze {}
+
+#[macro_export]
+#[rustc_builtin_macro]
+macro_rules! Copy {
+    () => {};
+}
+#[macro_export]
+#[rustc_builtin_macro]
+macro_rules! derive {
+    () => {};
+}
+
+#[lang = "start"]
+fn start<T>(_main: fn() -> T, _argc: isize, _argv: *const *const u8, _sigpipe: u8) -> isize {
+    0
+}
+
+fn main() {}

compiler/rustc_codegen_gcc/tests/run/unreachable-function.rs

@@ -0,0 +1,27 @@
+// Compiler:
+//
+// Run-time:
+//   status: 0
+
+use std::arch::asm;
+
+fn exit_syscall(status: i32) -> ! {
+    #[cfg(target_arch = "x86_64")]
+    unsafe {
+        asm!(
+            "syscall",
+            in("rax") 60,
+            in("rdi") status,
+            options(noreturn)
+        );
+    }
+
+    #[cfg(not(target_arch = "x86_64"))]
+    std::process::exit(status);
+}
+
+fn main() {
+    // Used to crash with rustc_codegen_gcc.
+    exit_syscall(0);
+    std::process::exit(1);
+}

compiler/rustc_codegen_gcc/tools/generate_intrinsics.py

@@ -12,7 +12,7 @@ def run_command(command, cwd=None):
         sys.exit(1)
 
 
-def clone_repository(repo_name, path, repo_url, branch="master", sub_paths=None):
+def clone_repository(repo_name, path, repo_url, sub_paths):
     if os.path.exists(path):
         while True:
             choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(path))
@@ -21,18 +21,15 @@ def clone_repository(repo_name, path, repo_url, branch="master", sub_paths=None)
                 return
             elif choice.lower() == "y":
                 print("Updating repository...")
-                run_command(["git", "pull", "origin", branch], cwd=path)
+                run_command(["git", "pull", "origin", "main"], cwd=path)
                 return
             else:
                 print("Didn't understand answer...")
     print("Cloning {} repository...".format(repo_name))
-    if sub_paths is None:
-        run_command(["git", "clone", repo_url, "--depth", "1", path])
-    else:
-        run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path])
-        run_command(["git", "sparse-checkout", "init"], cwd=path)
-        run_command(["git", "sparse-checkout", "set", *sub_paths], cwd=path)
-        run_command(["git", "checkout"], cwd=path)
+    run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path])
+    run_command(["git", "sparse-checkout", "init"], cwd=path)
+    run_command(["git", "sparse-checkout", "set", *sub_paths], cwd=path)
+    run_command(["git", "checkout"], cwd=path)
 
 
 def append_intrinsic(array, intrinsic_name, translation):
@@ -45,121 +42,36 @@ def convert_to_string(content):
     return content
 
 
-def extract_intrinsics_from_llvm(llvm_path, intrinsics):
-    command = ["llvm-tblgen", "llvm/IR/Intrinsics.td"]
+def extract_intrinsics_from_llvm(llvm_path):
+    intrinsics = {}
+    command = ["llvm-tblgen", "llvm/IR/Intrinsics.td", "--dump-json"]
     cwd = os.path.join(llvm_path, "llvm/include")
     print("=> Running command `{}` from `{}`".format(command, cwd))
     p = subprocess.Popen(command, cwd=cwd, stdout=subprocess.PIPE)
     output, err = p.communicate()
-    lines = convert_to_string(output).splitlines()
-    pos = 0
-    while pos < len(lines):
-        line = lines[pos]
-        if not line.startswith("def "):
-            pos += 1
+    content = json.loads(convert_to_string(output))
+    for intrinsic in content:
+        data = content[intrinsic]
+        if not isinstance(data, dict):
             continue
-        intrinsic = line.split(" ")[1].strip()
-        content = line
-        while pos < len(lines):
-            line = lines[pos].split(" // ")[0].strip()
-            content += line
-            pos += 1
-            if line == "}":
-                break
-        entries = re.findall('string ClangBuiltinName = "(\\w+)";', content)
-        current_arch = re.findall('string TargetPrefix = "(\\w+)";', content)
-        if len(entries) == 1 and len(current_arch) == 1:
-            current_arch = current_arch[0]
-            intrinsic = intrinsic.split("_")
-            if len(intrinsic) < 2 or intrinsic[0] != "int":
-                continue
-            intrinsic[0] = "llvm"
-            intrinsic = ".".join(intrinsic)
-            if current_arch not in intrinsics:
-                intrinsics[current_arch] = []
-            append_intrinsic(intrinsics[current_arch], intrinsic, entries[0])
-
-
-def append_translation(json_data, p, array):
-    it = json_data["index"][p]
-    content = it["docs"].split('`')
-    if len(content) != 5:
-        return
-    append_intrinsic(array, content[1], content[3])
-
-
-def extract_intrinsics_from_llvmint(llvmint, intrinsics):
-    archs = [
-        "AMDGPU",
-        "aarch64",
-        "arm",
-        "cuda",
-        "hexagon",
-        "mips",
-        "nvvm",
-        "ppc",
-        "ptx",
-        "x86",
-        "xcore",
-    ]
-
-    json_file = os.path.join(llvmint, "target/doc/llvmint.json")
-    # We need to regenerate the documentation!
-    run_command(
-        ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"],
-        cwd=llvmint,
-    )
-    with open(json_file, "r", encoding="utf8") as f:
-        json_data = json.loads(f.read())
-    for p in json_data["paths"]:
-        it = json_data["paths"][p]
-        if it["crate_id"] != 0:
-            # This is from an external crate.
+        current_arch = data.get("TargetPrefix")
+        builtin_name = data.get("ClangBuiltinName")
+        if current_arch is None or current_arch == "" or builtin_name is None:
             continue
-        if it["kind"] != "function":
-            # We're only looking for functions.
+        intrinsic = intrinsic.split("_")
+        if len(intrinsic) < 2 or intrinsic[0] != "int":
             continue
-        # if len(it["path"]) == 2:
-        #   # This is a "general" intrinsic, not bound to a specific arch.
-        #   append_translation(json_data, p, general)
-        #   continue
-        if len(it["path"]) != 3 or it["path"][1] not in archs:
-            continue
-        arch = it["path"][1]
-        if arch not in intrinsics:
-            intrinsics[arch] = []
-        append_translation(json_data, p, intrinsics[arch])
+        intrinsic[0] = "llvm"
+        intrinsic = ".".join(intrinsic)
+        if current_arch not in intrinsics:
+            intrinsics[current_arch] = []
+        append_intrinsic(intrinsics[current_arch], intrinsic, builtin_name)
+
+    return intrinsics
 
 
-def fill_intrinsics(intrinsics, from_intrinsics, all_intrinsics):
-    for arch in from_intrinsics:
-        if arch not in intrinsics:
-            intrinsics[arch] = []
-        for entry in from_intrinsics[arch]:
-            if entry[0] in all_intrinsics:
-                if all_intrinsics[entry[0]] == entry[1]:
-                    # This is a "full" duplicate, both the LLVM instruction and the GCC
-                    # translation are the same.
-                    continue
-                intrinsics[arch].append((entry[0], entry[1], True))
-            else:
-                intrinsics[arch].append((entry[0], entry[1], False))
-                all_intrinsics[entry[0]] = entry[1]
-
-
-def update_intrinsics(llvm_path, llvmint, llvmint2):
-    intrinsics_llvm = {}
-    intrinsics_llvmint = {}
-    all_intrinsics = {}
-
-    extract_intrinsics_from_llvm(llvm_path, intrinsics_llvm)
-    extract_intrinsics_from_llvmint(llvmint, intrinsics_llvmint)
-    extract_intrinsics_from_llvmint(llvmint2, intrinsics_llvmint)
-
-    intrinsics = {}
-    # We give priority to translations from LLVM over the ones from llvmint.
-    fill_intrinsics(intrinsics, intrinsics_llvm, all_intrinsics)
-    fill_intrinsics(intrinsics, intrinsics_llvmint, all_intrinsics)
+def update_intrinsics(llvm_path):
+    intrinsics = extract_intrinsics_from_llvm(llvm_path)
 
     archs = [arch for arch in intrinsics]
     archs.sort()
@@ -173,33 +85,41 @@ def update_intrinsics(llvm_path, llvmint, llvmint2):
     # Since all intrinsic names start with "llvm.", we skip that prefix.
     print("Updating content of `{}`...".format(output_file))
     with open(output_file, "w", encoding="utf8") as out:
-        out.write("// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`\n")
-        out.write("// DO NOT EDIT IT!\n")
-        out.write("/// Translate a given LLVM intrinsic name to an equivalent GCC one.\n")
-        out.write("fn map_arch_intrinsic(full_name:&str)->&'static str{\n")
-        out.write('let Some(name) = full_name.strip_prefix("llvm.") else { unimplemented!("***** unsupported LLVM intrinsic {}", full_name) };\n')
-        out.write('let Some((arch, name)) = name.split_once(\'.\') else { unimplemented!("***** unsupported LLVM intrinsic {}", name) };\n')
-        out.write("match arch {\n")
+        out.write("""// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`
+// DO NOT EDIT IT!
+/// Translate a given LLVM intrinsic name to an equivalent GCC one.
+fn map_arch_intrinsic(full_name:&str)-> &'static str {
+    let Some(name) = full_name.strip_prefix("llvm.") else { unimplemented!("***** unsupported LLVM intrinsic {}", full_name) };
+    let Some((arch, name)) = name.split_once('.') else { unimplemented!("***** unsupported LLVM intrinsic llvm.{}", name) };
+    let old_arch_res = old_archs(arch, name);
+    if let ArchCheckResult::Ok(res) = old_arch_res {
+        return res;
+    }
+match arch {""")
         for arch in archs:
             if len(intrinsics[arch]) == 0:
                 continue
             attribute = "#[expect(non_snake_case)]" if arch[0].isupper() else ""
             out.write("\"{}\" => {{ {} fn {}(name: &str,full_name:&str) -> &'static str {{ match name {{".format(arch, attribute, arch))
-            intrinsics[arch].sort(key=lambda x: (x[0], x[2]))
+            intrinsics[arch].sort(key=lambda x: (x[0], x[1]))
             out.write('    // {}\n'.format(arch))
             for entry in intrinsics[arch]:
                 llvm_name = entry[0].removeprefix("llvm.");
                 llvm_name = llvm_name.removeprefix(arch);
                 llvm_name = llvm_name.removeprefix(".");
-                if entry[2] is True: # if it is a duplicate
-                    out.write('    // [DUPLICATE]: "{}" => "{}",\n'.format(llvm_name, entry[1]))
-                elif "_round_mask" in entry[1]:
+                if "_round_mask" in entry[1]:
                     out.write('    // [INVALID CONVERSION]: "{}" => "{}",\n'.format(llvm_name, entry[1]))
                 else:
                     out.write('    "{}" => "{}",\n'.format(llvm_name, entry[1]))
             out.write('    _ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),\n')
             out.write("}} }} {}(name,full_name) }}\n,".format(arch))
-        out.write('    _ => unimplemented!("***** unsupported LLVM architecture {arch}, intrinsic:{full_name}"),\n')
+        out.write("""    _ => {
+        match old_arch_res {
+            ArchCheckResult::UnknownIntrinsic => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
+            ArchCheckResult::UnknownArch => unimplemented!("***** unsupported LLVM architecture {arch}, intrinsic: {full_name}"),
+            ArchCheckResult::Ok(_) => unreachable!(),
+        }
+    }""")
         out.write("}\n}")
     subprocess.call(["rustfmt", output_file])
     print("Done!")
@@ -210,35 +130,21 @@ def main():
         os.path.dirname(os.path.abspath(__file__)),
         "llvm-project",
     )
-    llvmint_path = os.path.join(
-        os.path.dirname(os.path.abspath(__file__)),
-        "llvmint",
-    )
-    llvmint2_path = os.path.join(
-        os.path.dirname(os.path.abspath(__file__)),
-        "llvmint-2",
-    )
 
     # First, we clone the LLVM repository if it's not already here.
     clone_repository(
         "llvm-project",
         llvm_path,
         "https://github.com/llvm/llvm-project",
-        branch="main",
-        sub_paths=["llvm/include/llvm/IR", "llvm/include/llvm/CodeGen/"],
+        ["llvm/include/llvm/IR", "llvm/include/llvm/CodeGen/"],
     )
-    clone_repository(
-        "llvmint",
-        llvmint_path,
-        "https://github.com/GuillaumeGomez/llvmint",
-    )
-    clone_repository(
-        "llvmint2",
-        llvmint2_path,
-        "https://github.com/antoyo/llvmint",
-    )
-    update_intrinsics(llvm_path, llvmint_path, llvmint2_path)
+    update_intrinsics(llvm_path)
 
+# llvm-tblgen can be built with:
+#
+# mkdir llvm-tblgen-build && cd llvm-tblgen-build
+# cmake -G Ninja  -DLLVM_ENABLE_PROJECTS="llvm"  -DCMAKE_BUILD_TYPE=Release  ../llvm
+# ninja llvm-tblgen
 
 if __name__ == "__main__":
     sys.exit(main())