Mirrors/rust
1
0
Fork 0
mirror of https://github.com/rust-lang/rust.git synced 2026-04-30 06:43:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1919 from sayantn/fix-vreinterpret

Browse Source 
Remove big-endian swizzles from `vreinterpret`
This commit is contained in:
Folkert de Vries
2025-09-15 08:18:20 +00:00
committed by GitHub
parent 33387434c5 bb31725e67
commit 5dd0fdcd67
4 changed files with 6 additions and 9286 deletions
Download Patch File Download Diff File Expand all files Collapse all files
library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
-811
View File
@@ -21477,7 +21477,6 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
@@ -21486,21 +21485,8 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
@@ -21509,24 +21495,8 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
@@ -21535,23 +21505,8 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
@@ -21560,24 +21515,8 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21585,22 +21524,8 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21608,20 +21533,8 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21629,20 +21542,8 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21650,23 +21551,8 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21674,23 +21560,8 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21698,22 +21569,8 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21721,22 +21578,8 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21744,22 +21587,8 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21767,19 +21596,6 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -21791,7 +21607,6 @@ pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21799,22 +21614,8 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21822,22 +21623,8 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21845,19 +21632,6 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -21869,7 +21643,6 @@ pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21877,22 +21650,8 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21900,19 +21659,6 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -21924,7 +21670,6 @@ pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21932,20 +21677,8 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21953,23 +21686,8 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -21977,27 +21695,8 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22005,23 +21704,8 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22029,23 +21713,8 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22053,23 +21722,8 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22077,27 +21731,8 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22105,23 +21740,8 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22129,23 +21749,8 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22153,23 +21758,8 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22177,27 +21767,8 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22205,23 +21776,8 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22229,23 +21785,8 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
let a: float64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22253,20 +21794,8 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22274,24 +21803,8 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22299,20 +21812,8 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22320,23 +21821,8 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22344,20 +21830,8 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22365,20 +21839,6 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -22399,7 +21859,6 @@ pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22407,23 +21866,8 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22431,23 +21875,8 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22455,20 +21884,8 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22476,24 +21893,8 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22501,20 +21902,8 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22522,23 +21911,8 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22546,20 +21920,8 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22567,20 +21929,6 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -22601,7 +21949,6 @@ pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22609,23 +21956,8 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22633,23 +21965,8 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22657,20 +21974,8 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22678,24 +21983,8 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22703,20 +21992,8 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22724,23 +22001,8 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22748,19 +22010,6 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -22790,7 +22039,6 @@ pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22798,23 +22046,8 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22822,23 +22055,8 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
@@ -22846,43 +22064,14 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
#[inline]
library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
-8475
View File
@@ -42089,7 +42089,6 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42103,29 +42102,8 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42139,29 +42117,8 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42175,29 +42132,8 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42211,29 +42147,8 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42247,26 +42162,8 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42280,29 +42177,8 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42316,29 +42192,8 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42352,29 +42207,8 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42388,26 +42222,8 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42421,29 +42237,8 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42457,29 +42252,8 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42493,29 +42267,8 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42529,33 +42282,8 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42569,29 +42297,8 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42605,29 +42312,8 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42641,29 +42327,8 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42677,33 +42342,8 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42717,29 +42357,8 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42753,29 +42372,8 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42789,29 +42387,8 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42825,33 +42402,8 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42865,29 +42417,8 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42901,29 +42432,8 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42937,29 +42447,8 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -42973,29 +42462,8 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43009,30 +42477,8 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43046,29 +42492,8 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43082,29 +42507,8 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43118,29 +42522,8 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43154,29 +42537,8 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43190,28 +42552,8 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43225,29 +42567,8 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43261,29 +42582,8 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43297,30 +42597,8 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43334,29 +42612,8 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43370,29 +42627,8 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43406,29 +42642,8 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43442,29 +42657,8 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43478,28 +42672,8 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43513,29 +42687,8 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43549,29 +42702,8 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43585,30 +42717,8 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43622,29 +42732,8 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43658,29 +42747,8 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43694,28 +42762,8 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43729,26 +42777,8 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43762,26 +42792,8 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43795,29 +42807,8 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43831,28 +42822,8 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
unsafe {
let ret_val: float16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
@@ -43866,29 +42837,8 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43908,34 +42858,8 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43955,35 +42879,8 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44003,35 +42900,8 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44051,35 +42921,8 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44099,32 +42942,8 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44144,35 +42963,8 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44192,35 +42984,8 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44240,35 +43005,8 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44288,32 +43026,8 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44333,35 +43047,8 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44381,35 +43068,8 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44429,32 +43089,8 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44474,39 +43110,8 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44526,35 +43131,8 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44574,35 +43152,8 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44622,35 +43173,8 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44670,39 +43194,8 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44722,35 +43215,8 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44770,35 +43236,8 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44818,35 +43257,8 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44866,39 +43278,8 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44918,35 +43299,8 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44966,35 +43320,8 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45014,35 +43341,8 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45062,35 +43362,8 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45110,32 +43383,8 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45155,35 +43404,8 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45203,35 +43425,8 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45251,35 +43446,8 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45299,32 +43467,8 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45344,35 +43488,8 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45392,35 +43509,8 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45440,36 +43530,8 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45489,36 +43551,8 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45538,36 +43572,8 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45587,36 +43593,8 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45636,40 +43614,8 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45689,36 +43635,8 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45738,36 +43656,8 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45787,36 +43677,8 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45836,40 +43698,8 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45889,36 +43719,8 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45938,35 +43740,8 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45986,35 +43761,8 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46034,35 +43782,8 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46082,32 +43803,8 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46127,35 +43824,8 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46175,35 +43845,8 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46223,35 +43866,8 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46271,32 +43887,8 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46316,35 +43908,8 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46364,35 +43929,8 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46412,35 +43950,8 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46460,39 +43971,8 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46512,35 +43992,8 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46560,35 +44013,8 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46608,39 +44034,8 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46660,35 +44055,8 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46708,35 +44076,8 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46756,35 +44097,8 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46804,39 +44118,8 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46856,35 +44139,8 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46904,35 +44160,8 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -46952,35 +44181,8 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47000,35 +44202,8 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47048,32 +44223,8 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47093,35 +44244,8 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47141,35 +44265,8 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47189,35 +44286,8 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47237,32 +44307,8 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47282,35 +44328,8 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47330,35 +44349,8 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47378,35 +44370,8 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47426,39 +44391,8 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47478,35 +44412,8 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47526,35 +44433,8 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47574,39 +44454,8 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47626,35 +44475,8 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47674,35 +44496,8 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47722,35 +44517,8 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47770,39 +44538,8 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47822,35 +44559,8 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47870,34 +44580,8 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47917,34 +44601,8 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -47964,34 +44622,8 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48011,34 +44643,8 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48058,34 +44664,8 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48105,34 +44685,8 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48152,31 +44706,6 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -48200,7 +44729,6 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48220,34 +44748,8 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48267,34 +44769,8 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48314,35 +44790,8 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48362,39 +44811,8 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48414,35 +44832,8 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48462,35 +44853,8 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48510,39 +44874,8 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48562,35 +44895,8 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48610,35 +44916,8 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48658,35 +44937,8 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48706,39 +44958,8 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48758,35 +44979,8 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48806,35 +45000,8 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48854,35 +45021,8 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48902,35 +45042,8 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48950,35 +45063,8 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -48998,32 +45084,8 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49043,35 +45105,8 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49091,35 +45126,8 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49139,32 +45147,8 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49184,35 +45168,8 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49232,35 +45189,8 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49280,36 +45210,8 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49329,40 +45231,8 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49382,36 +45252,8 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49431,36 +45273,8 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49480,36 +45294,8 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49529,36 +45315,8 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49578,36 +45336,8 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49627,36 +45357,8 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49676,40 +45378,8 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49729,36 +45399,8 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49778,35 +45420,8 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49826,35 +45441,8 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49874,35 +45462,8 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49922,35 +45483,8 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49970,32 +45504,8 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50015,35 +45525,8 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50063,35 +45546,8 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50111,32 +45567,8 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50156,35 +45588,8 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50204,35 +45609,8 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50252,35 +45630,8 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50300,39 +45651,8 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50352,35 +45672,8 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50400,35 +45693,8 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50448,35 +45714,8 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50496,39 +45735,8 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50548,35 +45756,8 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50596,35 +45777,8 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50644,39 +45798,8 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50696,35 +45819,8 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50744,35 +45840,8 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50792,35 +45861,8 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50840,35 +45882,8 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50888,35 +45903,8 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50936,32 +45924,8 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -50981,35 +45945,8 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51029,35 +45966,8 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51077,32 +45987,8 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51122,35 +46008,8 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51170,35 +46029,8 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51218,35 +46050,8 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51266,39 +46071,8 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51318,35 +46092,8 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51366,35 +46113,8 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51414,35 +46134,8 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51462,39 +46155,8 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51514,35 +46176,8 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51562,35 +46197,8 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51610,39 +46218,8 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51662,35 +46239,8 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51710,34 +46260,8 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51757,34 +46281,8 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51804,34 +46302,8 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51851,31 +46323,6 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
@@ -51899,7 +46346,6 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51919,34 +46365,8 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -51966,34 +46386,8 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52013,34 +46407,8 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52060,34 +46428,8 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52107,34 +46449,8 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52154,35 +46470,8 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52202,39 +46491,8 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52254,35 +46512,8 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52302,35 +46533,8 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52350,35 +46554,8 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52398,39 +46575,8 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52450,35 +46596,8 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52498,35 +46617,8 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52546,39 +46638,8 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52598,35 +46659,8 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52646,35 +46680,8 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52694,35 +46701,8 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52742,35 +46722,8 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52790,35 +46743,8 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52838,32 +46764,8 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52883,35 +46785,8 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52931,35 +46806,8 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -52979,35 +46827,8 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53027,32 +46848,8 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53072,35 +46869,8 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53120,36 +46890,8 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53169,40 +46911,8 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53222,36 +46932,8 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53271,36 +46953,8 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53320,36 +46974,8 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53369,40 +46995,8 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53422,36 +47016,8 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53471,36 +47037,8 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53520,36 +47058,8 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53569,36 +47079,8 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53618,35 +47100,8 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: float32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53666,35 +47121,8 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53714,35 +47142,8 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53762,35 +47163,8 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53810,32 +47184,8 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53855,35 +47205,8 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53903,35 +47226,8 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53951,35 +47247,8 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53999,32 +47268,8 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54044,35 +47289,8 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54092,35 +47310,8 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: float32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54140,39 +47331,8 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54192,35 +47352,8 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54240,35 +47373,8 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54288,35 +47394,8 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54336,39 +47415,8 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54388,35 +47436,8 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54436,35 +47457,8 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54484,35 +47478,8 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54532,39 +47499,8 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54584,38 +47520,8 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54635,34 +47541,8 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54682,34 +47562,8 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54729,34 +47583,8 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
unsafe {
let ret_val: int64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54776,38 +47604,8 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54827,34 +47625,8 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54874,34 +47646,8 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54921,34 +47667,8 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
unsafe {
let ret_val: uint64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -54968,38 +47688,8 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55019,34 +47709,8 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55066,34 +47730,8 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55113,32 +47751,8 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55158,33 +47772,8 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55204,36 +47793,8 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
let a: int8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55253,32 +47814,8 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55298,32 +47835,8 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55343,35 +47856,8 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55391,32 +47877,8 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55436,32 +47898,8 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55481,35 +47919,8 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55529,32 +47940,8 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55574,32 +47961,8 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55619,33 +47982,8 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55665,36 +48003,8 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
let a: uint8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55714,32 +48024,8 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55759,32 +48045,8 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55804,35 +48066,8 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55852,32 +48087,8 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55897,32 +48108,8 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55942,35 +48129,8 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -55990,32 +48150,8 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56035,32 +48171,8 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56080,33 +48192,8 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56126,36 +48213,8 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
let a: poly8x16_t =
unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56175,32 +48234,8 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56220,32 +48255,8 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56265,35 +48276,8 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
unsafe {
let ret_val: poly64x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56313,34 +48297,8 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
unsafe {
let ret_val: int8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56360,34 +48318,8 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
unsafe {
let ret_val: int16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56407,34 +48339,8 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
unsafe {
let ret_val: int32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56454,34 +48360,8 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
unsafe {
let ret_val: uint8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56501,34 +48381,8 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
unsafe {
let ret_val: uint16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56548,34 +48402,8 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
unsafe {
let ret_val: uint32x2_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56595,34 +48423,8 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
unsafe {
let ret_val: poly8x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56642,34 +48444,8 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
unsafe {
let ret_val: poly16x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56689,32 +48465,8 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56734,39 +48486,8 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56786,35 +48507,8 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56834,35 +48528,8 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: int32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56882,39 +48549,8 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56934,35 +48570,8 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -56982,35 +48591,8 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: uint32x4_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -57030,39 +48612,8 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly8x16_t = transmute(a);
simd_shuffle!(
ret_val,
ret_val,
[15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
)
}
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
#[inline]
#[cfg(target_endian = "little")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -57081,32 +48632,6 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
unsafe { transmute(a) }
}
#[doc = "Vector reinterpret cast operation"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
#[inline]
#[cfg(target_endian = "big")]
#[target_feature(enable = "neon,aes")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
assert_instr(nop)
)]
#[cfg_attr(
not(target_arch = "arm"),
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
target_arch = "arm",
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
unsafe {
let ret_val: poly16x8_t = transmute(a);
simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
}
}
#[doc = "Reversing vector elements (swap endianness)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
#[inline]
library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+2
View File
@@ -8781,6 +8781,7 @@ intrinsics:
- [float64x1_t, float32x2_t]
- [float32x4_t, float64x2_t]
- [float64x2_t, float32x4_t]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]
@@ -8801,6 +8802,7 @@ intrinsics:
# q
- [float64x2_t, float16x8_t]
- [float16x8_t, float64x2_t]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]
library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+4
View File
@@ -8480,6 +8480,7 @@ intrinsics:
- [poly16x8_t, p128]
- [int8x16_t, p128]
- [uint8x16_t, p128]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]
@@ -8717,6 +8718,7 @@ intrinsics:
- [poly8x16_t, float32x4_t]
- [poly16x8_t, float32x4_t]
- [p128, float32x4_t]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]
@@ -8780,6 +8782,7 @@ intrinsics:
- [float16x8_t, uint16x8_t]
- [float16x8_t, uint32x4_t]
- [float16x8_t, uint64x2_t]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]
@@ -8804,6 +8807,7 @@ intrinsics:
- [poly128_t, float16x8_t]
- [float16x8_t, poly128_t]
- [float16x8_t, poly64x2_t]
big_endian_inverse: false
compose:
- FnCall: [transmute, [a]]