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Rollup merge of #155856 - imazen:winarm-stable-features, r=Amanieu
std_detect: support detecting more features on aarch64 Windows Wires `IsProcessorFeaturePresent` calls for the `PF_ARM_*` constants exposed in Windows SDK 26100 (Windows 11 24H2), plus an architectural derivation for `rdm`. All eight feature names have been stable in `is_aarch64_feature_detected!` on Linux/Darwin/BSD since Rust 1.60 — this brings the Windows backend to parity. | Feature | Source on Windows | |---|---| | `fp16` | `PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE` (value 67) | | `i8mm` | `PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE` (value 66) | | `bf16` | `PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE` (value 68) | | `sha3` | `PF_ARM_SHA3` (value 64) **AND** `PF_ARM_SHA512` (value 65) | | `lse2` | `PF_ARM_LSE2_AVAILABLE` (value 62) | | `f32mm` | `PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE` (value 58) | | `f64mm` | `PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE` (value 59) | | `rdm` | derived from `PF_ARM_V82_DP` (see below) | `PF_ARM_SVE_F32MM` / `PF_ARM_SVE_F64MM` (values 58 / 59) were already added as commented-out placeholders in rust-lang/stdarch#1749 — they have direct stable Feature mappings (`f32mm`, `f64mm`), unlike their sibling values 52 / 53 / 57 (`SVE_BF16`, `SVE_EBF16`, `SVE_I8MM`) which have no SVE-specific stdarch Feature name and remain commented for that reason. `sha3` requires both `PF_ARM_SHA3` (FEAT_SHA3) and `PF_ARM_SHA512` (FEAT_SHA512), matching the existing convention from rust-lang/stdarch#1749 where `sve2-aes` is set only when both `PF_ARM_SVE_AES` and `PF_ARM_SVE_PMULL128` are present. ### `rdm` derivation There is no `PF_ARM_RDM_*` constant; Microsoft has never defined one. We derive it from `PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE` (FEAT_DotProd) via the following architectural chain: 1. FEAT_DotProd is an optional v8.2-A feature, so its presence implies the core implements at least v8.1-A. 2. Per Arm ARM K.a §D17.2.91: *"In an ARMv8.1 implementation, if FEAT_AdvSIMD is implemented, FEAT_RDM is implemented."* 3. AdvSIMD is universally implemented on every Windows-on-ARM SKU. 4. Therefore: DotProd ⇒ v8.1-A baseline + AdvSIMD ⇒ FEAT_RDM. This is the same derivation .NET 10 uses, with comment cited verbatim ([dotnet/runtime PR 109493](https://github.com/dotnet/runtime/pull/109493), shipped in v10.0.0 at [`src/native/minipal/cpufeatures.c`](https://github.com/dotnet/runtime/blob/v10.0.0/src/native/minipal/cpufeatures.c)): > *"IsProcessorFeaturePresent does not have a dedicated flag for RDM, so we enable it by implication. > 1) DP is an optional instruction set for Armv8.2, which may be included only in processors implementing at least Armv8.1. > 2) Armv8.1 requires RDM when AdvSIMD is implemented, and AdvSIMD is a baseline requirement of .NET. > Therefore, by documented standard, DP cannot exist here without RDM. In practice, there is only one CPU supported by Windows that includes RDM without DP, so this implication also has little practical chance of a false negative."* The "one CPU with RDM without DP" trade-off applies equally to us: we accept a possible false negative on that single SKU rather than introducing a more aggressive heuristic. ### Tests Adds `println!` lines to the existing `aarch64_windows()` test in `library/std_detect/tests/cpu-detection.rs` for each newly-detected feature, mirroring the existing single-line pattern. No structural assertions added. ### Scope Stable feature names only. The unstable SME family (`sme`, `sme2`, `sme2p1`, `sme_*`, `ssve_fp8*`) and other unstable additions tracked under rust-lang/rust#127764 are intentionally out of scope here to keep this PR minimal — happy to do a follow-up. ### References - Tracking issue: rust-lang/rust#127764 (`stdarch_aarch64_feature_detection`) - Precedent: rust-lang/stdarch#1749 (taiki-e, merged 2025-03-24) — added the SVE constants this builds on - MS docs: [`IsProcessorFeaturePresent`](https://learn.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent) — full PF_ARM_* table r? @Amanieu cc @taiki-e (author of rust-lang/stdarch#1749, would appreciate your eyes on the `rdm` inference) @rustbot label +T-libs +O-windows +O-ARM
This commit is contained in:
Jonathan Brouwer
@@ -31,8 +31,14 @@ pub(crate) fn detect_features() -> cache::Initializer {
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const PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 55;
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const PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE: u32 = 56;
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// const PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 57;
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// const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58;
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// const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59;
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const PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE: u32 = 58;
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const PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE: u32 = 59;
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const PF_ARM_LSE2_AVAILABLE: u32 = 62;
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const PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE: u32 = 64;
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const PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE: u32 = 65;
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const PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE: u32 = 66;
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const PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE: u32 = 67;
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const PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE: u32 = 68;
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unsafe extern "system" {
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fn IsProcessorFeaturePresent(ProcessorFeature: DWORD) -> BOOL;
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@@ -46,9 +52,11 @@ pub(crate) fn detect_features() -> cache::Initializer {
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}
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};
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// Some features may be supported on current CPU,
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// but no way to detect it by OS API.
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// Also, we require unsafe block for the extern "system" calls.
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// Some features may be supported on the current CPU but have no
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// detection path through the Win32 API; those report `false`.
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// SAFETY: `IsProcessorFeaturePresent` is a Win32 entry point taking a
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// `DWORD` by value and returning a `BOOL`. No pointer parameters,
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// no out-parameters, no thread-safety constraints.
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unsafe {
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enable_feature(
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Feature::fp,
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@@ -112,6 +120,46 @@ pub(crate) fn detect_features() -> cache::Initializer {
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Feature::sve2_sm4,
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IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::f32mm,
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IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::f64mm,
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IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::lse2,
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IsProcessorFeaturePresent(PF_ARM_LSE2_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::fp16,
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IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::i8mm,
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IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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enable_feature(
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Feature::bf16,
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IsProcessorFeaturePresent(PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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// stdarch `sha3` is FEAT_SHA3 + FEAT_SHA512 together; Windows
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// exposes them as two separate flags.
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enable_feature(
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Feature::sha3,
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IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE) != FALSE
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&& IsProcessorFeaturePresent(PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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// No PF_ARM_RDM_* constant exists. Derive FEAT_RDM from FEAT_DotProd:
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// DotProd is an optional v8.2-A feature only present on cores that
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// implement at least v8.1-A; v8.1-A with AdvSIMD mandates FEAT_RDM
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// (Arm ARM K.a §D17.2.91), and AdvSIMD is universal on Windows-on-ARM.
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// Same inference shipped in .NET 10 (dotnet/runtime PR 109493).
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enable_feature(
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Feature::rdm,
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IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != FALSE,
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);
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// PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE means aes, sha1, sha2 and
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// pmull support
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let crypto =
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@@ -150,14 +150,22 @@ fn aarch64_linux() {
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fn aarch64_windows() {
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println!("asimd: {:?}", is_aarch64_feature_detected!("asimd"));
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println!("fp: {:?}", is_aarch64_feature_detected!("fp"));
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println!("fp16: {:?}", is_aarch64_feature_detected!("fp16"));
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println!("crc: {:?}", is_aarch64_feature_detected!("crc"));
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println!("lse: {:?}", is_aarch64_feature_detected!("lse"));
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println!("lse2: {:?}", is_aarch64_feature_detected!("lse2"));
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println!("rdm: {:?}", is_aarch64_feature_detected!("rdm"));
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println!("dotprod: {:?}", is_aarch64_feature_detected!("dotprod"));
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println!("i8mm: {:?}", is_aarch64_feature_detected!("i8mm"));
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println!("bf16: {:?}", is_aarch64_feature_detected!("bf16"));
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println!("jsconv: {:?}", is_aarch64_feature_detected!("jsconv"));
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println!("rcpc: {:?}", is_aarch64_feature_detected!("rcpc"));
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println!("aes: {:?}", is_aarch64_feature_detected!("aes"));
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println!("pmull: {:?}", is_aarch64_feature_detected!("pmull"));
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println!("sha2: {:?}", is_aarch64_feature_detected!("sha2"));
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println!("sha3: {:?}", is_aarch64_feature_detected!("sha3"));
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println!("f32mm: {:?}", is_aarch64_feature_detected!("f32mm"));
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println!("f64mm: {:?}", is_aarch64_feature_detected!("f64mm"));
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}
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#[test]
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