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gen-arm: skip assert_instr on big-endian

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Some intrinsics optimise to different instructions on big endian which
leads to `assert_instr` failing
This commit is contained in:
David Wood
2026-05-01 12:26:25 +01:00
committed by sayantn
parent 51f8123fa7
commit 3d5f588f83
4 changed files with 1297 additions and 534 deletions
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library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+951 -372
View File
@@ -65,7 +65,10 @@ pub fn __jcvt(a: f64) -> i32 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(sabal2)
)]
pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
unsafe {
let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -80,7 +83,10 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(sabal2)
)]
pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
unsafe {
let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -95,7 +101,10 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(sabal2)
)]
pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
unsafe {
let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -110,7 +119,10 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uabal2)
)]
pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
unsafe {
let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -124,7 +136,10 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uabal2)
)]
pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
unsafe {
let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -138,7 +153,10 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uabal2)
)]
pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
unsafe {
let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -212,7 +230,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -226,7 +244,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -240,7 +258,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sabdl2))]
pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -253,8 +271,8 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -266,8 +284,8 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -279,8 +297,8 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uabdl2))]
pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -4092,7 +4110,10 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
@@ -4113,7 +4134,10 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
@@ -4137,7 +4161,10 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
@@ -4157,7 +4184,10 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
@@ -4175,7 +4205,10 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
@@ -4199,7 +4232,10 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -4222,7 +4258,10 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -4243,7 +4282,10 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
@@ -4267,7 +4309,10 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -4290,7 +4335,10 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -4312,7 +4360,10 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
@@ -4338,7 +4389,10 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -4362,7 +4416,10 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -4384,7 +4441,10 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -4413,7 +4473,10 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -4437,7 +4500,10 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -4459,7 +4525,10 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -4488,7 +4557,10 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -4536,7 +4608,10 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 1, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
@@ -4558,7 +4633,10 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 1, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
@@ -4580,7 +4658,10 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 1, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
@@ -4602,7 +4683,10 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 1, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
@@ -4624,7 +4708,10 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
@@ -4994,7 +5081,10 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
@@ -5022,7 +5112,10 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
@@ -5046,7 +5139,10 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
@@ -5419,7 +5515,10 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
@@ -5447,7 +5546,10 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
@@ -5471,7 +5573,10 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
@@ -5844,7 +5949,10 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
@@ -5872,7 +5980,10 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
@@ -5895,7 +6006,10 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
@@ -5916,7 +6030,10 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
@@ -6287,7 +6404,10 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
@@ -6314,7 +6434,10 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
@@ -6337,7 +6460,10 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
@@ -6358,7 +6484,10 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
@@ -6729,7 +6858,10 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
@@ -6756,7 +6888,10 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
@@ -6779,7 +6914,10 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
@@ -6800,7 +6938,10 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
@@ -7171,7 +7312,10 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
@@ -7198,7 +7342,10 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[cfg_attr(
all(test, target_endian = "little"),
assert_instr(mov, LANE1 = 0, LANE2 = 0)
)]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
@@ -7228,7 +7375,7 @@ pub fn vcreate_f64(a: u64) -> float64x1_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
unsafe { simd_cast(a) }
@@ -7282,7 +7429,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
@@ -7292,7 +7439,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
@@ -7302,7 +7449,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
@@ -7311,7 +7458,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
unsafe {
@@ -9459,7 +9606,7 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtxn))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
unsafe extern "unadjusted" {
@@ -9475,7 +9622,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtxn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fcvtxn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) }
@@ -10260,7 +10407,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfma_laneq_f64<const LANE: i32>(
@@ -10327,7 +10474,7 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
#[doc = "Floating-point fused multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10342,7 +10489,7 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
#[doc = "Floating-point fused multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10391,7 +10538,7 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -10405,7 +10552,7 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -10419,7 +10566,7 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmadd, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
@@ -11015,7 +11162,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfms_laneq_f64<const LANE: i32>(
@@ -11068,7 +11215,7 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11083,7 +11230,7 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11135,7 +11282,7 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
@@ -11145,7 +11292,7 @@ pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
@@ -11155,7 +11302,7 @@ pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
@@ -11165,7 +11312,7 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(fmsub, LANE = 0))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
@@ -14210,7 +14357,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -14221,7 +14368,7 @@ pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_laneq_s16<const LANE: i32>(
@@ -14236,7 +14383,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -14247,7 +14394,7 @@ pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_laneq_s32<const LANE: i32>(
@@ -14262,7 +14409,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_lane_u16<const LANE: i32>(
@@ -14277,7 +14424,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_laneq_u16<const LANE: i32>(
@@ -14292,7 +14439,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_lane_u32<const LANE: i32>(
@@ -14307,7 +14454,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_laneq_u32<const LANE: i32>(
@@ -14322,7 +14469,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
vmlal_high_s16(a, b, vdupq_n_s16(c))
@@ -14331,7 +14478,7 @@ pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
vmlal_high_s32(a, b, vdupq_n_s32(c))
@@ -14340,7 +14487,7 @@ pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
vmlal_high_u16(a, b, vdupq_n_u16(c))
@@ -14349,7 +14496,7 @@ pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
vmlal_high_u32(a, b, vdupq_n_u32(c))
@@ -14358,7 +14505,7 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
unsafe {
@@ -14371,7 +14518,7 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
unsafe {
@@ -14384,7 +14531,7 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
unsafe {
@@ -14397,7 +14544,7 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
unsafe {
@@ -14410,7 +14557,7 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
unsafe {
@@ -14423,7 +14570,7 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
unsafe {
@@ -14454,7 +14601,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -14465,7 +14612,7 @@ pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_laneq_s16<const LANE: i32>(
@@ -14480,7 +14627,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -14491,7 +14638,7 @@ pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_laneq_s32<const LANE: i32>(
@@ -14506,7 +14653,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_lane_u16<const LANE: i32>(
@@ -14521,7 +14668,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_laneq_u16<const LANE: i32>(
@@ -14536,7 +14683,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_lane_u32<const LANE: i32>(
@@ -14551,7 +14698,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2, LANE = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_laneq_u32<const LANE: i32>(
@@ -14566,7 +14713,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
vmlsl_high_s16(a, b, vdupq_n_s16(c))
@@ -14575,7 +14722,7 @@ pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
vmlsl_high_s32(a, b, vdupq_n_s32(c))
@@ -14584,7 +14731,7 @@ pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
vmlsl_high_u16(a, b, vdupq_n_u16(c))
@@ -14593,7 +14740,7 @@ pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
vmlsl_high_u32(a, b, vdupq_n_u32(c))
@@ -14602,7 +14749,7 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
unsafe {
@@ -14615,7 +14762,7 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
unsafe {
@@ -14628,7 +14775,7 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
unsafe {
@@ -14641,7 +14788,7 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
unsafe {
@@ -14654,7 +14801,7 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
unsafe {
@@ -14667,7 +14814,7 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
unsafe {
@@ -14681,7 +14828,7 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
unsafe {
let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -14693,7 +14840,7 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
unsafe {
let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -14705,7 +14852,7 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sxtl2))]
pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
unsafe {
let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -14717,7 +14864,7 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(uxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
unsafe {
let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -14729,7 +14876,7 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(uxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
unsafe {
let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -14741,7 +14888,7 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(uxtl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uxtl2))]
pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
unsafe {
let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -14753,7 +14900,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
unsafe {
let c: int8x8_t = simd_cast(b);
@@ -14765,7 +14912,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
unsafe {
let c: int16x4_t = simd_cast(b);
@@ -14777,7 +14924,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
unsafe {
let c: int32x2_t = simd_cast(b);
@@ -14789,7 +14936,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
unsafe {
let c: uint8x8_t = simd_cast(b);
@@ -14801,7 +14948,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
unsafe {
let c: uint16x4_t = simd_cast(b);
@@ -14813,7 +14960,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(xtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(xtn2))]
pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
unsafe {
let c: uint32x2_t = simd_cast(b);
@@ -14960,7 +15107,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
@@ -14971,7 +15118,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
@@ -14982,7 +15129,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
@@ -14993,7 +15140,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
@@ -15004,7 +15151,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t {
@@ -15015,7 +15162,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
@@ -15026,7 +15173,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t {
@@ -15037,7 +15184,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2, LANE = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2, LANE = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
@@ -15048,7 +15195,7 @@ pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> ui
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
vmull_high_s16(a, vdupq_n_s16(b))
@@ -15057,7 +15204,7 @@ pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(smull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
vmull_high_s32(a, vdupq_n_s32(b))
@@ -15066,7 +15213,7 @@ pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
vmull_high_u16(a, vdupq_n_u16(b))
@@ -15075,7 +15222,7 @@ pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(umull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
vmull_high_u32(a, vdupq_n_u32(b))
@@ -15085,7 +15232,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon,aes")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(pmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) }
}
@@ -15094,7 +15241,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(pmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))]
pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
unsafe {
let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15107,7 +15254,7 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(smull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
unsafe {
let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15120,7 +15267,7 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(smull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -15133,7 +15280,7 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(smull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(smull2))]
pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -15146,7 +15293,7 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(umull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -15159,7 +15306,7 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(umull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -15172,7 +15319,7 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(umull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(umull2))]
pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -16684,7 +16831,7 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -16695,7 +16842,7 @@ pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
@@ -16706,7 +16853,7 @@ pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -16717,7 +16864,7 @@ pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
@@ -16728,7 +16875,7 @@ pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
vqaddq_s32(a, vqdmull_high_n_s16(b, c))
@@ -16737,7 +16884,7 @@ pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
vqaddq_s32(a, vqdmull_high_s16(b, c))
@@ -16746,7 +16893,7 @@ pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
vqaddq_s64(a, vqdmull_high_n_s32(b, c))
@@ -16755,7 +16902,7 @@ pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
vqaddq_s64(a, vqdmull_high_s32(b, c))
@@ -16764,7 +16911,7 @@ pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 2))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
@@ -16775,7 +16922,7 @@ pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlal, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlal, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
@@ -16850,7 +16997,7 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t {
@@ -16861,7 +17008,7 @@ pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
@@ -16872,7 +17019,7 @@ pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t {
@@ -16883,7 +17030,7 @@ pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
@@ -16894,7 +17041,7 @@ pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
vqsubq_s32(a, vqdmull_high_n_s16(b, c))
@@ -16903,7 +17050,7 @@ pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
vqsubq_s32(a, vqdmull_high_s16(b, c))
@@ -16912,7 +17059,7 @@ pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
vqsubq_s64(a, vqdmull_high_n_s32(b, c))
@@ -16921,7 +17068,7 @@ pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
vqsubq_s64(a, vqdmull_high_s32(b, c))
@@ -16930,7 +17077,7 @@ pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 2))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
@@ -16941,7 +17088,7 @@ pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmlsl, N = 1))]
#[rustc_legacy_const_generics(3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
@@ -17138,7 +17285,7 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x4_t {
@@ -17153,7 +17300,7 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64x2_t {
@@ -17168,7 +17315,7 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2, N = 1))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 1))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x2_t {
@@ -17183,7 +17330,7 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2, N = 4))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2, N = 4))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32x4_t {
@@ -17198,7 +17345,7 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
unsafe {
@@ -17211,7 +17358,7 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
unsafe {
@@ -17224,7 +17371,7 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
@@ -17237,7 +17384,7 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqdmull2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqdmull2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
@@ -17361,7 +17508,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
unsafe {
@@ -17376,7 +17523,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
unsafe { simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17385,7 +17532,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
unsafe { simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) }
@@ -17394,7 +17541,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
unsafe {
@@ -17409,7 +17556,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17418,7 +17565,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqxtn2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqxtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) }
@@ -17495,7 +17642,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtun2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
unsafe {
@@ -17510,7 +17657,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtun2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) }
@@ -17519,7 +17666,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqxtun2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqxtun2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) }
@@ -18281,7 +18428,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -18298,7 +18445,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -18309,7 +18456,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -18320,7 +18467,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -18337,7 +18484,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -18348,7 +18495,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqrshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -18431,7 +18578,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
@@ -18448,7 +18595,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
@@ -18459,7 +18606,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqrshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
@@ -18730,7 +18877,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -18747,7 +18894,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -18758,7 +18905,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -18769,7 +18916,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -18786,7 +18933,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -18797,7 +18944,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(uqshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -18888,7 +19035,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
@@ -18905,7 +19052,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
@@ -18916,7 +19063,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sqshrun2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
@@ -22507,7 +22654,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -22524,7 +22671,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -22535,7 +22682,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -22546,7 +22693,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -22563,7 +22710,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -22574,7 +22721,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(rshrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(rshrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -23087,7 +23234,7 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
@@ -23101,7 +23248,7 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
@@ -23115,7 +23262,7 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(sshll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(sshll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
@@ -23129,7 +23276,7 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
@@ -23143,7 +23290,7 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
@@ -23157,7 +23304,7 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ushll2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ushll2, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
@@ -23171,7 +23318,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
@@ -23188,7 +23335,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
@@ -23199,7 +23346,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
@@ -23210,7 +23357,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
@@ -23227,7 +23374,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
@@ -23238,7 +23385,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(shrn2, N = 2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(shrn2, N = 2))]
#[rustc_legacy_const_generics(2)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
@@ -25610,7 +25757,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25625,7 +25772,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -25640,7 +25787,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubl2))]
pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -25655,7 +25802,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25670,7 +25817,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
@@ -25685,7 +25832,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubl2))]
pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
@@ -25700,7 +25847,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25712,7 +25859,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -25724,7 +25871,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(ssubw2))]
pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -25736,7 +25883,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
@@ -25748,7 +25895,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
@@ -25760,7 +25907,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw2))]
#[cfg_attr(all(test, target_endian = "little"), assert_instr(usubw2))]
pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
@@ -26094,7 +26241,10 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26104,7 +26254,10 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26113,7 +26266,10 @@ pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26122,7 +26278,10 @@ pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26131,7 +26290,10 @@ pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26140,7 +26302,10 @@ pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26149,7 +26314,10 @@ pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26158,7 +26326,10 @@ pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26167,7 +26338,10 @@ pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26176,7 +26350,10 @@ pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26185,7 +26362,10 @@ pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26194,7 +26374,10 @@ pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -26209,7 +26392,10 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26218,7 +26404,10 @@ pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26227,7 +26416,10 @@ pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26236,7 +26428,10 @@ pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26245,7 +26440,10 @@ pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -26260,7 +26458,10 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26269,7 +26470,10 @@ pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26278,7 +26482,10 @@ pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26287,7 +26494,10 @@ pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26296,7 +26506,10 @@ pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -26311,7 +26524,10 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 2, 6]) }
}
@@ -26320,7 +26536,10 @@ pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn1)
)]
pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) }
}
@@ -26330,7 +26549,10 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26340,7 +26562,10 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26349,7 +26574,10 @@ pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26358,7 +26586,10 @@ pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26367,7 +26598,10 @@ pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26376,7 +26610,10 @@ pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26385,7 +26622,10 @@ pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26394,7 +26634,10 @@ pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26403,7 +26646,10 @@ pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -26412,7 +26658,10 @@ pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26421,7 +26670,10 @@ pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26430,7 +26682,10 @@ pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -26445,7 +26700,10 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26454,7 +26712,10 @@ pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26463,7 +26724,10 @@ pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26472,7 +26736,10 @@ pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26481,7 +26748,10 @@ pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -26496,7 +26766,10 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26505,7 +26778,10 @@ pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26514,7 +26790,10 @@ pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26523,7 +26802,10 @@ pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26532,7 +26814,10 @@ pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -26547,7 +26832,10 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [1, 5, 3, 7]) }
}
@@ -26556,7 +26844,10 @@ pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(trn2)
)]
pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) }
}
@@ -26840,7 +27131,10 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -26850,7 +27144,10 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -26859,7 +27156,10 @@ pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26868,7 +27168,10 @@ pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26877,7 +27180,10 @@ pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26886,7 +27192,10 @@ pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26895,7 +27204,10 @@ pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26904,7 +27216,10 @@ pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26913,7 +27228,10 @@ pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -26922,7 +27240,10 @@ pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -26931,7 +27252,10 @@ pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -26940,7 +27264,10 @@ pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -26955,7 +27282,10 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -26964,7 +27294,10 @@ pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -26973,7 +27306,10 @@ pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -26982,7 +27318,10 @@ pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -26991,7 +27330,10 @@ pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -27006,7 +27348,10 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -27015,7 +27360,10 @@ pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -27024,7 +27372,10 @@ pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -27033,7 +27384,10 @@ pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -27042,7 +27396,10 @@ pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -27057,7 +27414,10 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6]) }
}
@@ -27066,7 +27426,10 @@ pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp1)
)]
pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) }
}
@@ -27076,7 +27439,10 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27086,7 +27452,10 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27095,7 +27464,10 @@ pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27104,7 +27476,10 @@ pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27113,7 +27488,10 @@ pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27122,7 +27500,10 @@ pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27131,7 +27512,10 @@ pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27140,7 +27524,10 @@ pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27149,7 +27536,10 @@ pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27158,7 +27548,10 @@ pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27167,7 +27560,10 @@ pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27176,7 +27572,10 @@ pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -27191,7 +27590,10 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27200,7 +27602,10 @@ pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27209,7 +27614,10 @@ pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27218,7 +27626,10 @@ pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27227,7 +27638,10 @@ pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -27242,7 +27656,10 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27251,7 +27668,10 @@ pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27260,7 +27680,10 @@ pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27269,7 +27692,10 @@ pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27278,7 +27704,10 @@ pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -27293,7 +27722,10 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7]) }
}
@@ -27302,7 +27734,10 @@ pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(uzp2)
)]
pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) }
}
@@ -27330,7 +27765,10 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27340,7 +27778,10 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27349,7 +27790,10 @@ pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27358,7 +27802,10 @@ pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27367,7 +27814,10 @@ pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27376,7 +27826,10 @@ pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27385,7 +27838,10 @@ pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -27400,7 +27856,10 @@ pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27409,7 +27868,10 @@ pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27418,7 +27880,10 @@ pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27427,7 +27892,10 @@ pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27436,7 +27904,10 @@ pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27445,7 +27916,10 @@ pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27454,7 +27928,10 @@ pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -27469,7 +27946,10 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27478,7 +27958,10 @@ pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27487,7 +27970,10 @@ pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27496,7 +27982,10 @@ pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27505,7 +27994,10 @@ pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27514,7 +28006,10 @@ pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27523,7 +28018,10 @@ pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -27538,7 +28036,10 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [0, 4, 1, 5]) }
}
@@ -27547,7 +28048,10 @@ pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) }
}
@@ -27556,7 +28060,10 @@ pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip1)
)]
pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [0, 2]) }
}
@@ -27566,7 +28073,10 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27576,7 +28086,10 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27585,7 +28098,10 @@ pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27594,7 +28110,10 @@ pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27603,7 +28122,10 @@ pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27612,7 +28134,10 @@ pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27621,7 +28146,10 @@ pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
unsafe {
simd_shuffle!(
@@ -27636,7 +28164,10 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27645,7 +28176,10 @@ pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27654,7 +28188,10 @@ pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27663,7 +28200,10 @@ pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27672,7 +28212,10 @@ pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27681,7 +28224,10 @@ pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27690,7 +28236,10 @@ pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
unsafe {
simd_shuffle!(
@@ -27705,7 +28254,10 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27714,7 +28266,10 @@ pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27723,7 +28278,10 @@ pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27732,7 +28290,10 @@ pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27741,7 +28302,10 @@ pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
@@ -27750,7 +28314,10 @@ pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27759,7 +28326,10 @@ pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
unsafe {
simd_shuffle!(
@@ -27774,7 +28344,10 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
unsafe { simd_shuffle!(a, b, [2, 6, 3, 7]) }
}
@@ -27783,7 +28356,10 @@ pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
unsafe { simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) }
}
@@ -27792,7 +28368,10 @@ pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
#[cfg_attr(
all(test, not(target_env = "msvc"), target_endian = "little"),
assert_instr(zip2)
)]
pub fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
unsafe { simd_shuffle!(a, b, [1, 3]) }
}
library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+200 -40
View File
@@ -2189,7 +2189,11 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2213,7 +2217,11 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2237,7 +2245,11 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2261,7 +2273,11 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2285,7 +2301,11 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2309,7 +2329,11 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(addhn2)
)]
#[cfg_attr(
@@ -2459,7 +2483,11 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddl2)
)]
#[cfg_attr(
@@ -2486,7 +2514,11 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddl2)
)]
#[cfg_attr(
@@ -2513,7 +2545,11 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddl2)
)]
#[cfg_attr(
@@ -2540,7 +2576,11 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddl2)
)]
#[cfg_attr(
@@ -2567,7 +2607,11 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddl2)
)]
#[cfg_attr(
@@ -2594,7 +2638,11 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddl2)
)]
#[cfg_attr(
@@ -2792,7 +2840,11 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddw2)
)]
#[cfg_attr(
@@ -2817,7 +2869,11 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddw2)
)]
#[cfg_attr(
@@ -2842,7 +2898,11 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(saddw2)
)]
#[cfg_attr(
@@ -2867,7 +2927,11 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddw2)
)]
#[cfg_attr(
@@ -2892,7 +2956,11 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddw2)
)]
#[cfg_attr(
@@ -2917,7 +2985,11 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(uaddw2)
)]
#[cfg_attr(
@@ -34881,7 +34953,11 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sqdmlal, N = 2)
)]
#[rustc_legacy_const_generics(3)]
@@ -34904,7 +34980,11 @@ pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sqdmlal, N = 1)
)]
#[rustc_legacy_const_generics(3)]
@@ -35011,7 +35091,11 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sqdmlsl, N = 2)
)]
#[rustc_legacy_const_generics(3)]
@@ -35034,7 +35118,11 @@ pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sqdmlsl, N = 1)
)]
#[rustc_legacy_const_generics(3)]
@@ -39004,7 +39092,11 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -39026,7 +39118,11 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -39048,7 +39144,11 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -39070,7 +39170,11 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -39094,7 +39198,11 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -39118,7 +39226,11 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(raddhn2)
)]
#[cfg_attr(
@@ -69685,7 +69797,11 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -69707,7 +69823,11 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -69729,7 +69849,11 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -69751,7 +69875,11 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -69773,7 +69901,11 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -69795,7 +69927,11 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(subhn2)
)]
#[cfg_attr(
@@ -70225,7 +70361,11 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sudot, LANE = 0)
)]
#[rustc_legacy_const_generics(3)]
@@ -70252,7 +70392,11 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sudot, LANE = 0)
)]
#[rustc_legacy_const_generics(3)]
@@ -70280,7 +70424,11 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
#[target_feature(enable = "neon,i8mm")]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sudot, LANE = 3)
)]
#[rustc_legacy_const_generics(3)]
@@ -70300,7 +70448,11 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
#[target_feature(enable = "neon,i8mm")]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(sudot, LANE = 3)
)]
#[rustc_legacy_const_generics(3)]
@@ -72296,7 +72448,11 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(usdot)
)]
#[cfg_attr(
@@ -72325,7 +72481,11 @@ pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
#[cfg_attr(
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
all(
test,
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
),
assert_instr(usdot)
)]
#[cfg_attr(
library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+129 -109
View File
@@ -78,14 +78,22 @@ cfg-target-has-atomic-64: &cfg-target-has-atomic-64
neon-unstable-fp8: &neon-unstable-fp8
FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']]
# all(test, target_endian = "little")
all-test-little-endian: &all-test-little-endian
FnCall: [all, [test, 'target_endian = "little"']]
# #[cfg(target_endian = "little")]
little-endian: &little-endian
cfg-little-endian: &cfg-little-endian
FnCall: [cfg, ['target_endian = "little"']]
# #[cfg(target_endian = "big")]
big-endian: &big-endian
cfg-big-endian: &cfg-big-endian
FnCall: [cfg, ['target_endian = "big"']]
# all(test, not(target_env = "msvc"), target_endian = "big")
cfg-test-not-msvc-little-endian: &cfg-test-not-msvc-little-endian
FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}, 'target_endian = "little"']]
intrinsics:
- name: "vaddd_{type}"
doc: Add
@@ -206,8 +214,9 @@ intrinsics:
doc: Signed Absolute difference Long
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [sabdl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
safety: safe
types:
- [int8x16_t, int16x8_t, int8x8_t, uint8x8_t]
@@ -245,8 +254,9 @@ intrinsics:
doc: Signed Absolute difference Long
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [sabdl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
safety: safe
types:
- [int16x8_t, int32x4_t, int16x4_t, uint16x4_t]
@@ -284,8 +294,9 @@ intrinsics:
doc: Signed Absolute difference Long
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [sabdl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sabdl2]]}]]
safety: safe
types:
- [int32x4_t, int64x2_t, int32x2_t, uint32x2_t]
@@ -1492,7 +1503,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]]
- *neon-stable
safety: safe
types:
@@ -1513,7 +1524,7 @@ intrinsics:
arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]]
- *neon-stable-fp16
- *target-not-arm64ec
safety: safe
@@ -1530,7 +1541,7 @@ intrinsics:
arguments: ["a: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtl2]]}]]
- *neon-stable-fp16
- *target-not-arm64ec
safety: safe
@@ -1547,7 +1558,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn]]}]]
- *neon-stable
safety: safe
types:
@@ -1560,7 +1571,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtn2]]}]]
- *neon-stable
safety: safe
types:
@@ -1577,7 +1588,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn]]}]]
- *neon-stable
safety: safe
types:
@@ -1612,7 +1623,7 @@ intrinsics:
arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
return_type: "{type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fcvtxn2]]}]]
- *neon-stable
safety: safe
types:
@@ -2687,7 +2698,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]]
- *neon-stable
safety: safe
types:
@@ -2704,7 +2715,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]]
- *neon-stable
safety: safe
types:
@@ -2727,7 +2738,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]]
- *neon-stable
safety: safe
types:
@@ -2750,7 +2761,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]]
- *neon-stable
safety: safe
types:
@@ -2766,8 +2777,9 @@ intrinsics:
doc: Extract narrow
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr: [*neon-stable]
assert_instr: [xtn2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [xtn2]]}]]
safety: safe
types:
- [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5145,8 +5157,9 @@ intrinsics:
doc: Signed multiply long
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[3]}"
attr: [*neon-stable]
assert_instr: [smull2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]]
safety: safe
types:
- [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t]
@@ -5167,8 +5180,9 @@ intrinsics:
doc: "Unsigned multiply long"
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[3]}"
attr: [*neon-stable]
assert_instr: [umull2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]]
safety: safe
types:
- [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t]
@@ -5211,8 +5225,8 @@ intrinsics:
return_type: "{neon_type[3]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]]
safety: safe
assert_instr: [pmull2]
types:
- [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t]
compose:
@@ -5233,8 +5247,8 @@ intrinsics:
attr:
- *neon-aes
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]]
safety: safe
assert_instr: [pmull2]
types:
- [poly64x2_t, "p128"]
compose:
@@ -5814,8 +5828,9 @@ intrinsics:
doc: Signed Subtract Wide
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr: [*neon-stable]
assert_instr: [ssubw2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubw2]]}]]
safety: safe
types:
- [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5835,8 +5850,9 @@ intrinsics:
doc: Unsigned Subtract Wide
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr: [*neon-stable]
assert_instr: [usubw2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubw2]]}]]
safety: safe
types:
- [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -5856,8 +5872,9 @@ intrinsics:
doc: "Signed Subtract Long"
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [ssubl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ssubl2]]}]]
safety: safe
types:
- [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t]
@@ -5886,8 +5903,9 @@ intrinsics:
doc: "Unsigned Subtract Long"
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [usubl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [usubl2]]}]]
safety: safe
types:
- [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t]
@@ -6894,8 +6912,9 @@ intrinsics:
doc: Vector move
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [sxtl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sxtl2]]}]]
safety: safe
types:
- [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -6912,8 +6931,9 @@ intrinsics:
doc: Vector move
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr: [*neon-stable]
assert_instr: [uxtl2]
attr:
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uxtl2]]}]]
safety: safe
types:
- [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -7125,7 +7145,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]]
- *neon-stable
safety: safe
types:
@@ -7141,7 +7161,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2]]}]]
- *neon-stable
safety: safe
types:
@@ -7209,7 +7229,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7228,7 +7248,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7246,7 +7266,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7298,7 +7318,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2]]}]]
- *neon-stable
safety: safe
types:
@@ -7314,7 +7334,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7380,7 +7400,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7396,7 +7416,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7412,7 +7432,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2]]}]]
- *neon-stable
safety: safe
types:
@@ -7428,7 +7448,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7494,7 +7514,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7510,7 +7530,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const N: i32']
@@ -7578,7 +7598,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtn2]]}]]
- *neon-stable
safety: safe
types:
@@ -7593,7 +7613,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqxtn2]]}]]
- *neon-stable
safety: safe
types:
@@ -7685,7 +7705,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqxtun2]]}]]
- *neon-stable
safety: safe
types:
@@ -7988,7 +8008,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8025,7 +8045,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8076,7 +8096,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8270,7 +8290,7 @@ intrinsics:
arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
return_type: "{neon_type[3]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8338,7 +8358,7 @@ intrinsics:
arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"]
return_type: "{neon_type[3]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8383,7 +8403,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8859,7 +8879,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -8884,7 +8904,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[3]}"
attr:
- *little-endian
- *cfg-little-endian
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]]
- *neon-stable
safety: safe
@@ -8907,7 +8927,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]
return_type: "{neon_type[3]}"
attr:
- *big-endian
- *cfg-big-endian
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn]]}]]
- *neon-stable
safety: safe
@@ -8930,7 +8950,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- *neon-stable
static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -8955,7 +8975,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- *neon-stable
static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -8980,7 +9000,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- *neon-stable
static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9009,7 +9029,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- *neon-stable
static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9035,7 +9055,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- *neon-stable
static_defs: ['const LANE1: i32, const LANE2: i32']
@@ -9155,7 +9175,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['1']]
- *neon-stable
static_defs: ['const N: i32']
@@ -9174,7 +9194,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['1']]
- *neon-stable
static_defs: ['const N: i32']
@@ -9193,7 +9213,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const N: i32']
@@ -9646,7 +9666,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]]
safety: safe
types:
- [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]']
@@ -9676,7 +9696,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn1]]}]]
safety: safe
types:
- [float16x4_t, '[0, 4, 2, 6]']
@@ -9690,7 +9710,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
safety: safe
types:
- [int32x2_t, '[0, 2]']
@@ -9709,7 +9729,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]]
safety: safe
types:
- [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]']
@@ -9738,7 +9758,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [trn2]]}]]
safety: safe
types:
- [float16x4_t, '[1, 5, 3, 7]']
@@ -9752,7 +9772,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
safety: safe
types:
- [int32x2_t, '[1, 3]']
@@ -9771,7 +9791,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
safety: safe
types:
- [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]']
@@ -9807,7 +9827,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
safety: safe
types:
- [float16x4_t, '[2, 6, 3, 7]']
@@ -9821,7 +9841,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
safety: safe
types:
- [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]']
@@ -9858,7 +9878,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
safety: safe
types:
- [float16x4_t, '[0, 4, 1, 5]']
@@ -9872,7 +9892,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip1]]}]]
safety: safe
types:
- [int32x2_t, '[0, 2]']
@@ -9891,7 +9911,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]]
safety: safe
types:
- [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]']
@@ -9920,7 +9940,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp1]]}]]
safety: safe
types:
- [float16x4_t, '[0, 2, 4, 6]']
@@ -9934,7 +9954,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [zip2]]}]]
safety: safe
types:
- [int32x2_t, '[1, 3]']
@@ -9953,7 +9973,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]]
safety: safe
types:
- [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]']
@@ -9986,7 +10006,7 @@ intrinsics:
- *neon-fp16
- *neon-stable-fp16
- *target-not-arm64ec
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uzp2]]}]]
safety: safe
types:
- [float16x4_t, '[1, 3, 5, 7]']
@@ -10004,7 +10024,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [uabal2]]}]]
safety: safe
types:
- [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -10031,7 +10051,7 @@ intrinsics:
return_type: "{neon_type[0]}"
attr:
- *neon-stable
- FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal2]]}]]
- FnCall: [cfg_attr, [*cfg-test-not-msvc-little-endian, {FnCall: [assert_instr, [sabal2]]}]]
safety: safe
types:
- [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t]
@@ -10360,7 +10380,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -10400,7 +10420,7 @@ intrinsics:
arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"]
return_type: "{type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -10453,7 +10473,7 @@ intrinsics:
arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"]
return_type: "{type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-fp16
- *neon-unstable-f16
@@ -10473,7 +10493,7 @@ intrinsics:
arguments: ["a: {type[0]}", "b: {type[0]}", "v: {neon_type[1]}"]
return_type: "{type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-fp16
- *neon-unstable-f16
@@ -10571,7 +10591,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -10603,7 +10623,7 @@ intrinsics:
arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"]
return_type: "{type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -11325,7 +11345,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2]]}]]
- *neon-stable
safety: safe
types:
@@ -11339,7 +11359,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2]]}]]
- *neon-stable
safety: safe
types:
@@ -11353,7 +11373,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -11376,7 +11396,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -11455,8 +11475,8 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
return_type: "{neon_type[1]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]]
- *neon-stable
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [uabdl2]]}]]
safety: safe
types:
- [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
@@ -11644,7 +11664,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2]]}]]
- *neon-stable
safety: safe
types:
@@ -11661,7 +11681,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2]]}]]
- *neon-stable
safety: safe
types:
@@ -11678,7 +11698,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -11700,7 +11720,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['2']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -11955,7 +11975,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2]]}]]
- *neon-stable
safety: safe
types:
@@ -11973,7 +11993,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2]]}]]
- *neon-stable
safety: safe
types:
@@ -11991,7 +12011,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
@@ -12010,7 +12030,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
return_type: "{neon_type[0]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-stable
static_defs: ['const LANE: i32']
library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+17 -13
View File
@@ -104,6 +104,10 @@ aarch64-crc-stable: &aarch64-crc-stable
neon-unstable-f16: &neon-unstable-f16
FnCall: [unstable, ['feature = "stdarch_neon_f16"', 'issue = "136306"']]
# all(target_endian = "little")
all-neon-target-aarch64-arm64ec-little-endian: &all-neon-target-aarch64-arm64ec-little-endian
FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}, 'target_endian = "little"']]
intrinsics:
- name: "vand{neon_type.no}"
doc: Vector bitwise and
@@ -6139,7 +6143,7 @@ intrinsics:
- *neon-i8mm
- *neon-v8
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [usdot]]}]]
- *neon-unstable-i8mm
- *neon-cfg-arm-unstable
safety: safe
@@ -6192,7 +6196,7 @@ intrinsics:
- *neon-i8mm
- *neon-v8
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-unstable-i8mm
- *neon-cfg-arm-unstable
@@ -6796,7 +6800,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [subhn2]]}]]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe
@@ -6992,7 +6996,7 @@ intrinsics:
- *neon-v8
- *neon-i8mm
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
static_defs: ["const LANE: i32"]
@@ -7650,7 +7654,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 2]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
@@ -7669,7 +7673,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlal, N = 1]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
@@ -7722,7 +7726,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 2]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
@@ -7741,7 +7745,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vqdmlsl, N = 1]]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]]
- FnCall: [rustc_legacy_const_generics, ['3']]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
@@ -13216,7 +13220,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe
@@ -13243,7 +13247,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"{type[3]}"']]}]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [raddhn2]]}]]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, {FnCall: [assert_instr, [raddhn2]]}]]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe
@@ -14469,7 +14473,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe
@@ -14525,7 +14529,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['{type[3]}']] } ]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['{type[4]}']]}] ]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe
@@ -14583,7 +14587,7 @@ intrinsics:
attr:
- *neon-v7
- FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['vaddhn']] } ]]
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['addhn2']]}] ]
- FnCall: [cfg_attr, [*all-neon-target-aarch64-arm64ec-little-endian, { FnCall: [assert_instr, ['addhn2']]}] ]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
safety: safe