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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
92 lines
3.6 KiB
C
Vendored
92 lines
3.6 KiB
C
Vendored
/* $OpenBSD: pte.h,v 1.23 2019/01/18 01:34:50 pd Exp $ */
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/* $NetBSD: pte.h,v 1.11 1998/02/06 21:58:05 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Charles D. Cranor and Washington University.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* pte.h rewritten by chuck based on the jolitz version, plus random
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* info on the pentium and other processors found on the net. the
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* goal of this rewrite is to provide enough documentation on the MMU
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* hardware that the reader will be able to understand it without having
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* to refer to a hardware manual.
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* now we define various for playing with virtual addresses
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*/
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#define PDSHIFT 22 /* offset of PD index in VA */
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#define NBPD (1 << PDSHIFT) /* # bytes mapped by PD (4MB) */
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/*
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* here we define the bits of the PDE/PTE, as described above:
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*
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* XXXCDC: need to rename these (PG_u == ugly).
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*/
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#define PG_V 0x00000001 /* valid entry */
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#define PG_RO 0x00000000 /* read-only page */
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#define PG_RW 0x00000002 /* read-write page */
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#define PG_u 0x00000004 /* user accessible page */
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#define PG_PROT 0x00000806 /* all protection bits */
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#define PG_WT 0x00000008 /* write through */
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#define PG_N 0x00000010 /* non-cacheable */
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#define PG_U 0x00000020 /* has been used */
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#define PG_M 0x00000040 /* has been modified */
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#define PG_PAT 0x00000080 /* PAT bit. (on pte) */
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#define PG_PS 0x00000080 /* 4MB page size (on pde) */
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#define PG_G 0x00000100 /* global, don't TLB flush */
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#define PG_AVAIL1 0x00000200 /* ignored by hardware */
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#define PG_AVAIL2 0x00000400 /* ignored by hardware */
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#define PG_AVAIL3 0x00000800 /* ignored by hardware */
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#define PG_PATLG 0x00001000 /* PAT on large pages */
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/* Cacheability bits when we are using PAT */
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#define PG_WB (0) /* The default */
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#define PG_WC (PG_WT) /* WT and CD is WC */
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#define PG_UCMINUS (PG_N) /* UC but mtrr can override */
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#define PG_UC (PG_WT | PG_N) /* hard UC */
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/*
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* various shorthand protection codes
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*/
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#define PG_KR 0x00000000 /* kernel read-only */
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#define PG_KW 0x00000002 /* kernel read-write */
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/*
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* page protection exception bits
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*/
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#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
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#define PGEX_W 0x02 /* exception during a write cycle */
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#define PGEX_U 0x04 /* exception while in user mode (upl) */
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#define PGEX_I 0x10 /* instruction fetch blocked by NX */
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#endif /* _MACHINE_PTE_H_ */ |