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https://codeberg.org/ziglang/zig.git
synced 2026-04-28 19:47:08 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
93 lines
2.8 KiB
C
Vendored
93 lines
2.8 KiB
C
Vendored
/* $OpenBSD: pctr.h,v 1.17 2014/03/29 18:09:29 guenther Exp $ */
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/*
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* Pentium performance counter driver for OpenBSD.
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* Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
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*
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* Modification and redistribution in source and binary forms is
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* permitted provided that due credit is given to the author and the
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* OpenBSD project by leaving this copyright notice intact.
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*/
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#ifndef _MACHINE_PCTR_H_
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#define _MACHINE_PCTR_H_
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#include <sys/ioccom.h>
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typedef u_int64_t pctrval;
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#define PCTR_NUM 4
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struct pctrst {
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u_int pctr_fn[PCTR_NUM]; /* Current settings of counters */
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pctrval pctr_tsc; /* Free-running 64-bit cycle counter */
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pctrval pctr_hwc[PCTR_NUM]; /* Values of the hardware counters */
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};
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/* Bit values in fn fields and PIOCS ioctl's */
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#define P5CTR_K 0x40 /* Monitor kernel-level events */
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#define P5CTR_U 0x80 /* Monitor user-level events */
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#define P5CTR_C 0x100 /* count cycles rather than events */
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#define PCTR_U 0x010000 /* Monitor user-level events */
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#define PCTR_K 0x020000 /* Monitor kernel-level events */
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#define PCTR_E 0x040000 /* Edge detect */
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#define PCTR_EN 0x400000 /* Enable counters (counter 0 only) */
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#define PCTR_I 0x800000 /* Invert counter mask */
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/* Unit Mask bits */
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#define PCTR_UM_M 0x0800 /* Modified cache lines */
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#define PCTR_UM_E 0x0400 /* Exclusive cache lines */
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#define PCTR_UM_S 0x0200 /* Shared cache lines */
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#define PCTR_UM_I 0x0100 /* Invalid cache lines */
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#define PCTR_UM_MESI (PCTR_UM_M|PCTR_UM_E|PCTR_UM_S|PCTR_UM_I)
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#define PCTR_UM_A 0x2000 /* Any initiator */
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#define PCTR_UM_SHIFT 8 /* Left shift for unit mask */
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#define PCTR_CM_SHIFT 24 /* Left shift for counter mask */
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/* ioctl to set which counter a device tracks */
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#define PCIOCRD _IOR('c', 1, struct pctrst) /* Read counter value */
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#define PCIOCS0 _IOW('c', 8, unsigned int) /* Set counter 0 function */
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#define PCIOCS1 _IOW('c', 9, unsigned int) /* Set counter 1 function */
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#define PCIOCS2 _IOW('c', 10, unsigned int) /* Set counter 0 function */
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#define PCIOCS3 _IOW('c', 11, unsigned int) /* Set counter 1 function */
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#define _PATH_PCTR "/dev/pctr"
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#define rdtsc() \
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({ \
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pctrval v; \
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__asm volatile ("rdtsc" : "=A" (v)); \
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v; \
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})
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/* Read the performance counters (Pentium Pro only) */
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#define rdpmc(ctr) \
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({ \
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pctrval v; \
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__asm volatile ("rdpmc\n" \
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"\tandl $0xff, %%edx" \
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: "=A" (v) : "c" (ctr)); \
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v; \
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})
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#ifdef _KERNEL
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#define rdmsr(msr) \
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({ \
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pctrval v; \
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__asm volatile ("rdmsr" : "=A" (v) : "c" (msr)); \
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v; \
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})
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#define wrmsr(msr, v) \
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__asm volatile ("wrmsr" :: "A" ((u_int64_t) (v)), "c" (msr));
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void pctrattach(int);
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int pctropen(dev_t, int, int, struct proc *);
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int pctrclose(dev_t, int, int, struct proc *);
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int pctrioctl(dev_t, u_long, caddr_t, int, struct proc *);
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#endif /* _KERNEL */
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#endif /* ! _MACHINE_PCTR_H_ */ |