mirror of
https://codeberg.org/ziglang/zig.git
synced 2026-04-28 19:47:08 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
316 lines
8.7 KiB
C
Vendored
316 lines
8.7 KiB
C
Vendored
/* $OpenBSD: atomic.h,v 1.20 2022/08/29 02:01:18 jsg Exp $ */
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/* $NetBSD: atomic.h,v 1.1.2.2 2000/02/21 18:54:07 sommerfeld Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by RedBack Networks Inc.
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*
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* Author: Bill Sommerfeld
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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/*
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* Perform atomic operations on memory. Should be atomic with respect
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* to interrupts and multiple processors.
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*
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* void atomic_setbits_int(volatile u_int *a, u_int mask) { *a |= mask; }
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* void atomic_clearbits_int(volatile u_int *a, u_int mas) { *a &= ~mask; }
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*/
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#if !defined(_LOCORE)
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#if defined(MULTIPROCESSOR) || !defined(_KERNEL)
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#define _LOCK "lock"
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#else
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#define _LOCK
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#endif
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static inline unsigned int
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_atomic_cas_uint(volatile unsigned int *p, unsigned int e, unsigned int n)
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{
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__asm volatile(_LOCK " cmpxchgl %2, %1"
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: "=a" (n), "=m" (*p)
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: "r" (n), "a" (e), "m" (*p));
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return (n);
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}
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#define atomic_cas_uint(_p, _e, _n) _atomic_cas_uint((_p), (_e), (_n))
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static inline unsigned long
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_atomic_cas_ulong(volatile unsigned long *p, unsigned long e, unsigned long n)
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{
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__asm volatile(_LOCK " cmpxchgl %2, %1"
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: "=a" (n), "=m" (*p)
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: "r" (n), "a" (e), "m" (*p));
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return (n);
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}
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#define atomic_cas_ulong(_p, _e, _n) _atomic_cas_ulong((_p), (_e), (_n))
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static inline void *
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_atomic_cas_ptr(volatile void *p, void *e, void *n)
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{
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__asm volatile(_LOCK " cmpxchgl %2, %1"
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: "=a" (n), "=m" (*(unsigned long *)p)
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: "r" (n), "a" (e), "m" (*(unsigned long *)p));
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return (n);
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}
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#define atomic_cas_ptr(_p, _e, _n) _atomic_cas_ptr((_p), (_e), (_n))
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static inline unsigned int
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_atomic_swap_uint(volatile unsigned int *p, unsigned int n)
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{
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__asm volatile("xchgl %0, %1"
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: "=a" (n), "=m" (*p)
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: "0" (n), "m" (*p));
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return (n);
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}
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#define atomic_swap_uint(_p, _n) _atomic_swap_uint((_p), (_n))
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#define atomic_swap_32(_p, _n) _atomic_swap_uint((_p), (_n))
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static inline unsigned long
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_atomic_swap_ulong(volatile unsigned long *p, unsigned long n)
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{
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__asm volatile("xchgl %0, %1"
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: "=a" (n), "=m" (*p)
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: "0" (n), "m" (*p));
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return (n);
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}
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#define atomic_swap_ulong(_p, _n) _atomic_swap_ulong((_p), (_n))
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static inline void *
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_atomic_swap_ptr(volatile void *p, void *n)
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{
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__asm volatile("xchgl %0, %1"
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: "=a" (n), "=m" (*(unsigned long *)p)
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: "0" (n), "m" (*(unsigned long *)p));
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return (n);
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}
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#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n))
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static inline void
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_atomic_inc_int(volatile unsigned int *p)
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{
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__asm volatile(_LOCK " incl %0"
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: "+m" (*p));
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}
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#define atomic_inc_int(_p) _atomic_inc_int(_p)
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static inline void
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_atomic_inc_long(volatile unsigned long *p)
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{
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__asm volatile(_LOCK " incl %0"
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: "+m" (*p));
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}
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#define atomic_inc_long(_p) _atomic_inc_long(_p)
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static inline void
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_atomic_dec_int(volatile unsigned int *p)
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{
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__asm volatile(_LOCK " decl %0"
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: "+m" (*p));
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}
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#define atomic_dec_int(_p) _atomic_dec_int(_p)
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static inline void
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_atomic_dec_long(volatile unsigned long *p)
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{
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__asm volatile(_LOCK " decl %0"
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: "+m" (*p));
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}
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#define atomic_dec_long(_p) _atomic_dec_long(_p)
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static inline void
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_atomic_add_int(volatile unsigned int *p, unsigned int v)
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{
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__asm volatile(_LOCK " addl %1,%0"
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: "+m" (*p)
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: "a" (v));
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}
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#define atomic_add_int(_p, _v) _atomic_add_int(_p, _v)
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static inline void
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_atomic_add_long(volatile unsigned long *p, unsigned long v)
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{
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__asm volatile(_LOCK " addl %1,%0"
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: "+m" (*p)
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: "a" (v));
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}
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#define atomic_add_long(_p, _v) _atomic_add_long(_p, _v)
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static inline void
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_atomic_sub_int(volatile unsigned int *p, unsigned int v)
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{
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__asm volatile(_LOCK " subl %1,%0"
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: "+m" (*p)
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: "a" (v));
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}
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#define atomic_sub_int(_p, _v) _atomic_sub_int(_p, _v)
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static inline void
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_atomic_sub_long(volatile unsigned long *p, unsigned long v)
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{
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__asm volatile(_LOCK " subl %1,%0"
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: "+m" (*p)
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: "a" (v));
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}
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#define atomic_sub_long(_p, _v) _atomic_sub_long(_p, _v)
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static inline unsigned long
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_atomic_add_int_nv(volatile unsigned int *p, unsigned int v)
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{
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unsigned int rv = v;
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__asm volatile(_LOCK " xaddl %0,%1"
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: "+a" (rv), "+m" (*p));
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return (rv + v);
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}
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#define atomic_add_int_nv(_p, _v) _atomic_add_int_nv(_p, _v)
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static inline unsigned long
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_atomic_add_long_nv(volatile unsigned long *p, unsigned long v)
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{
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unsigned long rv = v;
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__asm volatile(_LOCK " xaddl %0,%1"
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: "+a" (rv), "+m" (*p));
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return (rv + v);
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}
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#define atomic_add_long_nv(_p, _v) _atomic_add_long_nv(_p, _v)
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static inline unsigned long
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_atomic_sub_int_nv(volatile unsigned int *p, unsigned int v)
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{
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unsigned int rv = 0 - v;
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__asm volatile(_LOCK " xaddl %0,%1"
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: "+a" (rv), "+m" (*p));
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return (rv - v);
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}
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#define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv(_p, _v)
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static inline unsigned long
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_atomic_sub_long_nv(volatile unsigned long *p, unsigned long v)
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{
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unsigned long rv = 0 - v;
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__asm volatile(_LOCK " xaddl %0,%1"
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: "+a" (rv), "+m" (*p));
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return (rv - v);
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}
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#define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv(_p, _v)
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/*
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* The IA-32 architecture is rather strongly ordered. When accessing
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* normal write-back cacheable memory, only reads may be reordered with
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* older writes to different locations. There are a few instructions
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* (clfush, non-temporal move instructions) that obey weaker ordering
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* rules, but those instructions will only be used in (inline)
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* assembly code where we can add the necessary fence instructions
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* ourselves.
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*/
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#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
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#if defined(MULTIPROCESSOR) || !defined(_KERNEL)
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#define membar_enter() __membar("lock; addl $0,0(%%esp)")
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#define membar_exit() __membar("")
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#define membar_producer() __membar("")
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#define membar_consumer() __membar("")
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#define membar_sync() __membar("lock; addl $0,0(%%esp)")
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#else
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#define membar_enter() __membar("")
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#define membar_exit() __membar("")
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#define membar_producer() __membar("")
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#define membar_consumer() __membar("")
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#define membar_sync() __membar("")
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#endif
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#define membar_enter_after_atomic() __membar("")
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#define membar_exit_before_atomic() __membar("")
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#ifdef _KERNEL
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/* virtio needs MP membars even on SP kernels */
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#define virtio_membar_producer() __membar("")
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#define virtio_membar_consumer() __membar("")
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#define virtio_membar_sync() __membar("lock; addl $0,0(%%esp)")
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static __inline u_int64_t
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i386_atomic_testset_uq(volatile u_int64_t *ptr, u_int64_t val)
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{
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__asm__ volatile ("\n1:\t" _LOCK " cmpxchg8b (%1); jnz 1b" : "+A" (val) :
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"r" (ptr), "b" ((u_int32_t)val), "c" ((u_int32_t)(val >> 32)));
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return val;
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}
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static __inline u_int32_t
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i386_atomic_testset_ul(volatile u_int32_t *ptr, unsigned long val)
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{
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__asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
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return val;
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}
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static __inline int
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i386_atomic_testset_i(volatile int *ptr, unsigned long val)
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{
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__asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
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return val;
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}
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static __inline void
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i386_atomic_setbits_l(volatile u_int32_t *ptr, unsigned long bits)
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{
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__asm volatile(_LOCK " orl %1,%0" : "=m" (*ptr) : "ir" (bits));
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}
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static __inline void
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i386_atomic_clearbits_l(volatile u_int32_t *ptr, unsigned long bits)
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{
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bits = ~bits;
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__asm volatile(_LOCK " andl %1,%0" : "=m" (*ptr) : "ir" (bits));
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}
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#define atomic_setbits_int i386_atomic_setbits_l
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#define atomic_clearbits_int i386_atomic_clearbits_l
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#endif /* _KERNEL */
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#undef _LOCK
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#endif /* !defined(_LOCORE) */
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#endif /* _MACHINE_ATOMIC_H_ */ |