mirror of
https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
204 lines
7.3 KiB
C
Vendored
204 lines
7.3 KiB
C
Vendored
/* $OpenBSD: pte.h,v 1.17 2024/04/14 19:08:09 miod Exp $ */
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/* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */
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/*
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* Copyright (c) 1996-1999 Eduardo Horvath
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/* virtual address to virtual page number */
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#define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31)
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/* virtual address to offset within page */
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#define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF)
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/* When we go to 64-bit VAs we need to handle the hole */
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#define VA_VPG(va) VA_SUN4U_VPG(va)
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#define VA_OFF(va) VA_SUN4U_OFF(va)
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#define PG_SHIFT4U 13
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#define MMU_PAGE_ALIGN 8192
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/* If you know where a tte is in the tsb, how do you find its va? */
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#define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000))
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#ifndef _LOCORE
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/*
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* This is the spitfire TTE.
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*/
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#if 0 /* We don't use bitfields anyway. */
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struct sun4u_tag_fields {
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u_int64_t tag_g:1, /* global flag */
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tag_ctxt:15, /* context for mapping */
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tag_unassigned:6,
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tag_va:42; /* virtual address bits<64:22> */
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};
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union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; };
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struct sun4u_data_fields {
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u_int64_t data_v:1, /* valid bit */
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data_size:2, /* page size [8K*8**<SIZE>] */
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data_nfo:1, /* no-fault only */
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data_ie:1, /* invert endianness [inefficient] */
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data_soft2:2, /* reserved for S/W */
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data_pa:36, /* physical address */
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data_accessed:1,/* S/W accessed bit */
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data_modified:1,/* S/W modified bit */
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data_realw:1, /* S/W real writable bit (to manage modified) */
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data_tsblock:1, /* S/W TSB locked entry */
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data_exec:1, /* S/W Executable */
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data_onlyexec:1,/* S/W Executable only */
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data_lock:1, /* lock into TLB */
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data_cacheable:2, /* cacheability control */
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data_e:1, /* explicit accesses only */
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data_priv:1, /* privileged page */
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data_w:1, /* writeable */
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data_g:1; /* same as tag_g */
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};
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union sun4u_data { struct sun4u_data_fields f; int64_t data; };
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struct sun4u_tte {
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union sun4u_tag tag;
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union sun4u_data data;
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};
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#else
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struct sun4u_tte {
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int64_t tag;
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int64_t data;
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};
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#endif
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typedef struct sun4u_tte pte_t;
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/* Assembly routine to flush a mapping */
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extern void (*sp_tlb_flush_pte)(vaddr_t, uint64_t);
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extern void (*sp_tlb_flush_ctx)(uint64_t);
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#if defined(MULTIPROCESSOR)
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void smp_tlb_flush_pte(vaddr_t, uint64_t);
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void smp_tlb_flush_ctx(uint64_t);
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#define tlb_flush_pte(va,ctx) smp_tlb_flush_pte(va, ctx)
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#define tlb_flush_ctx(ctx) smp_tlb_flush_ctx(ctx)
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#else
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#define tlb_flush_pte(va,ctx) (*sp_tlb_flush_pte)(va, ctx)
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#define tlb_flush_ctx(ctx) (*sp_tlb_flush_ctx)(ctx)
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#endif
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#endif /* _LOCORE */
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/* TSB tag masks */
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#define CTX_MASK ((1<<13)-1)
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#define TSB_TAG_CTX_SHIFT 48
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#define TSB_TAG_VA_SHIFT 22
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#define TSB_TAG_LOCKED 0x0000040000000000LL
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#define TSB_TAG_G 0x8000000000000000LL
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#define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK)
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#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
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#define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT))
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/* Page sizes */
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#define PGSZ_8K 0
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#define PGSZ_64K 1
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#define PGSZ_512K 2
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#define PGSZ_4M 3
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#define SUN4U_PGSZ_SHIFT 61
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#define SUN4U_TLB_SZ(s) (((uint64_t)(s)) << SUN4U_PGSZ_SHIFT)
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/* TLB data masks */
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#define SUN4U_TLB_V 0x8000000000000000LL
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#define SUN4U_TLB_8K SUN4U_TLB_SZ(PGSZ_8K)
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#define SUN4U_TLB_64K SUN4U_TLB_SZ(PGSZ_64K)
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#define SUN4U_TLB_512K SUN4U_TLB_SZ(PGSZ_512K)
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#define SUN4U_TLB_4M SUN4U_TLB_SZ(PGSZ_4M)
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#define SUN4U_TLB_SZ_MASK 0x6000000000000000LL
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#define SUN4U_TLB_NFO 0x1000000000000000LL
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#define SUN4U_TLB_IE 0x0800000000000000LL
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#define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL
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#define SUN4U_TLB_RESERVED_MASK 0x0003800000000000LL
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#define SUN4U_TLB_PA_MASK 0x00007fffffffe000LL
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#define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL
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/* S/W bits */
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#define SUN4U_TLB_ACCESS 0x0000000000000200LL
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#define SUN4U_TLB_MODIFY 0x0000000000000800LL
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#define SUN4U_TLB_REAL_W 0x0000000000000400LL
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#define SUN4U_TLB_TSB_LOCK 0x0000000000001000LL
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#define SUN4U_TLB_EXEC 0x0000000000000100LL
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#define SUN4U_TLB_EXEC_ONLY 0x0000000000000080LL
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/* H/W bits */
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#define SUN4U_TLB_L 0x0000000000000040LL
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#define SUN4U_TLB_CACHE_MASK 0x0000000000000030LL
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#define SUN4U_TLB_CP 0x0000000000000020LL
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#define SUN4U_TLB_CV 0x0000000000000010LL
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#define SUN4U_TLB_E 0x0000000000000008LL
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#define SUN4U_TLB_P 0x0000000000000004LL
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#define SUN4U_TLB_W 0x0000000000000002LL
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#define SUN4U_TLB_G 0x0000000000000001LL
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#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|\
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(((u_int64_t)(pa))&SUN4U_TLB_PA_MASK)|\
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((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\
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((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|\
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((ie)?SUN4U_TLB_IE:0LL))
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#define SUN4V_PGSZ_SHIFT 0
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#define SUN4V_TLB_SZ(s) (((uint64_t)(s))<<SUN4V_PGSZ_SHIFT)
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/* TLB data masks */
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#define SUN4V_TLB_V 0x8000000000000000LL
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#define SUN4V_TLB_8K SUN4V_TLB_SZ(PGSZ_8K)
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#define SUN4V_TLB_64K SUN4V_TLB_SZ(PGSZ_64K)
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#define SUN4V_TLB_512K SUN4V_TLB_SZ(PGSZ_512K)
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#define SUN4V_TLB_4M SUN4V_TLB_SZ(PGSZ_4M)
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#define SUN4V_TLB_SZ_MASK 0x000000000000000fLL
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#define SUN4V_TLB_NFO 0x4000000000000000LL
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#define SUN4V_TLB_IE 0x0000000000001000LL
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#define SUN4V_TLB_SOFT2_MASK 0x3f00000000000000LL
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#define SUN4V_TLB_PA_MASK 0x00ffffffffffe000LL
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#define SUN4V_TLB_SOFT_MASK 0x0000000000000030LL
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/* S/W bits */
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#define SUN4V_TLB_ACCESS 0x0000000000000010LL
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#define SUN4V_TLB_MODIFY 0x0000000000000020LL
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#define SUN4V_TLB_REAL_W 0x2000000000000000LL
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#define SUN4V_TLB_TSB_LOCK 0x1000000000000000LL
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#define SUN4V_TLB_EXEC SUN4V_TLB_X
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#define SUN4V_TLB_EXEC_ONLY 0x0200000000000000LL
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/* H/W bits */
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#define SUN4V_TLB_CACHE_MASK 0x0000000000000600LL
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#define SUN4V_TLB_CP 0x0000000000000400LL
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#define SUN4V_TLB_CV 0x0000000000000200LL
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#define SUN4V_TLB_E 0x0000000000000800LL
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#define SUN4V_TLB_P 0x0000000000000100LL
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#define SUN4V_TLB_X 0x0000000000000080LL
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#define SUN4V_TLB_W 0x0000000000000040LL
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#define SUN4V_TLB_G 0x0000000000000000LL
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#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
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(((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\
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((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):SUN4V_TLB_E)|\
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((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
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((ie)?SUN4V_TLB_IE:0LL))
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#endif /* _MACHINE_PTE_H_ */ |