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https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
158 lines
6.1 KiB
C
Vendored
158 lines
6.1 KiB
C
Vendored
/* $OpenBSD: trap.h,v 1.9 2022/05/19 05:43:48 miod Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
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*/
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#ifndef _MACHINE_TRAP_H_
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#define _MACHINE_TRAP_H_
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#define EXC_RSVD 0x0000 /* Reserved */
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#define EXC_RST 0x0100 /* Reset; all but IBM4xx */
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#define EXC_MCHK 0x0200 /* Machine Check */
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#define EXC_DSI 0x0300 /* Data Storage Interrupt */
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#define EXC_DSE 0x0380 /* Data Segment Interrupt */
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#define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
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#define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
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#define EXC_EXI 0x0500 /* External Interrupt */
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#define EXC_ALI 0x0600 /* Alignment Interrupt */
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#define EXC_PGM 0x0700 /* Program Interrupt */
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#define EXC_FPU 0x0800 /* Floating-point Unavailable */
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#define EXC_DECR 0x0900 /* Decrementer Interrupt */
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#define EXC_SC 0x0c00 /* System Call */
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#define EXC_TRC 0x0d00 /* Trace */
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#define EXC_FPA 0x0e00 /* Floating-point Assist */
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/* The following is only available on the 601: */
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#define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */
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/* The following are only available on 970(G5): */
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#define EXC_VECAST_G5 0x1700 /* AltiVec Assist */
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/* The following are only available on 7400(G4): */
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#define EXC_VEC 0x0f20 /* AltiVec Unavailable */
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#define EXC_VECAST_G4 0x1600 /* AltiVec Assist */
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/* The following are only available on 604/750/7400: */
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#define EXC_PERF 0x0f00 /* Performance Monitoring */
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#define EXC_BPT 0x1300 /* Instruction Breakpoint */
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#define EXC_SMI 0x1400 /* System Management Interrupt */
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/* The following are only available on 750/7400: */
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#define EXC_THRM 0x1700 /* Thermal Management Interrupt */
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/* And these are only on the 603: */
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#define EXC_IMISS 0x1000 /* Instruction translation miss */
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#define EXC_DLMISS 0x1100 /* Data load translation miss */
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#define EXC_DSMISS 0x1200 /* Data store translation miss */
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/* Power ISA 2.06+: */
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#define EXC_HDSI 0x0e00 /* Hypervisor Data Storage */
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#define EXC_HISI 0x0e20 /* Hypervisor Instruction Storage */
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#define EXC_HEA 0x0e40 /* Hypervisor Emulation Assistance */
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#define EXC_HMI 0x0e60 /* Hypervisor Maintenance */
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#define EXC_VSX 0x0f40 /* VSX Unavailable */
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/* Power ISA 2.07+: */
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#define EXC_FAC 0x0f60 /* Facility Unavailable */
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#define EXC_HFAC 0x0f80 /* Hypervisor Facility Unavailable */
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/* Power ISA 3.0+: */
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#define EXC_HVI 0x0ea0 /* Hypervisor Virtualization */
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/* The following are available on 4xx and 85xx */
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#define EXC_CRIT 0x0100 /* Critical Input Interrupt */
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#define EXC_PIT 0x1000 /* Programmable Interval Timer */
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#define EXC_FIT 0x1010 /* Fixed Interval Timer */
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#define EXC_WDOG 0x1020 /* Watchdog Timer */
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#define EXC_DTMISS 0x1100 /* Data TLB Miss */
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#define EXC_ITMISS 0x1200 /* Instruction TLB Miss */
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#define EXC_APU 0x1300 /* Auxiliary Processing Unit */
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#define EXC_DEBUG 0x2f10 /* Debug trap */
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#define EXC_VECAST_E 0x2f20 /* Altivec Assist (Book-E) */
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#define EXC_SPFPD 0x2f30 /* SPE Floating-point Data */
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#define EXC_SPFPR 0x2f40 /* SPE Floating-point Round */
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/* POWER8 */
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#define EXC_SOFT_PATCH 0x1500 /* POWER8 Soft Patch Exception */
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#define EXC_END 0x3000 /* End of exception vectors */
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#define EXC_AST 0x3000 /* Fake AST vector */
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/* Trap was in user mode */
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#define EXC_USER 0x10000
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/*
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* EXC_ALI sets bits in the DSISR and DAR to provide enough
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* information to recover from the unaligned access without needing to
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* parse the offending instruction. This includes certain bits of the
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* opcode, and information about what registers are used. The opcode
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* indicator values below come from Appendix F of Book III of "The
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* PowerPC Architecture".
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*/
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#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
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#define EXC_ALI_LFD 0x09
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#define EXC_ALI_STFD 0x0b
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/* Macros to extract register information */
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#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
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#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
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#define EXC_ALI_INST_RST(instr) ((instr >> 21) & 0x1f)
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/*
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* SRR1 bits for program exception traps. These identify what caused
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* the program exception. See section 6.5.9 of the Power ISA Version
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* 2.05.
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*/
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#define EXC_PGM_FPENABLED (1UL << 20)
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#define EXC_PGM_ILLEGAL (1UL << 19)
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#define EXC_PGM_PRIV (1UL << 18)
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#define EXC_PGM_TRAP (1UL << 17)
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/*
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* DSISR bits.
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*/
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#define DSISR_STORE (1UL << 25)
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/* Magic pointers to store trap handler entry points */
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#define TRAP_ENTRY 0x1f8
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#define TRAP_HVENTRY 0x1f0
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#define TRAP_SLBENTRY 0x1e8
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#define TRAP_RSTENTRY 0x1e0
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#endif /* _MACHINE_TRAP_H_ */ |