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66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
80 lines
2.3 KiB
C
Vendored
80 lines
2.3 KiB
C
Vendored
/* $OpenBSD: pte.h,v 1.8 2023/01/25 09:53:53 kettenis Exp $ */
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/*
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* Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* Page Table Entry bits that should work for all 64-bit POWER CPUs as
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* well as the PowerPC 970.
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*/
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struct pte {
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uint64_t pte_hi;
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uint64_t pte_lo;
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};
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/* High doubleword: */
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#define PTE_VALID 0x0000000000000001ULL
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#define PTE_HID 0x0000000000000002ULL
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#define PTE_WIRED 0x0000000000000008ULL /* SW */
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#define PTE_AVPN 0x3fffffffffffff80ULL
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#define PTE_VSID_SHIFT 12
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/* Low doubleword: */
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#define PTE_PP 0x0000000000000003ULL
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#define PTE_RO 0x0000000000000003ULL
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#define PTE_RW 0x0000000000000002ULL
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#define PTE_N 0x0000000000000004ULL
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#define PTE_G 0x0000000000000008ULL
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#define PTE_M 0x0000000000000010ULL
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#define PTE_I 0x0000000000000020ULL
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#define PTE_W 0x0000000000000040ULL
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#define PTE_CHG 0x0000000000000080ULL
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#define PTE_REF 0x0000000000000100ULL
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#define PTE_AC 0x0000000000000200ULL
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#define PTE_RPGN 0x0ffffffffffff000ULL
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#define ADDR_PIDX 0x000000000ffff000ULL
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#define ADDR_PIDX_SHIFT 12
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#define ADDR_ESID_SHIFT 28
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#define ADDR_VSID_SHIFT 28
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struct pate {
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uint64_t pate_htab;
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uint64_t pate_prt;
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};
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#define SLBE_ESID_SHIFT 28
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#define SLBE_VALID 0x0000000008000000UL
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#define SLBV_VSID_SHIFT 12
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struct slb {
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uint64_t slb_slbe;
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uint64_t slb_slbv;
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};
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#define VSID_VRMA 0x1ffffff
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#define USER_ADDR 0xcfffffff00000000ULL
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#define USER_ESID (USER_ADDR >> ADDR_ESID_SHIFT)
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#define SEGMENT_SIZE (256 * 1024 * 1024ULL)
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#define SEGMENT_MASK (SEGMENT_SIZE - 1)
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#endif /* _MACHINE_PTE_H_ */ |