mirror of
https://codeberg.org/ziglang/zig.git
synced 2026-04-28 19:47:08 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
473 lines
10 KiB
C
Vendored
473 lines
10 KiB
C
Vendored
/* $OpenBSD: cpu.h,v 1.80 2025/04/07 15:43:00 gkoehler Exp $ */
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/* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _POWERPC_CPU_H_
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#define _POWERPC_CPU_H_
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#include <machine/frame.h>
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#include <sys/clockintr.h>
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#include <sys/device.h>
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#include <sys/sched.h>
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#include <sys/srp.h>
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struct cpu_info {
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struct device *ci_dev; /* our device */
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struct schedstate_percpu ci_schedstate; /* scheduler state */
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struct proc *ci_curproc;
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struct pcb *ci_curpcb;
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struct pmap *ci_curpm;
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struct proc *ci_fpuproc;
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struct proc *ci_vecproc;
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int ci_cpuid;
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volatile int ci_want_resched;
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volatile int ci_cpl;
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volatile int ci_ipending;
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volatile int ci_dec_deferred;
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volatile int ci_flags;
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#define CI_FLAGS_SLEEPING 2
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#if defined(MULTIPROCESSOR)
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struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
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#endif
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int ci_idepth;
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char *ci_intstk;
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#define CPUSAVE_LEN 8
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register_t ci_tempsave[CPUSAVE_LEN];
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register_t ci_ddbsave[CPUSAVE_LEN];
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#define DISISAVE_LEN 4
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register_t ci_disisave[DISISAVE_LEN];
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struct clockqueue ci_queue;
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volatile int ci_ddb_paused;
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#define CI_DDB_RUNNING 0
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#define CI_DDB_SHOULDSTOP 1
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#define CI_DDB_STOPPED 2
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#define CI_DDB_ENTERDDB 3
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#define CI_DDB_INDDB 4
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u_int32_t ci_randseed;
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#ifdef DIAGNOSTIC
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int ci_mutex_level;
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#endif
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#ifdef GPROF
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struct gmonparam *ci_gmon;
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struct clockintr ci_gmonclock;
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#endif
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char ci_panicbuf[512];
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};
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static __inline struct cpu_info *
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curcpu(void)
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{
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struct cpu_info *ci;
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__asm volatile ("mfsprg %0,0" : "=r"(ci));
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return ci;
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}
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#define curpcb (curcpu()->ci_curpcb)
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#define curpm (curcpu()->ci_curpm)
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#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
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#ifdef MULTIPROCESSOR
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#define PPC_MAXPROCS 4
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static __inline int
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cpu_number(void)
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{
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int pir;
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pir = curcpu()->ci_cpuid;
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return pir;
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}
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void cpu_boot_secondary_processors(void);
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#define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
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#define CPU_IS_RUNNING(ci) 1
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) \
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for (cii = 0, ci = &cpu_info[0]; cii < ncpusfound; cii++, ci++)
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void cpu_unidle(struct cpu_info *);
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#else
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#define PPC_MAXPROCS 1
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#define cpu_number() 0
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#define CPU_IS_PRIMARY(ci) 1
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#define CPU_IS_RUNNING(ci) 1
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) \
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for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
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#define cpu_unidle(ci)
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#endif
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#define CPU_BUSY_CYCLE() do {} while (0)
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#define MAXCPUS PPC_MAXPROCS
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extern struct cpu_info cpu_info[PPC_MAXPROCS];
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#define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
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#define CLKF_PC(frame) ((frame)->srr0)
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#define CLKF_INTR(frame) ((frame)->depth > 1)
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extern int ppc_cpuidle;
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extern int ppc_proc_is_64b;
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extern int ppc_nobat;
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void cpu_bootstrap(void);
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static inline unsigned int
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cpu_rnd_messybits(void)
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{
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unsigned int hi, lo;
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__asm volatile("mftbu %0; mftb %1" : "=r" (hi), "=r" (lo));
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return (hi ^ lo);
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}
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/*
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* This is used during profiling to integrate system time.
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*/
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#define PROC_PC(p) (trapframe(p)->srr0)
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#define PROC_STACK(p) (trapframe(p)->fixreg[1])
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void delay(unsigned);
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#define DELAY(n) delay(n)
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#define aston(p) ((p)->p_md.md_astpending = 1)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched(ci) \
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do { \
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ci->ci_want_resched = 1; \
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if (ci->ci_curproc != NULL) \
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aston(ci->ci_curproc); \
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} while (0)
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#define clear_resched(ci) (ci)->ci_want_resched = 0
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#define need_proftick(p) aston(p)
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void signotify(struct proc *);
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extern char *bootpath;
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#ifndef CACHELINESIZE
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#define CACHELINESIZE 32 /* For now XXX */
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#endif
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static __inline void
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syncicache(void *from, size_t len)
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{
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size_t by, i;
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by = CACHELINESIZE;
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i = 0;
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do {
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__asm volatile ("dcbst %0,%1" :: "r"(from), "r"(i));
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i += by;
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} while (i < len);
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__asm volatile ("sync");
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i = 0;
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do {
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__asm volatile ("icbi %0,%1" :: "r"(from), "r"(i));
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i += by;
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} while (i < len);
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__asm volatile ("sync; isync");
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}
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static __inline void
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invdcache(void *from, int len)
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{
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int l;
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char *p = from;
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len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
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l = len;
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do {
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__asm volatile ("dcbi 0,%0" :: "r"(p));
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p += CACHELINESIZE;
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} while ((l -= CACHELINESIZE) > 0);
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__asm volatile ("sync");
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}
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static __inline void
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flushdcache(void *from, int len)
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{
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int l;
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char *p = from;
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len = len + (((u_int32_t) from) & (CACHELINESIZE - 1));
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l = len;
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do {
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__asm volatile ("dcbf 0,%0" :: "r"(p));
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p += CACHELINESIZE;
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} while ((l -= CACHELINESIZE) > 0);
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__asm volatile ("sync");
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}
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#define FUNC_SPR(n, name) \
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static __inline u_int32_t ppc_mf ## name(void) \
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{ \
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u_int32_t ret; \
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__asm volatile ("mfspr %0," # n : "=r" (ret)); \
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return ret; \
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} \
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static __inline void ppc_mt ## name(u_int32_t val) \
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{ \
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__asm volatile ("mtspr "# n ",%0" :: "r" (val)); \
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} \
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FUNC_SPR(0, mq)
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FUNC_SPR(1, xer)
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FUNC_SPR(4, rtcu)
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FUNC_SPR(5, rtcl)
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FUNC_SPR(8, lr)
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FUNC_SPR(9, ctr)
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FUNC_SPR(18, dsisr)
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FUNC_SPR(19, dar)
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FUNC_SPR(22, dec)
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FUNC_SPR(25, sdr1)
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FUNC_SPR(26, srr0)
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FUNC_SPR(27, srr1)
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FUNC_SPR(256, vrsave)
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FUNC_SPR(272, sprg0)
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FUNC_SPR(273, sprg1)
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FUNC_SPR(274, sprg2)
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FUNC_SPR(275, sprg3)
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FUNC_SPR(280, asr)
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FUNC_SPR(282, ear)
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FUNC_SPR(287, pvr)
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FUNC_SPR(311, hior)
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FUNC_SPR(528, ibat0u)
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FUNC_SPR(529, ibat0l)
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FUNC_SPR(530, ibat1u)
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FUNC_SPR(531, ibat1l)
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FUNC_SPR(532, ibat2u)
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FUNC_SPR(533, ibat2l)
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FUNC_SPR(534, ibat3u)
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FUNC_SPR(535, ibat3l)
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FUNC_SPR(560, ibat4u)
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FUNC_SPR(561, ibat4l)
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FUNC_SPR(562, ibat5u)
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FUNC_SPR(563, ibat5l)
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FUNC_SPR(564, ibat6u)
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FUNC_SPR(565, ibat6l)
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FUNC_SPR(566, ibat7u)
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FUNC_SPR(567, ibat7l)
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FUNC_SPR(536, dbat0u)
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FUNC_SPR(537, dbat0l)
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FUNC_SPR(538, dbat1u)
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FUNC_SPR(539, dbat1l)
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FUNC_SPR(540, dbat2u)
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FUNC_SPR(541, dbat2l)
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FUNC_SPR(542, dbat3u)
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FUNC_SPR(543, dbat3l)
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FUNC_SPR(568, dbat4u)
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FUNC_SPR(569, dbat4l)
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FUNC_SPR(570, dbat5u)
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FUNC_SPR(571, dbat5l)
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FUNC_SPR(572, dbat6u)
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FUNC_SPR(573, dbat6l)
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FUNC_SPR(574, dbat7u)
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FUNC_SPR(575, dbat7l)
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FUNC_SPR(1009, hid1)
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FUNC_SPR(1010, iabr)
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FUNC_SPR(1017, l2cr)
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FUNC_SPR(1018, l3cr)
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FUNC_SPR(1013, dabr)
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FUNC_SPR(1023, pir)
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static __inline u_int32_t
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ppc_mftbl(void)
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{
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int ret;
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__asm volatile ("mftb %0" : "=r" (ret));
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return ret;
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}
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static __inline u_int64_t
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ppc_mftb(void)
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{
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u_long scratch;
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u_int64_t tb;
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__asm volatile ("1: mftbu %0; mftb %L0; mftbu %1;"
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" cmpw 0,%0,%1; bne 1b" : "=r"(tb), "=r"(scratch));
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return tb;
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}
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static __inline void
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ppc_mttb(u_int64_t tb)
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{
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__asm volatile ("mttbl %0" :: "r"(0));
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__asm volatile ("mttbu %0" :: "r"((u_int32_t)(tb >> 32)));
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__asm volatile ("mttbl %0" :: "r"((u_int32_t)(tb & 0xffffffff)));
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}
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static __inline u_int32_t
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ppc_mfmsr(void)
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{
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int ret;
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__asm volatile ("mfmsr %0" : "=r" (ret));
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return ret;
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}
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static __inline void
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ppc_mtmsr(u_int32_t val)
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{
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__asm volatile ("mtmsr %0" :: "r" (val));
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}
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static __inline void
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ppc_mtsrin(u_int32_t val, u_int32_t sn_shifted)
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{
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__asm volatile ("mtsrin %0,%1" :: "r"(val), "r"(sn_shifted));
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}
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u_int64_t ppc64_mfscomc(void);
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void ppc_mtscomc(u_int32_t);
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void ppc64_mtscomc(u_int64_t);
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u_int64_t ppc64_mfscomd(void);
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void ppc_mtscomd(u_int32_t);
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u_int32_t ppc_mfhid0(void);
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void ppc_mthid0(u_int32_t);
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u_int64_t ppc64_mfhid1(void);
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void ppc64_mthid1(u_int64_t);
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u_int64_t ppc64_mfhid4(void);
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void ppc64_mthid4(u_int64_t);
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u_int64_t ppc64_mfhid5(void);
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void ppc64_mthid5(u_int64_t);
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#include <machine/psl.h>
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/*
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* General functions to enable and disable interrupts
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* without having inlined assembly code in many functions.
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*/
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static __inline void
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ppc_intr_enable(int enable)
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{
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u_int32_t msr;
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if (enable != 0) {
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msr = ppc_mfmsr();
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msr |= PSL_EE;
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ppc_mtmsr(msr);
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}
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}
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static __inline int
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ppc_intr_disable(void)
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{
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u_int32_t emsr, dmsr;
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emsr = ppc_mfmsr();
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dmsr = emsr & ~PSL_EE;
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ppc_mtmsr(dmsr);
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return (emsr & PSL_EE);
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}
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static inline void
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intr_enable(void)
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{
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ppc_mtmsr(ppc_mfmsr() | PSL_EE);
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}
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static __inline u_long
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intr_disable(void)
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{
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return ppc_intr_disable();
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}
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static __inline void
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intr_restore(u_long s)
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{
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ppc_intr_enable(s);
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}
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int ppc_cpuspeed(int *);
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/*
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* PowerPC CPU types
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*/
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#define PPC_CPU_MPC601 1
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#define PPC_CPU_MPC603 3
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#define PPC_CPU_MPC604 4
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#define PPC_CPU_MPC603e 6
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#define PPC_CPU_MPC603ev 7
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#define PPC_CPU_MPC750 8
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#define PPC_CPU_MPC604ev 9
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#define PPC_CPU_MPC7400 12
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#define PPC_CPU_IBM970 0x0039
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#define PPC_CPU_IBM970FX 0x003c
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#define PPC_CPU_IBM970MP 0x0044
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#define PPC_CPU_IBM750FX 0x7000
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#define PPC_CPU_MPC7410 0x800c
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#define PPC_CPU_MPC7447A 0x8003
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#define PPC_CPU_MPC7448 0x8004
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#define PPC_CPU_MPC7450 0x8000
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#define PPC_CPU_MPC7455 0x8001
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#define PPC_CPU_MPC7457 0x8002
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#define PPC_CPU_MPC83xx 0x8083
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/*
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* This needs to be included late since it relies on definitions higher
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* up in this file.
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*/
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#if defined(MULTIPROCESSOR) && defined(_KERNEL)
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#include <sys/mplock.h>
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#endif
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#endif /* _POWERPC_CPU_H_ */ |