mirror of
https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
643 lines
21 KiB
C
Vendored
643 lines
21 KiB
C
Vendored
/* $OpenBSD: bus.h,v 1.27 2024/05/22 05:51:49 jsg Exp $ */
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/*
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* Copyright (c) 1997 Per Fogelstrom. All rights reserved.
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* Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_BUS_H_
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#define _MACHINE_BUS_H_
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#include <machine/pio.h>
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#ifdef __STDC__
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#define CAT(a,b) a##b
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#define CAT3(a,b,c) a##b##c
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#else
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#define CAT(a,b) a/**/b
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#define CAT3(a,b,c) a/**/b/**/c
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#endif
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/*
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* Bus access types.
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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typedef u_long bus_space_handle_t;
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typedef struct ppc_bus_space *bus_space_tag_t;
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struct ppc_bus_space {
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u_int32_t bus_base;
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u_int32_t bus_size;
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u_int8_t bus_io; /* IO or memory */
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};
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#define POWERPC_BUS_TAG_BASE(x) ((x)->bus_base)
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/*
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* Access methods for bus resources
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*/
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int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
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bus_size_t size, int flags, bus_space_handle_t *bshp);
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void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
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bus_size_t size);
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int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
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bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
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int bus_space_alloc(bus_space_tag_t tag, bus_addr_t rstart,
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bus_addr_t rend, bus_size_t size, bus_size_t alignment,
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bus_size_t boundary, int flags, bus_addr_t *addrp,
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bus_space_handle_t *handlep);
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void bus_space_free(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_size_t size);
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paddr_t bus_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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#define BUS_SPACE_MAP_PREFETCHABLE 0x04
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/*
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* void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t);
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*
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* Get the kernel virtual address for the mapped bus space.
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* Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR.
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*/
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#define bus_space_vaddr(t, h) ((void *)(h))
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#define bus_space_read(n,m) \
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static __inline CAT3(u_int,m,_t) \
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CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba) \
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{ \
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return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \
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}
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bus_space_read(1,8)
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bus_space_read(2,16)
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bus_space_read(4,32)
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#define bus_space_read_8 !!! bus_space_read_8 unimplemented !!!
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#define bus_space_write(n,m) \
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static __inline void \
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CAT(bus_space_write_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba, CAT3(u_int,m,_t) x) \
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{ \
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CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \
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}
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bus_space_write(1,8)
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bus_space_write(2,16)
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bus_space_write(4,32)
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#define bus_space_write_8 !!! bus_space_write_8 unimplemented !!!
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#define bus_space_read_raw(n,m) \
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static __inline CAT3(u_int,m,_t) \
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CAT(bus_space_read_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba) \
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{ \
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return CAT(in,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba))); \
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}
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bus_space_read_raw(1,8)
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bus_space_read_raw(2,16)
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bus_space_read_raw(4,32)
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#define bus_space_read_raw_8 !!! bus_space_read_raw_8 unimplemented !!!
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#define bus_space_write_raw(n,m) \
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static __inline void \
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CAT(bus_space_write_raw_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_addr_t ba, CAT3(u_int,m,_t) x) \
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{ \
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CAT(out,m)((volatile CAT3(u_int,m,_t) *)(bsh + (ba)), x); \
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}
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bus_space_write_raw(1,8)
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bus_space_write_raw(2,16)
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bus_space_write_raw(4,32)
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#define bus_space_write_raw_8 !!! bus_space_write_raw_8 unimplemented !!!
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#define bus_space_read_multi(n, m) \
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static __inline void \
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CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
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{ \
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while (cnt--) \
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*buf++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
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}
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bus_space_read_multi(1,8)
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bus_space_read_multi(2,16)
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bus_space_read_multi(4,32)
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#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!!
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#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
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#define bus_space_write_multi(n, m) \
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static __inline void \
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CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
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bus_size_t ba, const CAT3(u_int,m,_t) *buf, bus_size_t cnt) \
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{ \
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while (cnt--) \
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CAT(bus_space_write_,n)(bst, bsh, ba, *buf++); \
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}
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bus_space_write_multi(1,8)
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bus_space_write_multi(2,16)
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bus_space_write_multi(4,32)
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#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!!
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/*
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* void bus_space_read_region_N(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* u_intN_t *addr, size_t count);
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*
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* Read `count' 1, 2, 4, or 8 byte quantities from bus space
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* described by tag/handle and starting at `offset' and copy into
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* buffer provided.
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*/
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#define __BA(t, h, o) ((void *)((h) + (o)))
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static __inline void
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bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t *addr, size_t count)
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{
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volatile u_int8_t *s = __BA(tag, bsh, offset);
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while (count--)
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*addr++ = *s++;
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t *addr, size_t count)
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{
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volatile u_int16_t *s = __BA(tag, bsh, offset);
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while (count--)
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__asm volatile("lhbrx %0, 0, %1" :
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"=r"(*addr++) : "r"(s++));
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int32_t *addr, size_t count)
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{
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volatile u_int32_t *s = __BA(tag, bsh, offset);
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while (count--)
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__asm volatile("lwbrx %0, 0, %1" :
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"=r"(*addr++) : "r"(s++));
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__asm volatile("eieio; sync");
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}
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#if 0 /* Cause a link error for bus_space_read_region_8 */
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#define bus_space_read_region_8 !!! unimplemented !!!
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#endif
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/*
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* void bus_space_write_region_N(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* const u_intN_t *addr, size_t count);
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*
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* Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
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* to bus space described by tag/handle starting at `offset'.
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*/
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static __inline void
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bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, const u_int8_t *addr, size_t count)
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{
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volatile u_int8_t *d = __BA(tag, bsh, offset);
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while (count--)
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*d++ = *addr++;
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, const u_int16_t *addr, size_t count)
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{
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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while (count--)
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__asm volatile("sthbrx %0, 0, %1" ::
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"r"(*addr++), "r"(d++));
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, const u_int32_t *addr, size_t count)
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{
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volatile u_int32_t *d = __BA(tag, bsh, offset);
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while (count--)
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__asm volatile("stwbrx %0, 0, %1" ::
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"r"(*addr++), "r"(d++));
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__asm volatile("eieio; sync");
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}
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#if 0
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#define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!!
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#endif
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/*
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* void bus_space_read_raw_region_N(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* u_intN_t *addr, size_t count);
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*
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* Read `count' bytes from bus space described by tag/handle and starting
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* at `offset' and copy into buffer provided w/o bus-host byte swapping.
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*/
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static __inline void
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bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t *addr, size_t count)
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{
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volatile u_int16_t *s = __BA(tag, bsh, offset);
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u_int16_t *laddr = (void *)addr;
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count = count >> 1;
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while (count--)
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*laddr++ = *s++;
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t *addr, size_t count)
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{
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volatile u_int32_t *s = __BA(tag, bsh, offset);
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u_int32_t *laddr = (void *)addr;
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count = count >> 2;
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while (count--)
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*laddr++ = *s++;
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__asm volatile("eieio; sync");
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}
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#if 0 /* Cause a link error for bus_space_read_raw_region_8 */
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#define bus_space_read_raw_region_8 \
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!!! bus_space_read_raw_region_8 unimplemented !!!
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#endif
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/*
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* void bus_space_write_raw_region_N(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* const u_intN_t *addr, size_t count);
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*
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* Write `count' bytes from the buffer provided to bus space described
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* by tag/handle starting at `offset' w/o host-bus byte swapping.
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*/
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static __inline void
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bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, const u_int8_t *addr, size_t count)
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{
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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const u_int16_t *laddr = (void *)addr;
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count = count >> 1;
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while (count--)
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*d++ = *laddr++;
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__asm volatile("eieio; sync");
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}
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static __inline void
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bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, const u_int8_t *addr, size_t count)
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{
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volatile u_int32_t *d = __BA(tag, bsh, offset);
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const u_int32_t *laddr = (void *)addr;
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count = count >> 2;
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while (count--)
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*d++ = *laddr++;
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__asm volatile("eieio; sync");
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}
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#if 0
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#define bus_space_write_raw_region_8 \
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!!! bus_space_write_raw_region_8 unimplemented !!!
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#endif
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/*
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* void bus_space_set_multi_N(bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
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* size_t count);
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*
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* Write the 1, 2, 4, or 8 byte value `val' to bus space described
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* by tag/handle/offset `count' times.
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*/
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static __inline void bus_space_set_multi_1(bus_space_tag_t,
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bus_space_handle_t, bus_size_t, u_int8_t, size_t);
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static __inline void bus_space_set_multi_2(bus_space_tag_t,
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bus_space_handle_t, bus_size_t, u_int16_t, size_t);
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static __inline void bus_space_set_multi_4(bus_space_tag_t,
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bus_space_handle_t, bus_size_t, u_int32_t, size_t);
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static __inline void
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bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t val, size_t count)
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{
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volatile u_int8_t *d = __BA(tag, bsh, offset);
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while (count--)
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*d = val;
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__asm__ volatile("eieio; sync");
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}
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static __inline void
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bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t val, size_t count)
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{
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volatile u_int16_t *d = __BA(tag, bsh, offset);
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while (count--)
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__asm__ volatile("sthbrx %0, 0, %1" ::
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"r"(val), "r"(d));
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__asm__ volatile("eieio; sync");
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}
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static __inline void
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bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
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bus_size_t offset, u_int32_t val, size_t count)
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{
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volatile u_int32_t *d = __BA(tag, bsh, offset);
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while (count--)
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__asm__ volatile("stwbrx %0, 0, %1" ::
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"r"(val), "r"(d));
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__asm__ volatile("eieio; sync");
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}
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#define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!!
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/* These are OpenBSD extensions to the general NetBSD bus interface. */
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void
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bus_space_read_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_addr_t ba, u_int8_t *dst, bus_size_t size);
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void
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bus_space_read_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_addr_t ba, u_int8_t *dst, bus_size_t size);
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#define bus_space_read_raw_multi_8 \
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!!! bus_space_read_raw_multi_8 not implemented !!!
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void
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bus_space_write_raw_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_addr_t ba, const u_int8_t *src, bus_size_t size);
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void
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bus_space_write_raw_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_addr_t ba, const u_int8_t *src, bus_size_t size);
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#define bus_space_write_raw_multi_8 \
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!!! bus_space_write_raw_multi_8 not implemented !!!
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void
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bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
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u_int8_t val, bus_size_t c);
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void
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bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
|
|
u_int16_t val, bus_size_t c);
|
|
void
|
|
bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t h, bus_size_t o,
|
|
u_int32_t val, bus_size_t c);
|
|
#define bus_space_set_region_8 \
|
|
!!! bus_space_set_region_8 not implemented !!!
|
|
|
|
void
|
|
bus_space_copy_1(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
|
|
bus_size_t o1, bus_size_t o2, bus_size_t c);
|
|
void
|
|
bus_space_copy_2(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
|
|
bus_size_t o1, bus_size_t o2, bus_size_t c);
|
|
void
|
|
bus_space_copy_4(void *v, bus_space_handle_t h1, bus_space_handle_t h2,
|
|
bus_size_t o1, bus_size_t o2, bus_size_t c);
|
|
#define bus_space_copy_8 \
|
|
!!! bus_space_copy_8 not implemented !!!
|
|
|
|
/*
|
|
* Bus read/write barrier methods.
|
|
*
|
|
* void bus_space_barrier(bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* bus_size_t len, int flags);
|
|
*
|
|
* Note: powerpc does not currently implement barriers, but we must
|
|
* provide the flags to MI code.
|
|
* the processor does have eieio which is effectively the barrier
|
|
* operator, however due to how memory is mapped this should? not
|
|
* be required.
|
|
*/
|
|
#define bus_space_barrier(t, h, o, l, f) \
|
|
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
|
|
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
|
|
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
|
|
|
|
#define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */
|
|
#define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */
|
|
#define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */
|
|
#define BUS_DMA_COHERENT 0x0008 /* hint: map memory DMA coherent */
|
|
#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
|
|
#define BUS_DMA_BUS2 0x0020
|
|
#define BUS_DMA_BUS3 0x0040
|
|
#define BUS_DMA_BUS4 0x0080
|
|
#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
|
|
#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
|
|
#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
|
|
#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
|
|
#define BUS_DMA_NOCACHE 0x1000 /* map memory uncached */
|
|
#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
|
|
|
|
|
|
/* Forwards needed by prototypes below. */
|
|
struct mbuf;
|
|
struct proc;
|
|
struct uio;
|
|
|
|
#define BUS_DMASYNC_POSTREAD 0x01
|
|
#define BUS_DMASYNC_POSTWRITE 0x02
|
|
#define BUS_DMASYNC_PREREAD 0x04
|
|
#define BUS_DMASYNC_PREWRITE 0x08
|
|
|
|
typedef struct powerpc_bus_dma_tag *bus_dma_tag_t;
|
|
typedef struct powerpc_bus_dmamap *bus_dmamap_t;
|
|
|
|
/*
|
|
* bus_dma_segment_t
|
|
*
|
|
* Describes a single contiguous DMA transaction. Values
|
|
* are suitable for programming into DMA registers.
|
|
*/
|
|
struct powerpc_bus_dma_segment {
|
|
bus_addr_t ds_addr; /* DMA address */
|
|
bus_size_t ds_len; /* length of transfer */
|
|
};
|
|
typedef struct powerpc_bus_dma_segment bus_dma_segment_t;
|
|
|
|
/*
|
|
* bus_dma_tag_t
|
|
*
|
|
* A machine-dependent opaque type describing the implementation of
|
|
* DMA for a given bus.
|
|
*/
|
|
|
|
struct powerpc_bus_dma_tag {
|
|
void *_cookie; /* cookie used in the guts */
|
|
|
|
/*
|
|
* DMA mapping methods.
|
|
*/
|
|
int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
|
|
bus_size_t, bus_size_t, int, bus_dmamap_t *);
|
|
void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
|
|
int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
|
|
bus_size_t, struct proc *, int);
|
|
int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
|
|
struct mbuf *, int);
|
|
int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
|
|
struct uio *, int);
|
|
int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
|
|
bus_dma_segment_t *, int, bus_size_t, int);
|
|
void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
|
|
void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
|
|
bus_addr_t, bus_size_t, int);
|
|
|
|
/*
|
|
* DMA memory utility functions.
|
|
*/
|
|
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int);
|
|
int (*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int,
|
|
bus_addr_t, bus_addr_t);
|
|
void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
|
|
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, size_t, caddr_t *, int);
|
|
void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
|
|
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, off_t, int, int);
|
|
};
|
|
|
|
#define bus_dmamap_create(t, s, n, m, b, f, p) \
|
|
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
|
|
#define bus_dmamap_destroy(t, p) \
|
|
(*(t)->_dmamap_destroy)((t), (p))
|
|
#define bus_dmamap_load(t, m, b, s, p, f) \
|
|
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
|
|
#define bus_dmamap_load_mbuf(t, m, b, f) \
|
|
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
|
|
#define bus_dmamap_load_uio(t, m, u, f) \
|
|
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
|
|
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
|
|
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
|
|
#define bus_dmamap_unload(t, p) \
|
|
(*(t)->_dmamap_unload)((t), (p))
|
|
#define bus_dmamap_sync(t, p, a, l, o) \
|
|
(void)((t)->_dmamap_sync ? \
|
|
(*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
|
|
|
|
#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
|
|
(*(t)->_dmamem_alloc)((t)->_cookie, (s), (a), (b), (sg), (n), (r), (f))
|
|
#define bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h) \
|
|
(*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg), \
|
|
(n), (r), (f), (l), (h))
|
|
#define bus_dmamem_free(t, sg, n) \
|
|
(*(t)->_dmamem_free)((t)->_cookie, (sg), (n))
|
|
#define bus_dmamem_map(t, sg, n, s, k, f) \
|
|
(*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
|
|
#define bus_dmamem_unmap(t, k, s) \
|
|
(*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
|
|
#define bus_dmamem_mmap(t, sg, n, o, p, f) \
|
|
(*(t)->_dmamem_mmap)((t)->_cookie, (sg), (n), (o), (p), (f))
|
|
|
|
int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
|
|
bus_size_t, bus_size_t, int, bus_dmamap_t *);
|
|
void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
|
|
int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
|
|
bus_size_t, struct proc *, int);
|
|
int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
|
|
int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
|
|
int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
|
|
bus_dma_segment_t *, int, bus_size_t, int);
|
|
void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
|
|
void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, bus_size_t,
|
|
int);
|
|
|
|
int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int);
|
|
int _dmamem_alloc_range( bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int,
|
|
bus_addr_t, bus_addr_t);
|
|
void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
|
|
int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, size_t, caddr_t *, int);
|
|
void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
|
|
paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
|
|
|
|
/*
|
|
* bus_dmamap_t
|
|
*
|
|
* Describes a DMA mapping.
|
|
*/
|
|
struct powerpc_bus_dmamap {
|
|
/*
|
|
* PRIVATE MEMBERS: not for use by machine-independent code.
|
|
*/
|
|
bus_size_t _dm_size; /* largest DMA transfer mappable */
|
|
int _dm_segcnt; /* number of segs this map can map */
|
|
bus_size_t _dm_maxsegsz; /* largest possible segment */
|
|
bus_size_t _dm_boundary; /* don't cross this */
|
|
int _dm_flags; /* misc. flags */
|
|
|
|
void *_dm_cookie; /* cookie for bus-specific functions */
|
|
|
|
/*
|
|
* PUBLIC MEMBERS: these are used by machine-independent code.
|
|
*/
|
|
bus_size_t dm_mapsize; /* size of the mapping */
|
|
int dm_nsegs; /* # valid segments in mapping */
|
|
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
|
|
};
|
|
|
|
#endif /* _MACHINE_BUS_H_ */ |