mirror of
https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
108 lines
3.3 KiB
C
Vendored
108 lines
3.3 KiB
C
Vendored
/* $OpenBSD: loongson3.h,v 1.3 2017/05/10 16:04:21 visa Exp $ */
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/*
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* Copyright (c) 2016 Visa Hankala
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _MIPS64_LOONGSON3_H_
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#define _MIPS64_LOONGSON3_H_
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/*
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* Definitions for Loongson 3A.
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*/
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#define LS3_CFG_BASE(node) (0x100000004000ull*(node) + 0x3ff00000)
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#define LS3_MEM_BASE(node) (0x100000000000ull*(node))
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#define LS3_IPI_BASE(n, c) (LS3_CFG_BASE(n) + 0x1000 + 0x100*(c))
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#define LS3_IPI_ISR 0x00
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#define LS3_IPI_IMR 0x04
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#define LS3_IPI_SET 0x08
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#define LS3_IPI_CLEAR 0x0c
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#define LS3_IPI_MBOX0 0x20
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#define LS3_IPI_MBOX1 0x28
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#define LS3_IPI_MBOX2 0x30
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#define LS3_IPI_MBOX3 0x38
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static inline uint32_t
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loongson3_get_cpuid(void)
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{
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uint32_t tmp;
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asm volatile (
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" .set push\n"
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" .set mips64\n"
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" mfc0 %0, $15, 1\n" /* EBase */
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" .set pop\n"
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: "=r" (tmp));
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return tmp & 0xf;
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}
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#define LS3_COREID(cpuid) ((cpuid) & 3)
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#define LS3_NODEID(cpuid) ((cpuid) >> 2)
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/*
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* Interrupt router registers
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*/
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#define LS3_IRT_ENTRY(node, irq) (LS3_CFG_BASE(node) + 0x1400 + (irq))
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#define LS3_IRT_INTISR(node) (LS3_CFG_BASE(node) + 0x1420)
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#define LS3_IRT_INTEN(node) (LS3_CFG_BASE(node) + 0x1424)
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#define LS3_IRT_INTENSET(node) (LS3_CFG_BASE(node) + 0x1428)
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#define LS3_IRT_INTENCLR(node) (LS3_CFG_BASE(node) + 0x142c)
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#define LS3_IRT_INTISR_CORE(node, cpu) (LS3_CFG_BASE(node) + 0x1440 + (cpu)*8)
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/* sys int 0-3 */
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#define LS3_IRT_ENTRY_INT(node, x) LS3_IRT_ENTRY((node), (x))
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/* PCI int 0-3 */
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#define LS3_IRT_ENTRY_PCI(node, x) LS3_IRT_ENTRY((node), 0x04+(x))
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/* LPC int */
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#define LS3_IRT_ENTRY_LPC(node) LS3_IRT_ENTRY((node), 0x0a)
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/* HT0 int 0-7 */
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#define LS3_IRT_ENTRY_HT0(node, x) LS3_IRT_ENTRY((node), 0x10+(x))
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/* HT1 int 0-7 */
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#define LS3_IRT_ENTRY_HT1(node, x) LS3_IRT_ENTRY((node), 0x18+(x))
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#define LS3_IRT_ROUTE(core, intr) ((0x01 << (core)) | (0x10 << (intr)))
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#define LS3_IRQ_INT(x) (x) /* sys int 0-3 */
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#define LS3_IRQ_PCI(x) ((x) + 0x04) /* PCI int 0-3 */
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#define LS3_IRQ_LPC 0x0a /* LPC int */
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#define LS3_IRQ_HT0(x) ((x) + 0x10) /* HT0 int 0-7 */
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#define LS3_IRQ_HT1(x) ((x) + 0x18) /* HT1 int 0-7 */
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#define LS3_IRQ_NUM 32
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#define LS3_IRQ_IS_HT(irq) ((irq) >= 0x10)
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#define LS3_IRQ_HT_MASK 0xffff0000u
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/*
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* Number of HyperTransport interrupt vectors. In reality, each HT interface
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* has 256 vectors, but the interrupt code uses only a subset of them.
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*/
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#define LS3_HT_IRQ_NUM 32
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/*
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* HyperTransport registers
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*/
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#define LS3_HT1_MEM_BASE(n) (LS3_MEM_BASE(n)+0x00000e0000000000ull)
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#define LS3_HT1_CFG_BASE(n) (LS3_MEM_BASE(n)+0x00000efdfb000000ull)
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#define LS3_HT_ISR_OFFSET(x) (0x80 + (x) * 4)
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#define LS3_HT_IMR_OFFSET(x) (0xa0 + (x) * 4)
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#endif /* _MIPS64_LOONGSON3_H_ */ |