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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
232 lines
8.7 KiB
C
Vendored
232 lines
8.7 KiB
C
Vendored
/* $OpenBSD: pte.h,v 1.10 2021/03/11 11:16:55 jsg Exp $ */
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/* $NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_PTE_H_
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#define _ARM_PTE_H_
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/*
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* The ARM MMU architecture was introduced with ARM v3 (previous ARM
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* architecture versions used an optional off-CPU memory controller
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* to perform address translation).
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*
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* The ARM MMU consists of a TLB and translation table walking logic.
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* There is typically one TLB per memory interface (or, put another
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* way, one TLB per software-visible cache).
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*
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* The ARM MMU is capable of mapping memory in the following chunks:
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*
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* 1M Sections (L1 table)
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*
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* 64K Large Pages (L2 table)
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*
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* 4K Small Pages (L2 table)
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*
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* 1K Tiny Pages (L2 table)
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*
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* There are two types of L2 tables: Coarse Tables and Fine Tables.
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* Coarse Tables can map Large and Small Pages. Fine Tables can
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* map Tiny Pages.
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*
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* Coarse Tables can define 4 Subpages within Large and Small pages.
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* Subpages define different permissions for each Subpage within
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* a Page.
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*
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* Coarse Tables are 1K in length. Fine tables are 4K in length.
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*
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* The Translation Table Base register holds the pointer to the
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* L1 Table. The L1 Table is a 16K contiguous chunk of memory
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* aligned to a 16K boundary. Each entry in the L1 Table maps
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* 1M of virtual address space, either via a Section mapping or
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* via an L2 Table.
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*
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* In addition, the Fast Context Switching Extension (FCSE) is available
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* on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
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* TLB/cache flushes on context switch by use of a smaller address space
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* and a "process ID" that modifies the virtual address before being
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* presented to the translation logic.
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*/
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#ifndef _LOCORE
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typedef uint32_t pd_entry_t; /* L1 table entry */
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typedef uint32_t pt_entry_t; /* L2 table entry */
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#endif /* _LOCORE */
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#define L1_S_SIZE 0x00100000 /* 1M */
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#define L1_S_OFFSET (L1_S_SIZE - 1)
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#define L1_S_FRAME (~L1_S_OFFSET)
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#define L1_S_SHIFT 20
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#define L2_L_SIZE 0x00010000 /* 64K */
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#define L2_L_OFFSET (L2_L_SIZE - 1)
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#define L2_L_FRAME (~L2_L_OFFSET)
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#define L2_L_SHIFT 16
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#define L2_S_SIZE 0x00001000 /* 4K */
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#define L2_S_OFFSET (L2_S_SIZE - 1)
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#define L2_S_FRAME (~L2_S_OFFSET)
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#define L2_S_SHIFT 12
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#define L2_T_SIZE 0x00000400 /* 1K */
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#define L2_T_OFFSET (L2_T_SIZE - 1)
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#define L2_T_FRAME (~L2_T_OFFSET)
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#define L2_T_SHIFT 10
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/*
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* The NetBSD VM implementation only works on whole pages (4K),
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* whereas the ARM MMU's Coarse tables are sized in terms of 1K
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* (16K L1 table, 1K L2 table).
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*
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* So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
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* table.
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*/
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#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
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#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
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#define L1_TABLE_SIZE 0x4000 /* 16K */
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#define L2_TABLE_SIZE 0x1000 /* 4K */
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/*
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* The new pmap deals with the 1KB coarse L2 tables by
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* allocating them from a pool. Until every port has been converted,
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* keep the old L2_TABLE_SIZE define lying around. Converted ports
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* should use L2_TABLE_SIZE_REAL until then.
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*/
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#define L2_TABLE_SIZE_REAL 0x400 /* 1K */
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/*
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* ARM L1 Descriptors
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*/
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#define L1_TYPE_INV 0x00 /* Invalid (fault) */
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#define L1_TYPE_C 0x01 /* Coarse L2 */
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#define L1_TYPE_S 0x02 /* Section or Supersection */
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#define L1_TYPE_F 0x03 /* Fine L2 (pre-V7) */
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#define L1_TYPE_MASK 0x03 /* mask of type bits */
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/* L1 Section Descriptor */
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#define L1_S_B 0x00000004 /* bufferable Section */
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#define L1_S_C 0x00000008 /* cacheable Section */
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#define L1_S_IMP 0x00000010 /* implementation defined */
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#define L1_S_DOM(x) ((x) << 5) /* domain */
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#define L1_S_DOM_MASK L1_S_DOM(0xf)
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#define L1_S_AP(x) ((x) << 10) /* access permissions */
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#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
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#define L1_S_V7_TEX(x) (((x) & 0x7) << 12) /* Type Extension */
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#define L1_S_V7_TEX_MASK (0x7 << 12) /* Type Extension */
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#define L1_S_V7_NS 0x00080000 /* Non-secure */
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#define L1_S_V7_SS 0x00040000 /* Supersection */
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#define L1_S_V7_nG 0x00020000 /* not Global */
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#define L1_S_V7_S 0x00010000 /* Shareable */
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#define L1_S_V7_AP(x) ((((x) & 0x4) << 13) | (((x) & 0x2) << 10)) /* AP */
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#define L1_S_V7_AF 0x00000400 /* Access Flag */
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#define L1_S_V7_IMP 0x00000200 /* implementation defined */
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#define L1_S_V7_XN 0x00000010 /* eXecute Never */
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#define L1_S_V7_PXN 0x00000001 /* Privileged eXecute Never */
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/* L1 Coarse Descriptor */
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#define L1_C_IMP0 0x00000004 /* implementation defined */
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#define L1_C_IMP1 0x00000008 /* implementation defined */
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#define L1_C_IMP2 0x00000010 /* implementation defined */
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#define L1_C_DOM(x) ((x) << 5) /* domain */
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#define L1_C_DOM_MASK L1_C_DOM(0xf)
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#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
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#define L1_C_V7_IMP 0x00000200 /* implementation defined */
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#define L1_C_V7_NS 0x00000008 /* Non-secure */
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#define L1_C_V7_PXN 0x00000004 /* Privileged eXecute Never */
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/* L1 Fine Descriptor */
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#define L1_F_IMP0 0x00000004 /* implementation defined */
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#define L1_F_IMP1 0x00000008 /* implementation defined */
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#define L1_F_IMP2 0x00000010 /* implementation defined */
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#define L1_F_DOM(x) ((x) << 5) /* domain */
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#define L1_F_DOM_MASK L1_F_DOM(0xf)
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#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
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/*
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* ARM L2 Descriptors
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*/
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#define L2_TYPE_INV 0x00 /* Invalid (fault) */
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#define L2_TYPE_L 0x01 /* Large Page */
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#define L2_TYPE_S 0x02 /* Small Page */
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#define L2_TYPE_T 0x03 /* Tiny Page (pre-V7) */
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#define L2_TYPE_MASK 0x03 /* mask of type bits */
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#define L2_B 0x00000004 /* Bufferable page */
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#define L2_C 0x00000008 /* Cacheable page */
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#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
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#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
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#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
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#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
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#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
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#define L2_V7_L_TEX(x) (((x) & 0x7) << 12) /* Type Extension */
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#define L2_V7_L_TEX_MASK (0x7 << 12) /* Type Extension */
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#define L2_V7_L_XN 0x00008000 /* eXecute Never */
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#define L2_V7_S_TEX(x) (((x) & 0x7) << 6) /* Type Extension */
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#define L2_V7_S_TEX_MASK (0x7 << 6) /* Type Extension */
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#define L2_V7_S_XN 0x00000001 /* eXecute Never */
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#define L2_V7_AP(x) ((((x) & 0x4) << 7) | (((x) & 0x2) << 4)) /* AP */
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#define L2_V7_AF 0x00000010 /* Access Flag */
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#define L2_V7_S 0x00000400 /* Shareable */
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#define L2_V7_nG 0x00000800 /* not Global */
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/*
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* Short-hand for common AP_* constants.
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*
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* Note: These values assume the S (System) bit is set and
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* the R (ROM) bit is clear in CP15 register 1.
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*/
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#define AP_KR 0x00 /* kernel read */
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#define AP_V7_KR 0x05
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#define AP_KRW 0x01 /* kernel read/write */
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#define AP_KRWUR 0x02 /* kernel read/write usr read */
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#define AP_V7_KRUR 0x07 /* kernel read usr read */
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#define AP_KRWURW 0x03 /* kernel read/write usr read/write */
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/*
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* Domain Types for the Domain Access Control Register.
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*/
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#define DOMAIN_FAULT 0x00 /* no access */
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#define DOMAIN_CLIENT 0x01 /* client */
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#define DOMAIN_RESERVED 0x02 /* reserved */
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#define DOMAIN_MANAGER 0x03 /* manager */
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#endif /* _ARM_PTE_H_ */ |