mirror of
https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
392 lines
15 KiB
C
Vendored
392 lines
15 KiB
C
Vendored
/* $OpenBSD: armreg.h,v 1.43 2019/09/30 21:48:32 kettenis Exp $ */
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/* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */
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/*
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* Copyright (c) 1998, 2001 Ben Harris
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_ARMREG_H
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#define _ARM_ARMREG_H
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/* CCSIDR - Current Cache Size ID Register */
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#define CCSIDR_SETS_MASK 0x0fffe000
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#define CCSIDR_SETS_SHIFT 13
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#define CCSIDR_SETS(reg) \
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((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1)
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#define CCSIDR_WAYS_MASK 0x00001ff8
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#define CCSIDR_WAYS_SHIFT 3
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#define CCSIDR_WAYS(reg) \
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((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1)
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#define CCSIDR_LINE_MASK 0x00000007
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#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4))
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/* CLIDR - Cache Level ID Register */
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#define CLIDR_CTYPE_MASK 0x7
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#define CLIDR_CTYPE_INSN 0x1
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#define CLIDR_CTYPE_DATA 0x2
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#define CLIDR_CTYPE_UNIFIED 0x4
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/* CSSELR - Cache Size Selection Register */
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#define CSSELR_IND (1 << 0)
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#define CSSELR_LEVEL_SHIFT 1
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/* CTR - Cache Type Register */
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#define CTR_DLINE_SHIFT 16
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#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
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#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
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#define CTR_IL1P_SHIFT 14
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#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT)
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#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT)
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#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT)
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#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT)
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#define CTR_ILINE_SHIFT 0
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#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
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#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
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/*
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* ARM Process Status Register
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*
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* The picture in early ARM manuals looks like this:
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* 3 3 2 2 2 2
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* 1 0 9 8 7 6 8 7 6 5 4 0
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+
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* |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
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* | | | | | | | | | |4 3 2 1 0|
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* +-+-+-+-+-+-------------------------------------+-+-+-+---------+
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*
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* The picture in the ARMv7-A manuals looks like this:
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* 3 3 2 2 2 2 2 2 2 2 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 0 9 6 5 0 9 8 7 6 5 4 0
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* +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+
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* |N|Z|C|V|Q|I I|J|reserv-|G G G G|I I I I I I|E|A|I|F|T|M M M M M|
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* | | | | | |T T| |ed |E E E E|T T T T T T| | | | | | |
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* | | | | | |1 0| | |3 2 1 0|7 6 5 4 3 2| | | | | |4 3 2 1 0|
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* +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+
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* | flags 'f' | status 's' | extension 'x' | control 'c' |
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*/
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#define PSR_FLAGS 0xf0000000 /* flags */
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#define PSR_N (1U << 31) /* negative */
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#define PSR_Z (1 << 30) /* zero */
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#define PSR_C (1 << 29) /* carry */
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#define PSR_V (1 << 28) /* overflow */
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#define PSR_Q (1 << 27) /* saturation */
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#define PSR_A (1 << 8) /* Asynchronous abort disable */
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#define PSR_I (1 << 7) /* IRQ disable */
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#define PSR_F (1 << 6) /* FIQ disable */
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#define PSR_T (1 << 5) /* Thumb state */
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#define PSR_J (1 << 24) /* Java mode */
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#define PSR_MODE 0x0000001f /* mode mask */
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#define PSR_USR26_MODE 0x00000000
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#define PSR_FIQ26_MODE 0x00000001
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#define PSR_IRQ26_MODE 0x00000002
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#define PSR_SVC26_MODE 0x00000003
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#define PSR_USR32_MODE 0x00000010
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#define PSR_FIQ32_MODE 0x00000011
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#define PSR_IRQ32_MODE 0x00000012
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#define PSR_SVC32_MODE 0x00000013
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#define PSR_MON32_MODE 0x00000016
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#define PSR_ABT32_MODE 0x00000017
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#define PSR_HYP32_MODE 0x0000001a
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#define PSR_UND32_MODE 0x0000001b
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#define PSR_SYS32_MODE 0x0000001f
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#define PSR_32_MODE 0x00000010
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#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
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/*
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* Co-processor 15: The system control co-processor.
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*/
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#define ARM_CP15_CPU_ID 0
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/*
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* The CPU ID register is theoretically structured, but the definitions of
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* the fields keep changing.
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*/
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/* The high-order byte is always the implementor */
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#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
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#define CPU_ID_ARCH_MASK 0x000f0000
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#define CPU_ID_ARCH_V6 0x00070000
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#define CPU_ID_ARCH_CPUID 0x000f0000
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#define CPU_ID_VARIANT_MASK 0x00f00000
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/* Next three nybbles are part number */
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#define CPU_ID_PARTNO_MASK 0x0000fff0
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/* And finally, the revision number. */
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#define CPU_ID_REVISION_MASK 0x0000000f
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/* Individual CPUs are probably best IDed by everything but the revision. */
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#define CPU_ID_CPU_MASK 0xfffffff0
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#define CPU_ID_CORTEX_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A5 0x410fc050
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#define CPU_ID_CORTEX_A5_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A7 0x410fc070
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#define CPU_ID_CORTEX_A7_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A8_R1 0x411fc080
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#define CPU_ID_CORTEX_A8_R2 0x412fc080
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#define CPU_ID_CORTEX_A8_R3 0x413fc080
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#define CPU_ID_CORTEX_A8 0x410fc080
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#define CPU_ID_CORTEX_A8_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A9 0x410fc090
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#define CPU_ID_CORTEX_A9_R1 0x411fc090
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#define CPU_ID_CORTEX_A9_R2 0x412fc090
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#define CPU_ID_CORTEX_A9_R3 0x413fc090
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#define CPU_ID_CORTEX_A9_R4 0x414fc090
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#define CPU_ID_CORTEX_A9_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A12 0x410fc0d0
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#define CPU_ID_CORTEX_A12_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A15 0x410fc0f0
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#define CPU_ID_CORTEX_A15_R1 0x411fc0f0
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#define CPU_ID_CORTEX_A15_R2 0x412fc0f0
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#define CPU_ID_CORTEX_A15_R3 0x413fc0f0
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#define CPU_ID_CORTEX_A15_R4 0x414fc0f0
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#define CPU_ID_CORTEX_A15_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A17 0x410fc0e0
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#define CPU_ID_CORTEX_A17_R1 0x411fc0e0
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#define CPU_ID_CORTEX_A17_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A32 0x410fd010
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#define CPU_ID_CORTEX_A32_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A35 0x410fd040
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#define CPU_ID_CORTEX_A35_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A53 0x410fd030
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#define CPU_ID_CORTEX_A53_R1 0x411fd030
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#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A55 0x410fd050
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#define CPU_ID_CORTEX_A55_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A57 0x410fd070
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#define CPU_ID_CORTEX_A57_R1 0x411fd070
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#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A72 0x410fd080
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#define CPU_ID_CORTEX_A72_R1 0x411fd080
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#define CPU_ID_CORTEX_A72_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A73 0x410fd090
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#define CPU_ID_CORTEX_A73_MASK 0xff0ffff0
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#define CPU_ID_CORTEX_A75 0x410fd0a0
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#define CPU_ID_CORTEX_A75_MASK 0xff0ffff0
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/* CPUID on >= v7 */
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#define ID_MMFR0_VMSA_MASK 0x0000000f
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#define VMSA_V7 3
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#define VMSA_V7_PXN 4
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#define VMSA_V7_LDT 5
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/*
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* Post-ARM3 CP15 registers:
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*
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* 1 Control register
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*
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* 2 Translation Table Base
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*
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* 3 Domain Access Control
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*
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* 4 Reserved
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*
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* 5 Fault Status
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*
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* 6 Fault Address
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*
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* 7 Cache/write-buffer Control
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*
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* 8 TLB Control
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*
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* 9 Cache Lockdown
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*
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* 10 TLB Lockdown
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*
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* 11 Reserved
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*
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* 12 Reserved
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*
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* 13 Process ID (for FCSE)
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*
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* 14 Reserved
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*
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* 15 Implementation Dependent
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*/
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/* Some of the definitions below need cleaning up for V3/V4 architectures */
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/* CPU control register (CP15 register 1) */
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#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
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#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
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#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
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#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
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#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
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#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
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#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
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#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
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#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
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#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
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#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
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#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
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#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
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#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
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#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
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#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
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/* below were added by V6 */
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#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */
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#define CPU_CONTROL_U (1<<22) /* U: Unaligned */
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#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */
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#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */
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#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */
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/* added with v7 */
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#define CPU_CONTROL_WXN (1<<19) /* WXN: Write implies XN */
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#define CPU_CONTROL_UWXN (1<<20) /* UWXN: Unpriv write implies XN */
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#define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */
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#define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */
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#define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */
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#define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
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#define CORTEXA9_AUXCTL_FW (1 << 0) /* Cache and TLB updates broadcast */
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#define CORTEXA9_AUXCTL_L2PE (1 << 1) /* Prefetch hint enable */
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#define CORTEXA9_AUXCTL_L1PE (1 << 2) /* Data prefetch hint enable */
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#define CORTEXA9_AUXCTL_WR_ZERO (1 << 3) /* Ena. write full line of 0s mode */
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#define CORTEXA9_AUXCTL_SMP (1 << 6) /* Coherency is active */
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#define CORTEXA9_AUXCTL_EXCL (1 << 7) /* Exclusive cache bit */
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#define CORTEXA9_AUXCTL_ONEWAY (1 << 8) /* Allocate in on cache way only */
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#define CORTEXA9_AUXCTL_PARITY (1 << 9) /* Support parity checking */
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/* Cache type register definitions */
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#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
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#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
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#define CPU_CT_S (1U << 24) /* split cache */
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#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
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/* Cache type register definitions for ARM v7 */
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#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */
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#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */
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#define CPU_CT_CTYPE_WT 0 /* write-through */
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#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
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#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
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#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
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#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
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#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
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#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
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#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
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#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
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/* MPIDR, Multiprocessor Affinity Register */
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#define MPIDR_AFF2 (0xffU << 16)
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#define MPIDR_AFF1 (0xffU << 8)
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#define MPIDR_AFF0 (0xffU << 0)
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#define MPIDR_AFF (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
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/* Fault status register definitions */
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#define FAULT_USER 0x20
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#define FAULT_WRTBUF_0 0x00 /* Vector Exception */
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#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
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#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
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#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
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#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
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#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
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#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
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#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
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#define FAULT_ALIGN_0 0x01 /* Alignment */
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#define FAULT_ALIGN_1 0x03 /* Alignment */
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#define FAULT_TRANS_S 0x05 /* Translation -- Section */
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#define FAULT_TRANS_P 0x07 /* Translation -- Page */
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#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
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#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
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#define FAULT_PERM_S 0x0d /* Permission -- Section */
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#define FAULT_PERM_P 0x0f /* Permission -- Page */
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/* Fault type definitions for ARM v7 */
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#define FAULT_ACCESS_1 0x03 /* Access flag fault -- Level 1 */
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#define FAULT_ACCESS_2 0x06 /* Access flag fault -- Level 2 */
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#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
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#define FAULT_EXT 0x00001000 /* external abort */
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#define FAULT_WNR 0x00000800 /* write fault */
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#define FAULT_TYPE(fsr) ((fsr) & 0x0f)
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#define FAULT_TYPE_V7(fsr) (((fsr) & 0x0f) | (((fsr) & 0x00000400) >> 6))
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/*
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* Address of the vector page, low and high versions.
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*/
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#define ARM_VECTORS_LOW 0x00000000U
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#define ARM_VECTORS_HIGH 0xffff0000U
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/*
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* ARM Instructions
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*
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* 3 3 2 2 2
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* 1 0 9 8 7 0
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* +-------+-------------------------------------------------------+
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* | cond | instruction dependant |
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* |c c c c| |
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* +-------+-------------------------------------------------------+
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*/
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#define INSN_SIZE 4 /* Always 4 bytes */
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define INSN_COND_AL 0xe0000000 /* Always condition */
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/* Translation Table Base Register */
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#define TTBR_C (1 << 0) /* without MPE */
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#define TTBR_S (1 << 1)
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#define TTBR_IMP (1 << 2)
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#define TTBR_RGN_MASK (3 << 3)
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#define TTBR_RGN_NC (0 << 3)
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#define TTBR_RGN_WBWA (1 << 3)
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#define TTBR_RGN_WT (2 << 3)
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#define TTBR_RGN_WBNWA (3 << 3)
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#define TTBR_NOS (1 << 5)
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#define TTBR_IRGN_MASK ((1 << 0) | (1 << 6))
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#define TTBR_IRGN_NC ((0 << 0) | (0 << 6))
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#define TTBR_IRGN_WBWA ((0 << 0) | (1 << 6))
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#define TTBR_IRGN_WT ((1 << 0) | (0 << 6))
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#define TTBR_IRGN_WBNWA ((1 << 0) | (1 << 6))
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#endif |