mirror of
https://codeberg.org/ziglang/zig.git
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Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
282 lines
8.1 KiB
C
Vendored
282 lines
8.1 KiB
C
Vendored
/* $OpenBSD: mips_cpu.h,v 1.11 2022/12/11 05:07:25 visa Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
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*/
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#ifndef _MIPS64_CPUREGS_H_
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#define _MIPS64_CPUREGS_H_
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#if defined(_KERNEL) || defined(_STANDALONE)
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/*
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* Status register.
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*/
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#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */
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#define SR_COP_0_BIT 0x10000000
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#define SR_COP_1_BIT 0x20000000
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#define SR_COP_2_BIT 0x40000000
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#define SR_RP 0x08000000
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#define SR_FR_32 0x04000000
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#define SR_RE 0x02000000
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#define SR_DSD 0x01000000 /* Only on R12000 */
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#define SR_BOOT_EXC_VEC 0x00400000
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#define SR_TLB_SHUTDOWN 0x00200000
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#define SR_SOFT_RESET 0x00100000
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#define SR_DIAG_CH 0x00040000
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#define SR_DIAG_CE 0x00020000
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#define SR_DIAG_DE 0x00010000
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#define SR_KX 0x00000080
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#define SR_SX 0x00000040
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#define SR_UX 0x00000020
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#define SR_ERL 0x00000004
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#define SR_EXL 0x00000002
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#define SR_INT_ENAB 0x00000001
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#define SOFT_INT_MASK_0 0x00000100
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#define SOFT_INT_MASK_1 0x00000200
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#define SR_INT_MASK_0 0x00000400
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#define SR_INT_MASK_1 0x00000800
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#define SR_INT_MASK_2 0x00001000
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#define SR_INT_MASK_3 0x00002000
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#define SR_INT_MASK_4 0x00004000
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#define SR_INT_MASK_5 0x00008000
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#define SR_XX 0x80000000
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#define SR_KSU_MASK 0x00000018
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#define SR_KSU_SUPER 0x00000008
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#define SR_KSU_KERNEL 0x00000000
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#define SR_INT_MASK 0x0000ff00
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/* SR_KSU_USER is in <mips64/cpu.h> for CLKF_USERMODE() */
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#ifndef SR_KSU_USER
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#define SR_KSU_USER 0x00000010
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#endif
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#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
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/*
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* Cause register.
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*/
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#define CR_BR_DELAY 0x80000000
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#define CR_BR_DELAY_SHIFT 31
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#define CR_EXC_CODE 0x0000007c
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#define CR_EXC_CODE_SHIFT 2
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#define CR_COP_ERR 0x30000000
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#define CR_COP1_ERR 0x10000000
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#define CR_COP2_ERR 0x20000000
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#define CR_COP3_ERR 0x20000000
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#define CR_INT_SOFT0 0x00000100
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#define CR_INT_SOFT1 0x00000200
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#define CR_INT_0 0x00000400
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#define CR_INT_1 0x00000800
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#define CR_INT_2 0x00001000
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#define CR_INT_3 0x00002000
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#define CR_INT_4 0x00004000
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#define CR_INT_5 0x00008000
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#define CR_INT_MASK 0x003fff00
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/*
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* Config register.
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*/
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#define CFGR_CCA_MASK 0x00000007
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#define CFGR_CU 0x00000008
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#define CFGR_ICE 0x0000000200000000
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#define CFGR_SMM 0x0000000400000000
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/*
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* Location of exception vectors.
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*/
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#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000)
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#define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000)
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#define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080)
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#define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100)
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#define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180)
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/*
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* Coprocessor 0 registers
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*/
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/* Common subset */
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#define COP_0_COUNT $9
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#define COP_0_TLB_HI $10
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#define COP_0_STATUS_REG $12
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#define COP_0_CAUSE_REG $13
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#define COP_0_EXC_PC $14
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#define COP_0_PRID $15
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#define COP_0_CONFIG $16
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/* MIPS64 release 2 */
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#define COP_0_USERLOCAL $4, 2
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#define COP_0_TLB_PG_GRAIN $5, 1
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#define COP_0_EBASE $15, 1
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/* R4000/5000/10000 */
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#define COP_0_TLB_INDEX $0
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#define COP_0_TLB_RANDOM $1
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#define COP_0_TLB_LO0 $2
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#define COP_0_TLB_LO1 $3
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#define COP_0_TLB_CONTEXT $4
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#define COP_0_TLB_PG_MASK $5
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#define COP_0_TLB_WIRED $6
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#define COP_0_BAD_VADDR $8
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#define COP_0_COMPARE $11
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#define COP_0_LLADDR $17
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#define COP_0_WATCH_LO $18
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#define COP_0_WATCH_HI $19
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#define COP_0_TLB_XCONTEXT $20
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#define COP_0_ECC $26
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#define COP_0_CACHE_ERR $27
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#define COP_0_TAG_LO $28
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#define COP_0_TAG_HI $29
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#define COP_0_ERROR_PC $30
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/* Loongson-2 specific */
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#define COP_0_DIAG $22
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/* Octeon specific */
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#define COP_0_CVMCTL $9, 7
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#define COP_0_CVMMEMCTL $11, 7
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/*
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* COP_0_COUNT speed divider.
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*/
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#if defined(CPU_OCTEON)
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#define CP0_CYCLE_DIVIDER 1
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#else
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#define CP0_CYCLE_DIVIDER 2
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#endif
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/*
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* The floating point version and status registers.
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*/
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#define FPC_ID $0
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#define FPC_CSR $31
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/*
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* Config1 register
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*/
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#define CONFIG1_M 0x80000000u
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#define CONFIG1_MMUSize1 0x7e000000u
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#define CONFIG1_MMUSize1_SHIFT 25
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#define CONFIG1_IS 0x01c00000u
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#define CONFIG1_IS_SHIFT 22
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#define CONFIG1_IL 0x00380000u
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#define CONFIG1_IL_SHIFT 19
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#define CONFIG1_IA 0x00070000u
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#define CONFIG1_IA_SHIFT 16
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#define CONFIG1_DS 0x0000e000u
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#define CONFIG1_DS_SHIFT 13
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#define CONFIG1_DL 0x00001c00u
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#define CONFIG1_DL_SHIFT 10
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#define CONFIG1_DA 0x00000380u
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#define CONFIG1_DA_SHIFT 7
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#define CONFIG1_C2 0x00000040u
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#define CONFIG1_MD 0x00000020u
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#define CONFIG1_PC 0x00000010u
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#define CONFIG1_WR 0x00000008u
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#define CONFIG1_CA 0x00000004u
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#define CONFIG1_EP 0x00000002u
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#define CONFIG1_FP 0x00000001u
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/*
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* Config3 register
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*/
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#define CONFIG3_M 0x80000000
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#define CONFIG3_BPG 0x40000000
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#define CONFIG3_CMGCR 0x20000000
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#define CONFIG3_IPLW 0x00600000
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#define CONFIG3_MMAR 0x001c0000
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#define CONFIG3_MCU 0x00020000
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#define CONFIG3_ISAOnExc 0x00010000
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#define CONFIG3_ISA 0x0000c000
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#define CONFIG3_ULRI 0x00002000
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#define CONFIG3_RXI 0x00001000
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#define CONFIG3_DSP2P 0x00000800
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#define CONFIG3_DSPP 0x00000400
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#define CONFIG3_CTXTC 0x00000200
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#define CONFIG3_ITL 0x00000100
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#define CONFIG3_LPA 0x00000080
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#define CONFIG3_VEIC 0x00000040
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#define CONFIG3_VInt 0x00000020
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#define CONFIG3_SP 0x00000010
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#define CONFIG3_CDMM 0x00000008
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#define CONFIG3_MT 0x00000004
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#define CONFIG3_SM 0x00000002
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#define CONFIG3_TL 0x00000001
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/*
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* Config4 register
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*/
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#define CONFIG4_M 0x80000000u
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#define CONFIG4_IE 0x60000000u
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#define CONFIG4_AE 0x10000000u
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#define CONFIG4_VTLBSizeExt 0x0f000000u /* when MMUExtDef=3 */
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#define CONFIG4_KScrExist 0x00ff0000u
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#define CONFIG4_MMUExtDef 0x0000c000u
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#define CONFIG4_MMUExtDef_SHIFT 14
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#define CONFIG4_FTLBPageSize 0x00001f00u /* when MMUExtDef=2 or 3 */
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#define CONFIG4_FTLBWays 0x000000f0u /* when MMUExtDef=2 or 3 */
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#define CONFIG4_FTLBSets 0x0000000fu /* when MMUExtDef=2 or 3 */
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#define CONFIG4_MMUSizeExt 0x000000ffu /* when MMUExtDef=1 */
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/*
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* PageGrain register
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*/
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#define PGRAIN_RIE 0x80000000
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#define PGRAIN_XIE 0x40000000
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#define PGRAIN_ELPA 0x20000000
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#define PGRAIN_ESP 0x10000000
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#define PGRAIN_IEC 0x08000000
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/*
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* HWREna register
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*/
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#define HWRENA_ULR 0x20000000u
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#define HWRENA_CC 0x00000004u
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#endif /* _KERNEL || _STANDALONE */
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#endif /* !_MIPS64_CPUREGS_H_ */ |