mirror of
https://codeberg.org/ziglang/zig.git
synced 2026-04-27 19:09:47 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
150 lines
5.0 KiB
C
Vendored
150 lines
5.0 KiB
C
Vendored
/* $OpenBSD: cpustate.h,v 1.11 2015/09/27 18:17:08 miod Exp $ */
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/*
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* Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#define KERN_REG_SIZE (NUMSAVEREGS * REGSZ)
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#define KERN_EXC_FRAME_SIZE (CF_SZ + KERN_REG_SIZE + 16)
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#define SAVE_REG(reg, offs, base, bo) \
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REG_S reg, bo + (REGSZ * offs) (base)
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#define RESTORE_REG(reg, offs, base, bo) \
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REG_L reg, bo + (REGSZ * offs) (base)
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/*
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* This macro saves the 'scratch' cpu state on stack.
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* Macros are generic so no 'special' instructions!
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* a0 will have a pointer to the 'frame' on return.
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* a1 will have saved STATUS_REG on return.
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* a3 will have the exception pc on 'return'.
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* No traps, no interrupts if frame = k1 or k0!
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* Temp regs are saved with their register number so
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* branch emulation etc works properly.
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*/
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#define SAVE_CPU(frame, bo) \
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SAVE_REG(AT, AST, frame, bo) ;\
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SAVE_REG(v0, V0, frame, bo) ;\
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SAVE_REG(v1, V1, frame, bo) ;\
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SAVE_REG(a0, A0, frame, bo) ;\
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SAVE_REG(a1, A1, frame, bo) ;\
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SAVE_REG(a2, A2, frame, bo) ;\
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SAVE_REG(a3, A3, frame, bo) ;\
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MFC0 a0, COP_0_CAUSE_REG ;\
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MFC0_HAZARD ;\
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SAVE_REG(a4, A4, frame, bo) ;\
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SAVE_REG(a5, A5, frame, bo) ;\
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MFC0 a1, COP_0_STATUS_REG ;\
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MFC0_HAZARD ;\
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SAVE_REG(a6, A6, frame, bo) ;\
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SAVE_REG(a7, A7, frame, bo) ;\
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PRE_MFC0_ADDR_HAZARD ;\
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DMFC0 a2, COP_0_BAD_VADDR ;\
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MFC0_HAZARD ;\
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SAVE_REG(t0, T0, frame, bo) ;\
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SAVE_REG(t1, T1, frame, bo) ;\
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DMFC0 a3, COP_0_EXC_PC ;\
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MFC0_HAZARD ;\
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SAVE_REG(t2, T2, frame, bo) ;\
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SAVE_REG(t3, T3, frame, bo) ;\
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SAVE_REG(t8, T8, frame, bo) ;\
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SAVE_REG(t9, T9, frame, bo) ;\
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SAVE_REG(gp, GP, frame, bo) ;\
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SAVE_REG(ra, RA, frame, bo) ;\
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mflo v0 ;\
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mfhi v1 ;\
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SAVE_REG(v0, MULLO, frame, bo) ;\
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SAVE_REG(v1, MULHI, frame, bo) ;\
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SAVE_REG(a0, CAUSE, frame, bo) ;\
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SAVE_REG(a1, SR, frame, bo) ;\
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SAVE_REG(a2, BADVADDR, frame, bo) ;\
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SAVE_REG(a3, PC, frame, bo) ;\
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SAVE_REG(sp, SP, frame, bo) ;\
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PTR_ADDU a0, frame, bo ;\
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GET_CPU_INFO(v0, v1) ;\
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lw a2, CI_IPL(v0) ;\
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SAVE_REG(a2, CPL, frame, bo)
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/*
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* Save 'callee save' registers in frame to aid DDB.
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*/
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#define SAVE_CPU_SREG(frame, bo) \
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SAVE_REG(s0, S0, frame, bo) ;\
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SAVE_REG(s1, S1, frame, bo) ;\
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SAVE_REG(s2, S2, frame, bo) ;\
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SAVE_REG(s3, S3, frame, bo) ;\
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SAVE_REG(s4, S4, frame, bo) ;\
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SAVE_REG(s5, S5, frame, bo) ;\
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SAVE_REG(s6, S6, frame, bo) ;\
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SAVE_REG(s7, S7, frame, bo) ;\
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SAVE_REG(s8, S8, frame, bo)
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/*
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* Restore cpu state. When called a0 = EXC_PC.
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*/
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#define RESTORE_CPU(frame, bo) \
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RESTORE_REG(t1, SR, frame, bo) ;\
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RESTORE_REG(t2, MULLO, frame, bo) ;\
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RESTORE_REG(t3, MULHI, frame, bo) ;\
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MTC0 t1, COP_0_STATUS_REG ;\
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MTC0_SR_IE_HAZARD ;\
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mtlo t2 ;\
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mthi t3 ;\
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DMTC0 a0, COP_0_EXC_PC ;\
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MTC0_HAZARD ;\
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RESTORE_REG(AT, AST, frame, bo) ;\
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RESTORE_REG(v0, V0, frame, bo) ;\
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RESTORE_REG(v1, V1, frame, bo) ;\
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RESTORE_REG(a0, A0, frame, bo) ;\
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RESTORE_REG(a1, A1, frame, bo) ;\
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RESTORE_REG(a2, A2, frame, bo) ;\
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RESTORE_REG(a3, A3, frame, bo) ;\
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RESTORE_REG(a4, A4, frame, bo) ;\
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RESTORE_REG(a5, A5, frame, bo) ;\
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RESTORE_REG(a6, A6, frame, bo) ;\
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RESTORE_REG(a7, A7, frame, bo) ;\
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RESTORE_REG(t0, T0, frame, bo) ;\
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RESTORE_REG(t1, T1, frame, bo) ;\
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RESTORE_REG(t2, T2, frame, bo) ;\
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RESTORE_REG(t3, T3, frame, bo) ;\
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RESTORE_REG(t8, T8, frame, bo) ;\
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RESTORE_REG(t9, T9, frame, bo) ;\
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RESTORE_REG(gp, GP, frame, bo) ;\
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RESTORE_REG(ra, RA, frame, bo)
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/*
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* Restore 'callee save' registers
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*/
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#define RESTORE_CPU_SREG(frame, bo) \
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RESTORE_REG(s0, S0, frame, bo) ;\
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RESTORE_REG(s1, S1, frame, bo) ;\
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RESTORE_REG(s2, S2, frame, bo) ;\
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RESTORE_REG(s3, S3, frame, bo) ;\
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RESTORE_REG(s4, S4, frame, bo) ;\
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RESTORE_REG(s5, S5, frame, bo) ;\
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RESTORE_REG(s6, S6, frame, bo) ;\
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RESTORE_REG(s7, S7, frame, bo) ;\
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RESTORE_REG(s8, S8, frame, bo) |