mirror of
https://codeberg.org/ziglang/zig.git
synced 2026-04-27 19:09:47 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
107 lines
3.2 KiB
C
Vendored
107 lines
3.2 KiB
C
Vendored
/* $OpenBSD: cache.h,v 1.9 2016/12/21 13:59:57 visa Exp $ */
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/*
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* Copyright (c) 2012 Miodrag Vallat.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _MIPS64_CACHE_H_
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#define _MIPS64_CACHE_H_
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/*
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* Declare canonical cache functions for a given processor.
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*
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* The following assumptions are made:
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* - only L1 has split instruction and data caches.
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* - L1 I$ is virtually indexed.
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*
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* Processor-specific routines will make extra assumptions.
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*/
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#define CACHE_PROTOS(chip) \
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/* Figure out cache configuration */ \
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void chip##_ConfigCache(struct cpu_info *); \
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/* Writeback and invalidate all caches */ \
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void chip##_SyncCache(struct cpu_info *); \
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/* Invalidate all I$ for the given range */ \
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void chip##_InvalidateICache(struct cpu_info *, vaddr_t, size_t); \
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/* Register a given page for I$ invalidation */ \
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void chip##_InvalidateICachePage(struct cpu_info *, vaddr_t); \
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/* Perform postponed I$ invalidation */ \
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void chip##_SyncICache(struct cpu_info *); \
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/* Writeback all D$ for the given page */ \
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void chip##_SyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
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/* Writeback all D$ for the (currently mapped) given page */ \
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void chip##_HitSyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
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/* Writeback all D$ for the given range */ \
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void chip##_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); \
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/* Invalidate all D$ for the given range */ \
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void chip##_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); \
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/* Enforce coherency of the given range */ \
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void chip##_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int);
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/*
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* Cavium Octeon.
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*/
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CACHE_PROTOS(Octeon)
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void Octeon_lock_secondary_cache(struct cpu_info *, paddr_t, size_t);
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void Octeon_unlock_secondary_cache(struct cpu_info *, paddr_t, size_t);
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/*
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* STC Loongson 2E and 2F.
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*/
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CACHE_PROTOS(Loongson2)
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/*
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* Loongson 3A and 2Gq.
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*/
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CACHE_PROTOS(Loongson3)
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/*
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* MIPS R4000 and R4400.
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*/
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CACHE_PROTOS(Mips4k)
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/*
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* IDT/QED/PMC-Sierra R4600, R4700, R5000, RM52xx, RM7xxx, RM9xxx.
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*/
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CACHE_PROTOS(Mips5k)
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/*
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* MIPS (SGI, really) R8000.
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*/
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CACHE_PROTOS(tfp)
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/*
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* MIPS/NEC R10000/R120000/R140000/R16000.
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*/
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CACHE_PROTOS(Mips10k)
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/*
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* mips64r2-compliant processors.
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*/
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CACHE_PROTOS(mips64r2)
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/*
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* Values used by the IOSyncDCache routine [which acts as the backend of
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* bus_dmamap_sync()].
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*/
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#define CACHE_SYNC_R 0 /* WB invalidate, WT invalidate */
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#define CACHE_SYNC_W 1 /* WB writeback, WT unaffected */
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#define CACHE_SYNC_X 2 /* WB writeback + invalidate, WT invalidate */
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extern vaddr_t cache_valias_mask;
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#endif /* _MIPS64_CACHE_H_ */ |