mirror of
https://codeberg.org/ziglang/zig.git
synced 2026-04-27 19:09:47 +03:00
Alex Rønne Petersen
66d97267c7
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
214 lines
4.2 KiB
C
Vendored
214 lines
4.2 KiB
C
Vendored
/* $OpenBSD: atomic.h,v 1.12 2019/10/28 09:41:37 visa Exp $ */
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/* Public Domain */
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#ifndef _MIPS64_ATOMIC_H_
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#define _MIPS64_ATOMIC_H_
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#if defined(_KERNEL)
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/* wait until the bits to set are clear, and set them */
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static __inline void
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atomic_wait_and_setbits_int(volatile unsigned int *uip, unsigned int v)
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{
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unsigned int tmp0, tmp1;
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__asm__ volatile (
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"1: ll %0, 0(%2)\n"
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" and %1, %0, %3\n"
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" bnez %1, 1b\n"
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" or %0, %3, %0\n"
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" sc %0, 0(%2)\n"
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" beqz %0, 1b\n"
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" nop\n" :
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"=&r"(tmp0), "=&r"(tmp1) :
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"r"(uip), "r"(v) : "memory");
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}
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static __inline void
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atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
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{
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unsigned int tmp;
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__asm__ volatile (
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"1: ll %0, 0(%1)\n"
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" or %0, %2, %0\n"
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" sc %0, 0(%1)\n"
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" beqz %0, 1b\n"
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" nop\n" :
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"=&r"(tmp) :
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"r"(uip), "r"(v) : "memory");
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}
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static __inline void
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atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
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{
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unsigned int tmp;
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__asm__ volatile (
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"1: ll %0, 0(%1)\n"
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" and %0, %2, %0\n"
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" sc %0, 0(%1)\n"
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" beqz %0, 1b\n"
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" nop\n" :
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"=&r"(tmp) :
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"r"(uip), "r"(~v) : "memory");
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}
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#endif /* defined(_KERNEL) */
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static inline unsigned int
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_atomic_cas_uint(volatile unsigned int *p, unsigned int o, unsigned int n)
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{
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unsigned int rv, wv;
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__asm__ volatile (
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"1: ll %0, %1\n"
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" bne %0, %4, 2f\n"
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" move %2, %3\n"
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" sc %2, %1\n"
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" beqz %2, 1b\n"
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"2: nop\n"
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: "=&r" (rv), "+m" (*p), "=&r" (wv)
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: "r" (n), "Ir" (o));
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return (rv);
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}
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#define atomic_cas_uint(_p, _o, _n) _atomic_cas_uint((_p), (_o), (_n))
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static inline unsigned long
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_atomic_cas_ulong(volatile unsigned long *p, unsigned long o, unsigned long n)
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{
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unsigned long rv, wv;
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__asm__ volatile (
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"1: lld %0, %1\n"
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" bne %0, %4, 2f\n"
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" move %2, %3\n"
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" scd %2, %1\n"
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" beqz %2, 1b\n"
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"2: nop\n"
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: "=&r" (rv), "+m" (*p), "=&r" (wv)
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: "r" (n), "Ir" (o));
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return (rv);
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}
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#define atomic_cas_ulong(_p, _o, _n) _atomic_cas_ulong((_p), (_o), (_n))
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static inline void *
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_atomic_cas_ptr(volatile void *pp, void *o, void *n)
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{
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void * volatile *p = pp;
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void *rv, *wv;
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__asm__ volatile (
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"1: lld %0, %1\n"
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" bne %0, %4, 2f\n"
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" move %2, %3\n"
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" scd %2, %1\n"
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" beqz %2, 1b\n"
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"2: nop\n"
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: "=&r" (rv), "+m" (*p), "=&r" (wv)
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: "r" (n), "Ir" (o));
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return (rv);
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}
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#define atomic_cas_ptr(_p, _o, _n) _atomic_cas_ptr((_p), (_o), (_n))
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static inline unsigned int
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_atomic_swap_uint(volatile unsigned int *uip, unsigned int v)
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{
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unsigned int o, t;
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__asm__ volatile (
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"1: ll %0, %1\n"
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" move %2, %3\n"
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" sc %2, %1\n"
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" beqz %2, 1b\n"
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" nop\n"
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: "=&r" (o), "+m" (*uip), "=&r" (t)
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: "r" (v));
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return (o);
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}
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#define atomic_swap_uint(_p, _v) _atomic_swap_uint((_p), (_v))
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static inline unsigned long
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_atomic_swap_ulong(volatile unsigned long *uip, unsigned long v)
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{
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unsigned long o, t;
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__asm__ volatile (
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"1: lld %0, %1\n"
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" move %2, %3\n"
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" scd %2, %1\n"
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" beqz %2, 1b\n"
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" nop\n"
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: "=&r" (o), "+m" (*uip), "=&r" (t)
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: "r" (v));
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return (o);
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}
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#define atomic_swap_ulong(_p, _v) _atomic_swap_ulong((_p), (_v))
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static inline void *
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_atomic_swap_ptr(volatile void *uipp, void *n)
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{
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void * volatile *uip = uipp;
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void *o, *t;
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__asm__ volatile (
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"1: lld %0, %1\n"
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" move %2, %3\n"
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" scd %2, %1\n"
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" beqz %2, 1b\n"
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" nop\n"
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: "=&r" (o), "+m" (*uip), "=&r" (t)
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: "r" (n));
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return (o);
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}
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#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n))
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static inline unsigned int
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_atomic_add_int_nv(volatile unsigned int *uip, unsigned int v)
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{
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unsigned int rv, nv;
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__asm__ volatile (
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"1: ll %0, %1\n"
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" addu %2, %0, %3\n"
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" sc %2, %1\n"
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" beqz %2, 1b\n"
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" nop\n"
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: "=&r" (rv), "+m" (*uip), "=&r" (nv)
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: "Ir" (v));
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return (rv + v);
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}
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#define atomic_add_int_nv(_uip, _v) _atomic_add_int_nv((_uip), (_v))
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#define atomic_sub_int_nv(_uip, _v) _atomic_add_int_nv((_uip), 0 - (_v))
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static inline unsigned long
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_atomic_add_long_nv(volatile unsigned long *uip, unsigned long v)
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{
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unsigned long rv, nv;
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__asm__ volatile (
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"1: lld %0, %1\n"
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" daddu %2, %0, %3\n"
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" scd %2, %1\n"
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" beqz %2, 1b\n"
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" nop\n"
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: "=&r" (rv), "+m" (*uip), "=&r" (nv)
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: "Ir" (v));
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return (rv + v);
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}
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#define atomic_add_long_nv(_uip, _v) _atomic_add_long_nv((_uip), (_v))
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#define atomic_sub_long_nv(_uip, _v) _atomic_add_long_nv((_uip), 0UL - (_v))
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#endif /* _MIPS64_ATOMIC_H_ */ |