Commit Graph

60 Commits

Author SHA1 Message Date
Alex Rønne Petersen 978555eea4 std.Target.x86: purge avx10.n-256, rename avx10.n_512 to avx10.n, require evex512 for avx512f
Intel has abandoned AVX10.N/128,256; AVX10.N is now always 512-bit.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen 587eddda28 std.Target: update CPU features to LLVM 21 2025-08-30 06:36:41 +02:00
Andrew Kelley 749f10af49 std.ArrayList: make unmanaged the default 2025-08-11 15:52:49 -07:00
KNnut fcb088cb6a std.Target.Query: fix WindowsVersion format in zigTriple() 2025-08-05 06:08:42 +02:00
Andrew Kelley 0e37ff0d59 std.fmt: breaking API changes
added adapter to AnyWriter and GenericWriter to help bridge the gap
between old and new API

make std.testing.expectFmt work at compile-time

std.fmt no longer has a dependency on std.unicode. Formatted printing
was never properly unicode-aware. Now it no longer pretends to be.

Breakage/deprecations:
* std.fs.File.reader -> std.fs.File.deprecatedReader
* std.fs.File.writer -> std.fs.File.deprecatedWriter
* std.io.GenericReader -> std.io.Reader
* std.io.GenericWriter -> std.io.Writer
* std.io.AnyReader -> std.io.Reader
* std.io.AnyWriter -> std.io.Writer
* std.fmt.format -> std.fmt.deprecatedFormat
* std.fmt.fmtSliceEscapeLower -> std.ascii.hexEscape
* std.fmt.fmtSliceEscapeUpper -> std.ascii.hexEscape
* std.fmt.fmtSliceHexLower -> {x}
* std.fmt.fmtSliceHexUpper -> {X}
* std.fmt.fmtIntSizeDec -> {B}
* std.fmt.fmtIntSizeBin -> {Bi}
* std.fmt.fmtDuration -> {D}
* std.fmt.fmtDurationSigned -> {D}
* {} -> {f} when there is a format method
* format method signature
  - anytype -> *std.io.Writer
  - inferred error set -> error{WriteFailed}
  - options -> (deleted)
* std.fmt.Formatted
  - now takes context type explicitly
  - no fmt string
2025-07-07 22:43:51 -07:00
Ali Cheraghi 1df79ab895 remove spirv cpu arch 2025-06-23 06:03:03 +02:00
Jacob Young 917640810e Target: pass and use locals by pointer instead of by value
This struct is larger than 256 bytes and code that copies it
consistently shows up in profiles of the compiler.
2025-06-19 11:45:06 -04:00
Alex Rønne Petersen 9d534790eb std.Target: Introduce Cpu convenience functions for feature tests.
Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
Ali Cheraghi 4bf1e4d198 target: auto-generated spirv features 2025-05-21 15:26:18 +03:30
Ali Cheraghi 0901328f12 spirv: write error value in an storage buffer 2025-05-21 12:57:40 +03:30
Alex Rønne Petersen 4de368a1b6 std.Target: Update CPU models/features for LLVM 20.
Closes #21818.
2025-04-04 06:08:09 +02:00
Ali Cheraghi ee06b2ce76 spirv: require int8/int16 capabilities 2025-03-18 07:05:50 +03:30
Ali Cheraghi 50539a2447 spirv/target: arbitrary_precision_integers feature support 2025-03-17 21:56:17 +03:30
Ali Cheraghi 78ad866dd1 target: split addresses and physical_storage_buffer features 2025-03-17 21:56:17 +03:30
Alex Rønne Petersen 9840157c18 std.Target.Query: Don't append glibc version in zigTriple() if ABI isn't GNU. 2025-03-09 19:50:13 +01:00
Ali Cheraghi a0eec9ce9e spirv: replace some unreachables with compile errors 2025-02-24 19:12:33 +01:00
Ali Cheraghi d5e1cb3ea2 spirv: ziggify and remove unknown spirv features
`OpCapability` and `OpExtension` now can also be emitted from inline assembly
2025-02-18 18:08:47 +03:30
Ali Cheraghi 1b0c7f51ef target: update spirv features 2025-02-18 18:07:48 +03:30
Alex Rønne Petersen 481b7bf3f0 std.Target: Remove functions that just wrap component functions.
Functions like isMinGW() and isGnuLibC() have a good reason to exist: They look
at multiple components of the target. But functions like isWasm(), isDarwin(),
isGnu(), etc only exist to save 4-8 characters. I don't think this is a good
enough reason to keep them, especially given that:

* It's not immediately obvious to a reader whether target.isDarwin() means the
  same thing as target.os.tag.isDarwin() precisely because isMinGW() and similar
  functions *do* look at multiple components.
* It's not clear where we would draw the line. The logical conclusion before
  this commit would be to also wrap Arch.isX86(), Os.Tag.isSolarish(),
  Abi.isOpenHarmony(), etc... this obviously quickly gets out of hand.
* It's nice to just have a single correct way of doing something.
2025-02-17 19:18:19 +01:00
Alex Rønne Petersen 2fe32ef847 std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead. 2025-02-17 19:17:55 +01:00
Alex Rønne Petersen ea1502974d wasm: Add a nontrapping_bulk_memory_len0 feature.
This will mainly be used when targeting our wasm2c implementation which has no
problem with zero-length bulk memory operations, as a non-standard extension.
2025-01-22 20:56:28 +01:00
Alex Rønne Petersen 280ced66eb std.Target: Define and use lime1 as the baseline CPU model for WebAssembly.
See: https://github.com/WebAssembly/tool-conventions/pull/235

This is not *quite* using the same features as the spec'd lime1 model because
LLVM 19 doesn't have the level of feature granularity that we need for that.
This will be fixed once we upgrade to LLVM 20.

Part of #21818.
2025-01-22 03:01:05 +01:00
Jacob Young ac1a975f9b x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
mlugg da1ffae7d2 std: fix undefined value in Target.Query
This is an RLS footgun.

Resolves: #21834
2025-01-05 16:26:21 +00:00
Alex Rønne Petersen 8594f179f9 Merge pull request #22067 from alexrp/pie-tests
Add PIC/PIE tests and fix some bugs + some improvements to the test harness
2024-11-28 14:07:28 +01:00
David Rubin f36f7d54a7 refactor update_cpu_features.zig
Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
2024-11-25 01:11:15 -08:00
David Rubin 9e17e097e5 make crc32 a featdep of sse4.2
To my knowledge there isn't an implementation of `sse4.2` that doesn't have `crc32`.
The Clang driver also sets `crc32` to be implicitly enabled when an explicit `-crc32`
wasn't provided. This matches that behaviour.

We need this behaviour to compile libraries like `rocksdb` which currently guard against
`crc32` intrinsics by checking for `sse4.2`.
2024-11-25 01:11:15 -08:00
Alex Rønne Petersen 24ecf45569 std.Target: Add Os.HurdVersionRange for Os.Tag.hurd.
This is necessary since isGnuLibC() is true for hurd, so we need to be able to
represent a glibc version for it.

Also add an Os.TaggedVersionRange.gnuLibCVersion() convenience function.
2024-11-24 22:11:16 +01:00
Daniel Hooper ed04acf90d Provide a detailed message for invalid arch in target triple (#21921) 2024-11-06 03:38:01 +00:00
Alex Rønne Petersen baf60426d4 std.Target: Rename amdgpu module to amdgcn.
This was an inconsistency left over from c825b567b2.
2024-11-02 10:44:14 +01:00
Alex Rønne Petersen fccf15fc9f std.Target: Remove armv7k/armv7s.
Like d1d95294fd, this is more Apple nonsense where
they abused the arch component of the triple to encode what's really an ABI.

Handling this correctly in Zig's target triple model would take quite a bit of
work. Fortunately, the last Armv7-based Apple Watch was released in 2017 and
these targets are now considered legacy. By the time Zig hits 1.0, they will be
a distant memory. So just remove them.
2024-11-02 10:25:40 +01:00
Alex Rønne Petersen 3c1ccbdf39 std.Target: Add support for specifying Android API level. 2024-11-01 06:23:59 +01:00
Alex Rønne Petersen 549a7eba40 std.Target: Rename OS version range functions to drop the "get" prefix. 2024-10-16 22:25:29 +02:00
Alex Rønne Petersen 1bca53cc20 std.Target: Change Cpu.baseline() to also be able to take OS into consideration. 2024-10-16 00:33:10 +02:00
DravenK ba1331090c std.Target.Query: fix compilation error (#21669)
closes #21668

Co-authored-by: Alex Rønne Petersen <alex@alexrp.com>
2024-10-12 23:15:11 +00:00
Felix Queißner 7c74edec8d Adds new cpu architectures propeller1 and propeller2. (#21563)
* Adds new cpu architectures propeller1 and propeller2.

These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves #21559

* Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2
* Fixes missing switch prongs in src/codegen/llvm.zig
* Fixes order in std.Target.Arch

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>
2024-10-04 13:53:28 -07:00
Alex Rønne Petersen eb363bf845 Merge pull request #21572 from alexrp/tests-llvm-targets
`test`: Rewrite the target triple list for `llvm_targets`.
2024-10-04 19:37:12 +02:00
Alex Rønne Petersen cb1ac0bb2f update_cpu_features: Don't delete the output file if there are no CPU features.
At bare minimum, the compiler expects std.Target.<arch>.cpu.generic to work for
any given architecture when generating the builtin module. So rather than try to
hack that into working when the affected modules are omitted, just actually keep
them.

This affected lanai and xcore.
2024-10-03 05:01:14 +02:00
Alex Rønne Petersen 8ee52f99ce Merge pull request #21505 from alexrp/cpu-features-exts
`update_cpu_features`: Add support for parsing `DefaultExts` as used for aarch64.
2024-10-03 00:41:48 +02:00
Alex Rønne Petersen 5458c9c71b std.Target: Regenerate CPU models/features based on LLVM 19.1.0.
* DefaultExts parsing for aarch64.
* cortex-m85 trustzone correction for arm.
2024-09-24 11:45:01 +02:00
Alex Rønne Petersen ebbc50d8be std.Target: Introduce Abi.androideabi to distinguish the soft float case.
Abi.android on its own is not enough to know whether soft float or hard float
should be used. In the C world, androideabi is typically used for the soft float
case, so let's go with that.

Note that Android doesn't have a hard float ABI, so no androideabihf.

Closes #21488.
2024-09-24 09:23:24 +02:00
Alex Rønne Petersen 916eaad1ef std.Target: Update CPU models/features for LLVM 19.1.0. 2024-09-19 18:20:22 -07:00
Alex Rønne Petersen da8b7fb0c0 std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
mlugg 0fe3fd01dd std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
Alex Rønne Petersen cad69e2c29 std.Target.Query: Fix parse test on ABIs like gnueabi, gnuabi64, etc.
The `zigTriple()` implementation simply returns `gnu` when a glibc version is provided but a more specific ABI isn't.
2024-08-23 22:39:05 -07:00
Linus Groh fd434fcd38 std.Target: Rename feature_set_fns to FeatureSetFns
From https://ziglang.org/documentation/master/#Names:

> If `x` is callable, and `x`'s return type is `type`, then `x` should
> be `TitleCase`.
2024-08-12 00:34:59 +01:00
Ryan Liptak e912411fbe Run update_cpu_features against LLVM 18.1.8
- RISCV unaligned-scalar-mem was added in LLVM 18.1.6
- Fixes arm v9_5a confusion
2024-08-07 09:03:05 -07:00
Jora Troosh 13070448f5 std: fix typos (#20560) 2024-07-09 14:25:42 -07:00
Andrew Kelley d34fae26d5 LLVM 18 std lib updates and fixes
* some manual fixes to generated CPU features code. In the future it
  would be nice to make the script do those automatically.

* add to various target OS switches. Some of the values I was unsure of
  and added TODO panics, for example in the case of spirv CPU arch.
2024-05-08 19:37:28 -07:00
Andrew Kelley 109ec72924 update CPU features to LLVM 18
release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
2024-05-08 19:37:28 -07:00