Commit Graph

242 Commits

Author SHA1 Message Date
Jacob Young ac64c75876 Dwarf: implement pointers to more comptime values
Closes #30600
Closes #30602
2026-01-05 11:24:48 +01:00
Pavel Verigo bf58a3bc08 stage2_wasm: revival, enabling tests 2025-12-07 07:21:15 +01:00
Ali Cheraghi dec1163fbb all: replace all @Type usages
Co-authored-by: Matthew Lugg <mlugg@mlugg.co.uk>
2025-11-22 22:42:38 +00:00
Andrew Kelley 1c9ac9dbb7 add behavior test: avoid unused field function body compile error 2025-09-20 18:51:43 -07:00
Andrew Kelley 2ba03e98c8 disable failing stage2_aarch64 behavior tests 2025-09-20 18:33:01 -07:00
Jacob Young 2fdf0e29b3 aarch64: enable fixed behavior 2025-09-20 18:33:00 -07:00
Andrew Kelley 640c11171b LLVM backend:fix align 1 sret parameter load returned
closes #25067
2025-08-29 03:37:18 -07:00
Andrew Kelley 749f10af49 std.ArrayList: make unmanaged the default 2025-08-11 15:52:49 -07:00
Ali Cheraghi 64563e2fff test: skip tests that were not meant to pass for spirv 2025-08-09 13:27:45 +03:30
Jacob Young c334956a54 aarch64: workaround some optional/union issues 2025-07-28 09:03:17 -07:00
Jacob Young 7894703ee7 aarch64: implement more optional/error union/union support 2025-07-26 21:39:50 -04:00
Jacob Young 5060ab99c9 aarch64: add new from scratch self-hosted backend 2025-07-22 19:43:47 -07:00
Andrew Kelley 34f64432b0 remove usingnamespace from the language
closes #20663
2025-07-07 13:39:48 -07:00
Bingwu Zhang e8d6ecb9ce riscv64: skip failing tests 2025-06-28 06:47:09 +08:00
Jacob Young 1f98c98fff x86_64: increase passing test coverage on windows
Now that codegen has no references to linker state this is much easier.

Closes #24153
2025-06-19 18:41:12 -04:00
Ali Cheraghi 872f68c9cb rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Jacob Young 80170d017b Legalize: handle packed semantics
Closes #22915
2025-06-03 15:04:43 -04:00
Jacob Young 1f6f8b0ffe x86_64: implement integer @reduce(.Add) 2025-05-28 15:10:22 -04:00
Ali Cheraghi 9bd8f8ed56 test: skip "struct fields get automatically reordered" for spirv64 backend 2025-04-28 10:49:19 +03:30
Andrew Kelley 65bd8d52c8 Merge pull request #23061 from pavelverigo/stage2-wasm-misc
stage2-wasm: multiple fixes
2025-04-11 15:56:35 -04:00
Jacob Young 9827ffe1de x86_64: fix incorrect handling of unreusable operands
Closes #23448
2025-04-05 20:49:56 -04:00
Pavel Verigo 33ad2c949e stage2-wasm: packed store/load 128 bits 2025-03-24 15:00:00 +01:00
Ali Cheraghi 54c097f50d spirv: packed struct init + field val access 2025-03-18 07:05:48 +03:30
Ali Cheraghi aec0f9b3e7 test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Jacob Young e5d5a8bc4e x86_64: implement switch jump tables 2025-01-16 20:42:08 -05:00
mlugg d00e05f186 all: update to std.builtin.Type.Pointer.Size field renames
This was done by regex substitution with `sed`. I then manually went
over the entire diff and fixed any incorrect changes.

This diff also changes a lot of `callconv(.C)` to `callconv(.c)`, since
my regex happened to also trigger here. I opted to leave these changes
in, since they *are* a correct migration, even if they're not the one I
was trying to do!
2025-01-16 12:46:29 +00:00
mlugg e9bd2d45d4 Sema: rewrite semantic analysis of function calls
This rewrite improves some error messages, hugely simplifies the logic,
and fixes several bugs. One of these bugs is technically a new rule
which Andrew and I agreed on: if a parameter has a comptime-only type
but is not declared `comptime`, then the corresponding call argument
should not be *evaluated* at comptime; only resolved. Implementing this
required changing how function types work a little, which in turn
required allowing a new kind of function coercion for some generic use
cases: function coercions are now allowed to implicitly *remove*
`comptime` annotations from parameters with comptime-only types. This is
okay because removing the annotation affects only the call site.

Resolves: #22262
2025-01-09 06:46:47 +00:00
Alex Rønne Petersen c9e67e71c1 std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().
The old isARM() function was a portability trap. With the name it had, it seemed
like the obviously correct function to use, but it didn't include Thumb. In the
vast majority of cases where someone wants to ask "is the target Arm?", Thumb
*should* be included.

There are exactly 3 cases in the codebase where we do actually need to exclude
Thumb, although one of those is in Aro and mirrors a check in Clang that is
itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-11-03 09:29:30 +01:00
mlugg d11bbde5f9 compiler: remove anonymous struct types, unify all tuples
This commit reworks how anonymous struct literals and tuples work.

Previously, an untyped anonymous struct literal
(e.g. `const x = .{ .a = 123 }`) was given an "anonymous struct type",
which is a special kind of struct which coerces using structural
equivalence. This mechanism was a holdover from before we used
RLS / result types as the primary mechanism of type inference. This
commit changes the language so that the type assigned here is a "normal"
struct type. It uses a form of equivalence based on the AST node and the
type's structure, much like a reified (`@Type`) type.

Additionally, tuples have been simplified. The distinction between
"simple" and "complex" tuple types is eliminated. All tuples, even those
explicitly declared using `struct { ... }` syntax, use structural
equivalence, and do not undergo staged type resolution. Tuples are very
restricted: they cannot have non-`auto` layouts, cannot have aligned
fields, and cannot have default values with the exception of `comptime`
fields. Tuples currently do not have optimized layout, but this can be
changed in the future.

This change simplifies the language, and fixes some problematic
coercions through pointers which led to unintuitive behavior.

Resolves: #16865
2024-10-31 20:42:53 +00:00
mlugg 097766bba3 compiler: implement @FieldType
Resolves: #21702
2024-10-18 08:50:40 +01:00
David Rubin bc161430b0 riscv: implement optional_payload_ptr_set 2024-09-12 20:29:10 -04:00
David Rubin fbac7afa0f riscv: implement errunion_payload_ptr_set 2024-09-01 17:34:06 +01:00
mlugg c3fb30803f behavior: avoid field/decl name conflicts 2024-08-29 23:43:52 +01:00
mlugg 0fe3fd01dd std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
David Rubin 8da212c11b riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin a1f6a8ef90 riscv: airAsm rewrite
with this rewrite we can call functions inside of
inline assembly, enabling us to use the default start.zig logic

all that's left is to implement lr/sc loops for atomically manipulating
1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26 04:19:55 -07:00
David Rubin b533e848a2 riscv: enable passing tests 2024-07-26 04:19:17 -07:00
David Rubin 9bc7e8c852 riscv: update tests 2024-07-26 04:05:43 -07:00
David Rubin 1820f44104 riscv: implement sub-byte addition 2024-07-26 04:05:42 -07:00
David Rubin cde6956b21 riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin 8d30fc45c4 riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin 7a02878f4e riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin 4fd8900337 riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin a270c6f8c8 riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin 083b7b483e riscv: zero registers when using register-wide operations
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13 02:22:04 -07:00
David Rubin b67995689d riscv: add airAggregateInit for arrays 2024-06-13 02:22:04 -07:00
David Rubin 05de6c279b riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin c457f35da5 riscv: arbitrary sized arrays 2024-06-13 02:19:40 -07:00
David Rubin ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin 2fd83d8c0a riscv: by-value structs + @min 2024-05-11 02:17:24 -07:00