Commit Graph

7872 Commits

Author SHA1 Message Date
Jakub Konka 4d0c48738b x64: make lowerUnnamedConst a fallthrough condition 2022-02-28 11:40:25 +01:00
Jakub Konka 06f58a0b3b codegen: impl lowering of union type to memory 2022-02-28 11:40:25 +01:00
Jakub Konka 1dc05e9e77 x64: impl airSetUnionTag 2022-02-28 11:40:21 +01:00
Andrew Kelley 4d658f83ed Sema: handle error.GenericPoison in fieldVal
Brings us 1 crash closer to formatted printing test cases.
2022-02-26 21:47:22 -07:00
Andrew Kelley 2687b8f7f4 stage2: implement @unionInit
The ZIR instruction `union_init_ptr` is renamed to `union_init`.
I made it always use by-value semantics for now, not taking the time to
invest in result location semantics, in case we decide to change the
rules for unions. This way is much simpler.

There is a new AIR instruction: union_init. This is for a comptime known
tag, runtime-known field value.
vector_init is renamed to aggregate_init, which solves a TODO comment.
2022-02-26 20:59:36 -07:00
Andrew Kelley 32e89a98d8 Sema: implement union value equality at comptime
Still TODO is extern unions.
2022-02-26 20:59:23 -07:00
Mitchell Hashimoto e999a925fa stage2: @TypeInfo for error sets (#10998) 2022-02-26 22:59:06 -05:00
Andrew Kelley aefe4046de Sema: implement @enumToInt for unions 2022-02-26 16:53:23 -07:00
Andrew Kelley d62229e3ad Sema: Module.Union.abiAlignment can return 0
When the union is a 0-bit type.
2022-02-26 16:53:23 -07:00
Andrew Kelley 822d29286b Sema: make align(a) T same as align(a:0:N) T
where `@sizeOf(T) == N`.
2022-02-26 16:50:35 -07:00
Andrew Kelley e81b21a0ea Merge pull request #10992 from mitchellh/peer-slices
stage2: peer resolve *[N]T to []T and E![]T and [*]T, handle in-memory coercion
2022-02-26 18:49:44 -05:00
Veikka Tuominen bf3c88b68d stage2: various fixes to get one test passing
* resolve error sets before merging them
* implement tupleFieldPtr
* make ret_ptr behave like alloc with zero sized types in llvm backend
2022-02-26 18:44:23 -05:00
Joachim Schmidt 058e482247 Merge pull request #10996 from joachimschmidt557/stage2-arm
stage2 ARM: implement truncate to integers with <= 32 bits
2022-02-26 22:50:31 +01:00
Veikka Tuominen bf5c055562 stage2: unify runtime and comptime coerce_result_ptr 2022-02-26 12:52:07 -07:00
Veikka Tuominen bff7714a7c stage2: fix toAllocatedBytes on slices 2022-02-26 12:52:06 -07:00
Veikka Tuominen ee149aaa03 stage2: actually coerce in coerce_result_ptr at comptime 2022-02-26 12:51:23 -07:00
Mitchell Hashimoto a5c9e8a494 typo in comment 2022-02-26 09:33:03 -08:00
Veikka Tuominen 315d4e8442 stage2: do not require function when evaluating typeOf
We only care about the instructions type; it will never actually be codegen'd.
2022-02-26 18:08:31 +02:00
Veikka Tuominen ff72b8a819 stage2: evaluate TypeOf arguments in a separate scope 2022-02-26 18:08:11 +02:00
joachimschmidt557 f48f4baf67 stage2 ARM: generate correct variants of ldr instruction
When loading an i16 for example, generate ldrsh instead of ldrh
2022-02-26 13:00:01 +01:00
joachimschmidt557 8ef80cfaab stage2 ARM: implement truncate to ints with bits <= 32 2022-02-26 12:59:57 +01:00
Mitchell Hashimoto 91af552f87 stage2: resolve peer types that trivially coerce 2022-02-25 18:47:10 -08:00
Mitchell Hashimoto 943ee59bb1 stage2: *[N]T to [*]T (and vice versa) 2022-02-25 17:29:50 -08:00
Mitchell Hashimoto 4a6f918029 stage2: remove extranneous debug 2022-02-25 13:37:07 -08:00
Mitchell Hashimoto 1019181982 stage2: *[N]T and E![]T 2022-02-25 13:33:11 -08:00
Mitchell Hashimoto 117ef22d3c stage2: peer resolve *[N]T to []T (and vice versa) 2022-02-25 13:21:07 -08:00
Jakub Konka e0f5627d4a x64+aarch64: check for pointer to zero-bit type when lowering decl
Unless the pointer is a pointer to a function, if the pointee type
has zero-bits, we need to return `MCValue.none` as the `Decl` has
not been lowered to memory, and therefore, any GOT reference will be
wrong.
2022-02-25 21:59:19 +01:00
Jakub Konka 4b14384989 aarch64: check if type has runtime bits before allocating mem ptr 2022-02-25 21:59:19 +01:00
Jakub Konka 1b8ed7842c macho: redo selection of segment/section for decls and consts
* fix alignment issues for consts with natural ABI alignment not
  matching that of the `ldr` instruction in `aarch64` - solved by
  preceeding the `ldr` with an additional `add` instruction to form
  the full address before dereferencing the pointer.
* redo selection of segment/section for decls and consts based on
  combined type and value
2022-02-25 21:59:19 +01:00
Veikka Tuominen bf6540ce50 Revert "stage2: make array len field type usize to match stage1"
This reverts commit 73bf418eb1.
2022-02-25 11:33:53 +02:00
Veikka Tuominen 73bf418eb1 stage2: make array len field type usize to match stage1
match stage1 behavior to avoid issues in standard library.
2022-02-25 11:25:56 +02:00
Luuk de Gram 0147eb9b58 wasm: Fix error union's size/alignment
Previously error unions were packed in memory. Now each 'field' is correctly
aligned to the error union's alignment.
2022-02-25 09:33:15 +01:00
Luuk de Gram f4adb53bcf wasm: Refactor lowerUnnamedConst
Rather than ping ponging between codegen and the linker to generate the symbols/atoms
for a local constant and its relocations. We now create all neccesary objects within the linker.

This simplifies the code as we can now simply call `lowerUnnamedConst` from anywhere in codegen,
allowing us to further improve lowering constants into .rodata so we do not have to sacrifice
lowering certain types such as decl_ref's where its type is a slice.
2022-02-25 09:33:15 +01:00
Andrew Kelley 27eb42c15e Sema: implement tupleFieldVal, fix comptime elem_ptr 2022-02-24 22:28:37 -07:00
Andrew Kelley adb746a701 stage2: improved handling of store_to_block_ptr
* AstGen: remove the setBlockBodyEliding function. This is no longer
   needed after 63788b2a51.
 * Sema: store_to_block_ptr instruction is handled as
   store_to_inferred_ptr or store, as necessary.
2022-02-24 22:28:37 -07:00
Veikka Tuominen 63788b2a51 stage2: change how stale store_to_block_ptrs are detected
Instead of explicitly setting lhs to .none,
check if the lhs instruction was analyzed.
This simpler approach also handles stores from nested blocks correctly.
2022-02-24 18:32:08 -05:00
Andrew Kelley e06cb31659 Merge pull request #10982 from Vexu/stage2
stage2: implement fieldParentPtr
2022-02-24 15:52:56 -05:00
Andrew Kelley 5ab5e2e673 Revert "Merge pull request #10950 from hexops/sg/responsefiles"
This reverts commit 136a43934b, reversing
changes made to 9dd839b7ed.

This broke the behavior of `zig run`.
2022-02-24 12:11:11 -07:00
Veikka Tuominen cbd5d6c704 spirv spec: do not align packed struct fields 2022-02-24 19:48:34 +02:00
Veikka Tuominen b034c45b2b stage2: implement fieldParentPtr 2022-02-24 19:48:34 +02:00
Andrew Kelley 6249a24e81 stage2: integer-backed packed structs
This implements #10113 for the self-hosted compiler only. It removes the
ability to override alignment of packed struct fields, and removes the
ability to put pointers and arrays inside packed structs.

After this commit, nearly all the behavior tests pass for the stage2 llvm
backend that involve packed structs.

I didn't implement the compile errors or compile error tests yet. I'm
waiting until we have stage2 building itself and then I want to rework
the compile error test harness with inspiration from Vexu's arocc test
harness. At that point it should be a much nicer dev experience to work
on compile errors.
2022-02-23 23:59:25 -07:00
Mitchell Hashimoto 65c0475970 stage2: peer type resolution *[N]T and *[M]T to []const T 2022-02-24 08:50:26 +02:00
Jakub Konka ffb7ac6755 elf: use fully qualified decl names in the linker 2022-02-24 00:01:11 +01:00
Jakub Konka 9d098318e2 Merge pull request #10977 from joachimschmidt557/stage2-aarch64
stage2 AArch64: more support for PIE targets (Mach-O)
2022-02-24 00:00:15 +01:00
Jakub Konka 136a43934b Merge pull request #10950 from hexops/sg/responsefiles
Do not fail to build if 'zig build-lib' etc. arguments exceed OS limits
2022-02-23 22:54:25 +01:00
Jakub Konka 9dd839b7ed Merge pull request #10976 from ziglang/x64-macos-fixes
x64: print test runner results on macos
2022-02-23 22:40:06 +01:00
Jan Philipp Hafer 5d89955543 compiler_rt: specify goals, organize README and compiler_rt.zig
* goals
  - zig as linker for object files generated by other compilers
  - zig-specific runtime features for eventual standardisation

* changes
  - missing routines are marked with `missing`
  - structure inspired by libgcc docs, but improved order and wording
  - rename misspelled functions
  - reorder and rephrase compiler_rt.zig to reflect documentation
  - potential decimal float or fixed-point arithmetic support:
    * 'Decimal float library routines' ca. 120 functions
    * 'Fixed-point fractional library routines' ca. 300 functions

thanks to @Vexu for multiple reviews and @scheibo for review
2022-02-23 16:38:51 -05:00
Andrew Kelley ecf56d85ef Merge pull request #10969 from Vexu/stage2
stage2: fn typeinfo params
2022-02-23 16:10:17 -05:00
joachimschmidt557 f91fe9afb9 stage2 AArch64: more support for MCValue.got_load and direct_load 2022-02-23 21:58:13 +01:00
joachimschmidt557 4683f94463 stage2 AArch64: remove MIR load_memory instruction
This instruction now just represents loading from a hard-coded adrress
after extracting the other use cases for load_memory into load_got and
load_direct.
2022-02-23 21:57:59 +01:00