Commit Graph

219 Commits

Author SHA1 Message Date
Veikka Tuominen e63ff4f1c1 add ast-check flag to zig fmt, fix found bugs 2021-06-14 00:16:40 +03:00
Andrew Kelley 138afd5cbf zig fmt 2021-06-10 20:13:43 -07:00
Martin Wickham fc9430f567 Breaking hash map changes for 0.8.0
- hash/eql functions moved into a Context object
- *Context functions pass an explicit context
- *Adapted functions pass specialized keys and contexts
- new getPtr() function returns a pointer to value
- remove functions renamed to fetchRemove
- new remove functions return bool
- removeAssertDiscard deleted, use assert(remove(...)) instead
- Keys and values are stored in separate arrays
- Entry is now {*K, *V}, the new KV is {K, V}
- BufSet/BufMap functions renamed to match other set/map types
- fixed iterating-while-modifying bug in src/link/C.zig
2021-06-03 17:02:16 -05:00
Luuk de Gram 5cbe930e36 wasm: Add stage2 tests for error unions 2021-05-28 12:58:17 +02:00
Luuk de Gram 8a81dfc999 wasm: Reverse the order of error and payload
This will set us up to correctly retrieve the error local index and payload index
depending on that of the multi_value's index. As from now, the error will always use
the multi_value's index, and the payload will use the following locals.
2021-05-28 12:58:17 +02:00
Luuk de Gram 967a299c34 wasm: Add support for error union as return type
- This currently uses the multi-value feature to return both the possible error, and its payload.
- Also genAlloc and the logic to allocate the locals itself have been seperated, so we can create more locals
whenever needed, and not only when `genAlloc` is called.
2021-05-28 12:58:17 +02:00
Luuk de Gram 5481059232 wasm: Implement error unions and unwrapping
- Slightly refactored `Wvalue.multi_value` to also contain the amount of locals it contains,
this allows us to set all fields at once.
2021-05-28 12:58:17 +02:00
Luuk de Gram a5b5a5532e wasm: Support error sets 2021-05-28 12:58:17 +02:00
joachimschmidt557 e8236551ab stage2: Move BlockData out of ir.Inst.Block 2021-05-22 21:15:25 -04:00
Andrew Kelley 63aabbbba7 Merge pull request #8852 from Snektron/spirv
SPIR-V: More codegen
2021-05-22 18:20:20 -04:00
Andrew Kelley 79dee75b1c stage2: rename ir.zig to air.zig
We've settled on the nomenclature for the artifacts the compiler
pipeline produces:

1. Tokens
2. AST (Abstract Syntax Tree)
3. ZIR (Zig Intermediate Representation)
4. AIR (Analyzed Intermediate Representation)
5. Machine Code

Renaming `ir` identifiers to `air` will come with the inevitable
air-memory-layout branch that I plan to start after the 0.8.0 release.
2021-05-22 14:29:16 -07:00
Robin Voetter cba97e4773 SPIR-V: Make functions which always return a null result return void instead 2021-05-22 16:11:56 +02:00
Robin Voetter 228f71fa0c SPIR-V: Generate locals at the start of a function 2021-05-22 16:11:56 +02:00
Robin Voetter 6634abfd26 SPIR-V: Debug line info/source info 2021-05-22 16:11:56 +02:00
Robin Voetter e3be1a1e88 SPIR-V: DeclGen constructor/destructor 2021-05-22 16:11:56 +02:00
Robin Voetter 46184ab85e SPIR-V: branching 2021-05-22 16:11:56 +02:00
Robin Voetter 5edc5f9730 SPIR-V: Pass source location to genType and genConstant for better error reporting 2021-05-22 16:11:56 +02:00
Robin Voetter 63d0576f1c SPIR-V: Preliminary alloc/store/load generation 2021-05-22 16:11:56 +02:00
Robin Voetter 6a121d9ccd SPIR-V: Split out genCmp from genBinOp 2021-05-22 16:11:56 +02:00
Robin Voetter b8444d2c51 SPIR-V: Preliminary integer constant encoding 2021-05-22 16:11:56 +02:00
Robin Voetter c190b2ff83 SPIR-V: ResultId and Word aliases to improve code clarity 2021-05-22 16:11:56 +02:00
Robin Voetter 9ddd7f4a60 SPIR-V: Put types in SPIRVModule, some general restructuring 2021-05-22 16:11:56 +02:00
Robin Voetter bcda3c5b82 SPIR-V: Use Value.toFloat instead of switching on value tag when generating float constants 2021-05-22 16:11:56 +02:00
Luuk de Gram f8d0501f50 Also support multi-prong branches 2021-05-20 16:21:11 +02:00
Luuk de Gram 81d8fe7558 stage2 wasm: Support basic switches
- Adds support for single branches
- Allows both enums and integers
- Supports 'else' branch
2021-05-20 14:21:02 +02:00
Luuk de Gram 87a9c6946d wasm backend: implement multi_value for WValue
This allows us to differentiate between regular locals and variables that create multiple locals
on the stack such as optionals and structs.
Now `struct_a = struct_b;` works and only updates a reference, rather than update all local's values.

Also created more test cases to test against this.
2021-05-20 09:25:02 +02:00
Luuk de Gram 6962647862 Do not create a local for the struct itself + test cases 2021-05-19 10:37:44 +02:00
Luuk de Gram ac5fd47e2e Initial support for structs in wasm backend
- Creates a 'local' for the struct itself and each field
- The index of the local is calculated from the struct's local index + field index
2021-05-19 10:37:44 +02:00
Luuk de Gram 141a0cbb5a Explicit return & more complex wasm enum test
- When returning within a block, we must use an explicit return opcode. For now always emit the opcode when calling return, rather than using implicit return statements.
- Also added a more comprehensive test case to test for enum values using conditions
2021-05-19 10:35:45 +02:00
Luuk de Gram b22e22ef55 wasm backend - Initial enum support
- This adds support for enum values using field indexes
- EmitConstant's signature was changed so it's easier to recursively call it using a different type (enum -> int type).
- Implemented initial support for bitcast which for now just returns the `WValue` of the operand.
2021-05-19 08:59:08 +02:00
Andrew Kelley 615d45da77 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * src/codegen/spirv.zig
 * src/link/SpirV.zig

We're going to want to improve the stage2 test harness to print
the source file name when a compile error occurs otherwise std lib
contributors are going to see some confusing CI failures when they cause
stage2 AstGen compile errors.
2021-05-17 19:30:38 -07:00
Robin Voetter 880473dc3f SPIR-V: Unary not operation 2021-05-16 14:55:09 +02:00
Robin Voetter 489b3ef7d4 SPIR-V: bool binary operations 2021-05-16 14:52:11 +02:00
Robin Voetter 585122b1ac SPIR-V: comparison and equality operations 2021-05-16 14:46:58 +02:00
Robin Voetter f14000c7e1 SPIR-V: More bitwise binary operations 2021-05-16 14:20:18 +02:00
Robin Voetter 4735e95d16 SPIR-V: More binary operations 2021-05-16 14:20:12 +02:00
Robin Voetter 10678af876 SPIR-V: genBinOp setup 2021-05-16 14:13:23 +02:00
Robin Voetter ae2e21639a SPIR-V: Some initial floating point constant generation 2021-05-16 14:13:23 +02:00
Robin Voetter cbf5280f54 SPIR-V: Some instructions + constant generation setup 2021-05-16 14:13:23 +02:00
Robin Voetter da0cc732ea SPIR-V: Function parameter generation 2021-05-16 14:13:23 +02:00
Robin Voetter 074cb9f1da SPIR-V: OpFunction/OpFunctionEnd generation 2021-05-16 14:13:23 +02:00
Robin Voetter 4403f3598a SPIR-V: Proper floating point type generation 2021-05-16 14:13:23 +02:00
Robin Voetter 38cdfebad3 SPIR-V: Function prototype generation 2021-05-16 14:13:23 +02:00
Robin Voetter 458c338aeb SPIR-V: Compute backing integer bits 2021-05-16 14:13:23 +02:00
Robin Voetter de6df2bc12 SPIR-V: Restructure codegen a bit 2021-05-16 14:13:23 +02:00
Andrew Kelley 597082adf4 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * build.zig
 * src/Compilation.zig
 * src/codegen/spirv/spec.zig
 * src/link/SpirV.zig
 * test/stage2/darwin.zig
   - this one might be problematic; start.zig looks for `main` in the
     root source file, not `_main`. Not sure why there is an underscore
     there in master branch.
2021-05-15 21:44:38 -07:00
Andrew Kelley 07606d12da stage2: remove SPU Mark II backend
As it stands, the backend is incomplete, and there is no active contributor,
making it dead weight.

However, anyone is free to resurrect this backend at any time.
2021-05-15 21:25:42 -07:00
Andrew Kelley dc036f5b6f codegen: implement const value rendering for ints <= 64 bits 2021-05-15 21:00:15 -07:00
Robin Voetter 42f2ff6ec9 SPIR-V: Re-generate spec.zig 2021-05-14 19:49:32 +02:00
Robin Voetter d45e7dfc24 SPIR-V: Begin generating types 2021-05-14 19:49:32 +02:00