Commit Graph

91 Commits

Author SHA1 Message Date
Alex Rønne Petersen 39e91deb77 std.Target: add CPU features and models for hppa 2025-11-13 22:29:12 +01:00
Alex Rønne Petersen 2b23f98d2c std.Target: add CPU features and models for alpha 2025-11-13 22:28:50 +01:00
Alex Rønne Petersen 2c470d24b3 std.Target: add Arch tag and info for kvx 2025-11-10 08:20:21 +01:00
Matthew Lugg 74931fe25c std.debug.lockStderrWriter: also return ttyconf
`std.Io.tty.Config.detect` may be an expensive check (e.g. involving
syscalls), and doing it every time we need to print isn't really
necessary; under normal usage, we can compute the value once and cache
it for the whole program's execution. Since anyone outputting to stderr
may reasonably want this information (in fact they are very likely to),
it makes sense to cache it and return it from `lockStderrWriter`. Call
sites who do not need it will experience no significant overhead, and
can just ignore the TTY config with a `const w, _` destructure.
2025-10-30 09:31:28 +00:00
Alex Rønne Petersen 767f28d7a6 Merge pull request #25733 from GasInfinity-Forks/x86_16-cpu_context
* fix: add `i86` cpu in `update_cpu_features`
* feat: add `x86_16` debug `cpu_context`
2025-10-30 01:41:32 +01:00
GasInfinity fca748ffba fix: add i86 cpu in update_cpu_features 2025-10-29 14:34:58 +01:00
Alex Rønne Petersen a7119d4269 remove all IBM AIX and z/OS support
As with Solaris (dba1bf9353), we have no way to
actually audit contributions for these OSs. IBM also makes it even harder than
Oracle to actually obtain these OSs.

closes #23695
closes #23694
closes #3655
closes #23693
2025-10-29 14:25:51 +01:00
Andrew Kelley 4a38d783e8 tools: eliminate dependency on std.SegmentedList 2025-09-19 16:40:00 -07:00
Alex Rønne Petersen 5e9e1fb0c8 std.Target: adjustments to LoongArch CPU models
* Remove the generic model; we already have generic_la32 and generic_la64 and
  pick appropriately based on bitness.
* Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's
  actually pretty misleading and useless; it doesn't represent any real CPU and
  has less features than generic_la64.
* Add la64v1_0 and la64v1_1 models.
* Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to
  the baseline feature set.
2025-09-18 12:42:24 +02:00
Alex Rønne Petersen 978555eea4 std.Target.x86: purge avx10.n-256, rename avx10.n_512 to avx10.n, require evex512 for avx512f
Intel has abandoned AVX10.N/128,256; AVX10.N is now always 512-bit.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen 94f95fefe3 update_cpu_features: bump branch quota for amdgcn
/lib/std/Target/amdgcn.zig:1656:5: error: evaluation exceeded 1000 backwards branches
        for (&result, 0..) |*elem, i| {
        ^~~
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen 5739ce786e update_cpu_features: fix a fmtId call to be fmtIdPU 2025-08-30 06:36:41 +02:00
Andrew Kelley 749f10af49 std.ArrayList: make unmanaged the default 2025-08-11 15:52:49 -07:00
Andrew Kelley 8c9dfcbd0f std.Io: remove BufferedWriter 2025-08-08 17:17:53 -07:00
Alex Rønne Petersen 2ffa63acef tools: fix some bitrot 2025-07-16 06:37:48 +02:00
Andrew Kelley d8e26275f2 update standalone and incremental tests to new API 2025-07-07 22:43:53 -07:00
Ali Cheraghi 1df79ab895 remove spirv cpu arch 2025-06-23 06:03:03 +02:00
Ali Cheraghi 4bf1e4d198 target: auto-generated spirv features 2025-05-21 15:26:18 +03:30
Alex Rønne Petersen 4de368a1b6 std.Target: Update CPU models/features for LLVM 20.
Closes #21818.
2025-04-04 06:08:09 +02:00
Ali Cheraghi d5e1cb3ea2 spirv: ziggify and remove unknown spirv features
`OpCapability` and `OpExtension` now can also be emitted from inline assembly
2025-02-18 18:08:47 +03:30
Alex Rønne Petersen 2fe32ef847 std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead. 2025-02-17 19:17:55 +01:00
Alex Rønne Petersen 5248f0a909 update_cpu_features: Handle targets that don't have LLVM data. 2025-02-17 19:17:55 +01:00
Alex Rønne Petersen ea1502974d wasm: Add a nontrapping_bulk_memory_len0 feature.
This will mainly be used when targeting our wasm2c implementation which has no
problem with zero-length bulk memory operations, as a non-standard extension.
2025-01-22 20:56:28 +01:00
Alex Rønne Petersen 280ced66eb std.Target: Define and use lime1 as the baseline CPU model for WebAssembly.
See: https://github.com/WebAssembly/tool-conventions/pull/235

This is not *quite* using the same features as the spec'd lime1 model because
LLVM 19 doesn't have the level of feature granularity that we need for that.
This will be fixed once we upgrade to LLVM 20.

Part of #21818.
2025-01-22 03:01:05 +01:00
Jacob Young ac1a975f9b x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
David Rubin f36f7d54a7 refactor update_cpu_features.zig
Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
2024-11-25 01:11:15 -08:00
David Rubin 9e17e097e5 make crc32 a featdep of sse4.2
To my knowledge there isn't an implementation of `sse4.2` that doesn't have `crc32`.
The Clang driver also sets `crc32` to be implicitly enabled when an explicit `-crc32`
wasn't provided. This matches that behaviour.

We need this behaviour to compile libraries like `rocksdb` which currently guard against
`crc32` intrinsics by checking for `sse4.2`.
2024-11-25 01:11:15 -08:00
David Rubin bc3ed51b7f cleanup update_cpu_feature.zig
* Cleanup the argument handling logic to allow for optional arguments.
* Add a filter for which `llvm_target` to process.
* Switch to using a threadpool, needed for skipping llvm targets cleanly
  and better distributes the work.
* Remove a seemingly useless piece of logic. I re-ran the script and it gave identical outputs.
2024-11-25 01:11:06 -08:00
Alex Rønne Petersen baf60426d4 std.Target: Rename amdgpu module to amdgcn.
This was an inconsistency left over from c825b567b2.
2024-11-02 10:44:14 +01:00
Alex Rønne Petersen fccf15fc9f std.Target: Remove armv7k/armv7s.
Like d1d95294fd, this is more Apple nonsense where
they abused the arch component of the triple to encode what's really an ABI.

Handling this correctly in Zig's target triple model would take quite a bit of
work. Fortunately, the last Armv7-based Apple Watch was released in 2017 and
these targets are now considered legacy. By the time Zig hits 1.0, they will be
a distant memory. So just remove them.
2024-11-02 10:25:40 +01:00
Alex Rønne Petersen eb363bf845 Merge pull request #21572 from alexrp/tests-llvm-targets
`test`: Rewrite the target triple list for `llvm_targets`.
2024-10-04 19:37:12 +02:00
Alex Rønne Petersen cb1ac0bb2f update_cpu_features: Don't delete the output file if there are no CPU features.
At bare minimum, the compiler expects std.Target.<arch>.cpu.generic to work for
any given architecture when generating the builtin module. So rather than try to
hack that into working when the affected modules are omitted, just actually keep
them.

This affected lanai and xcore.
2024-10-03 05:01:14 +02:00
Alex Rønne Petersen c0561da179 update_cpu_features: Don't set trustzone on cortex-m85.
cortex-m85 already has 8msecext, which is not the same as trustzone. The former
is for the M profile, while the latter is for the A profile.

Revert of a small part of #18498.
2024-09-24 11:45:01 +02:00
Alex Rønne Petersen dcbd3cbce9 update_cpu_features: Add support for parsing DefaultExts as used for aarch64. 2024-09-24 11:08:29 +02:00
Alex Rønne Petersen 662683cafd update_cpu_features: Fix feature_overrides logic and replace an omit_cpus misuse. 2024-09-19 18:20:21 -07:00
Alex Rønne Petersen a4af54b4e5 update_cpu_features: Update for LLVM 19.
* Add `ProcessorAlias` support.
* Bump output buffer size.
* Include `i` extension in RISC-V baselines.
* Update evaluation branch quota for RISC-V.
* Retain some CPU features that LLVM removed.
* Flatten more 'meta-features' used for CPU models.
* Remove some superfluous dependencies.
2024-09-19 18:20:21 -07:00
mlugg 0fe3fd01dd std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
Linus Groh fd434fcd38 std.Target: Rename feature_set_fns to FeatureSetFns
From https://ziglang.org/documentation/master/#Names:

> If `x` is callable, and `x`'s return type is `type`, then `x` should
> be `TitleCase`.
2024-08-12 00:34:59 +01:00
Ryan Liptak cf2558e971 update_cpu_features: Add x86 alias and arm override
Before this commit, the name `v9.5a` was being used for two different features, and one was overwriting the other in the `all_features` array.

`arrowlake_s` is an alias for `arrowlake-s`
2024-08-07 08:56:50 -07:00
Andrew Kelley 727f1fa743 update update_cpu_features tool to latest std.Progress API
closes #20261
2024-06-11 15:24:57 -07:00
Andrew Kelley f47824f24d std: restructure child process namespace 2024-05-26 09:31:55 -07:00
Andrew Kelley 109ec72924 update CPU features to LLVM 18
release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
2024-05-08 19:37:28 -07:00
Carl Åstholm 4c393c7468 Update usages of fmtId/isValidId
`{}` for decls
`{p}` for enum fields
`{p_}` for struct fields and in contexts following a `.`

Elsewhere, `{p}` was used since it's equivalent to the old behavior.
2024-04-07 14:47:11 +02:00
Carl Åstholm f2dfd7d212 Override incorrect ARM Cortex-M series CPU feature definitions
Based on the Arm Cortex-M Processor Comparison Table v3.0
<https://developer.arm.com/documentation/102787/0300/?lang=en>
2024-01-09 17:53:18 +01:00
Carl Åstholm 55f2a6684e update_cpu_features: Support omitting deps 2024-01-09 17:53:09 +01:00
Jan Philipp Hafer fd2239bde9 child_process + Build: rename exec to run + all related code
Justification: exec, execv etc are unix concepts and portable version
should be called differently.

Do no touch non-Zig code. Adjust error names as well, if associated.
Closes #5853.
2023-10-22 14:47:20 -04:00
Andrew Kelley 62a12e0631 LLVM 17 std lib updates and fixes
* some manual fixes to generated CPU features code. in the future it
   would be nice to make the script do those automatically. I suspect
   the sm_90a thing is a bug in LLVM.
 * add liteos to various target OS switches. I know nothing about this
   OS; someone will need to work specifically on support for this OS
   when the time comes to support it properly in zig.
 * while waiting for the compiler, I went ahead and made more
   conservative choices about when to use `inline` in std/Target.zig
2023-09-19 09:37:31 -07:00
Andrew Kelley 3ed40b1140 update CPU features to LLVM 17
release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8
2023-09-19 09:37:31 -07:00
Eric Joldasov 50339f595a all: zig fmt and rename "@XToY" to "@YFromX"
Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
2023-06-19 12:34:42 -07:00
Josh Wolfe 32cb9462ff std: Support user-provided jsonParse method. Unify json.Parser and json.parse* (#15705) 2023-06-19 11:21:37 -04:00