Commit Graph

2327 Commits

Author SHA1 Message Date
mlugg 3ef8bb6354 llvn: fix incorrect mips64 callconv handling 2024-10-19 19:21:32 +01:00
mlugg 1f11eed3d1 llvm: fix lowering of avr_interrupt and m68k_interrupt callconvs 2024-10-19 19:21:32 +01:00
mlugg cb48376bec cbe,translate-c: support more callconvs
There are several more that we could support here, but I didn't feel
like going down the rabbit-hole of figuring them out. In particular,
some of the Clang enum fields aren't specific enough for us, so we'll
have to switch on the target to figure out how to translate-c them. That
can be a future enhancement.
2024-10-19 19:15:24 +01:00
mlugg 2d9a167cd2 std.Target: rename defaultCCallingConvention and Cpu.Arch.fromCallconv 2024-10-19 19:15:23 +01:00
mlugg bc797a97b1 std: update for new CallingConvention
The old `CallingConvention` type is replaced with the new
`NewCallingConvention`. References to `NewCallingConvention` in the
compiler are updated accordingly. In addition, a few parts of the
standard library are updated to use the new type correctly.
2024-10-19 19:15:23 +01:00
mlugg 51706af908 compiler: introduce new CallingConvention
This commit begins implementing accepted proposal #21209 by making
`std.builtin.CallingConvention` a tagged union.

The stage1 dance here is a little convoluted. This commit introduces the
new type as `NewCallingConvention`, keeping the old `CallingConvention`
around. The compiler uses `std.builtin.NewCallingConvention`
exclusively, but when fetching the type from `std` when running the
compiler (e.g. with `getBuiltinType`), the name `CallingConvention` is
used. This allows a prior build of Zig to be used to build this commit.
The next commit will update `zig1.wasm`, and then the compiler and
standard library can be updated to completely replace
`CallingConvention` with `NewCallingConvention`.

The second half of #21209 is to remove `@setAlignStack`, which will be
implemented in another commit after updating `zig1.wasm`.
2024-10-19 19:08:59 +01:00
Andrew Kelley 8504e1f550 Merge pull request #21610 from alexrp/riscv-abis
Fix some RISC-V ABI issues and add ILP32/LP64 (soft float) to module tests
2024-10-17 12:54:44 -07:00
Alex Rønne Petersen 7a3626d1c6 llvm: Disable f16 lowering for loongarch.
This should be reverted with LLVM 20.
2024-10-16 01:19:00 +02:00
Alex Rønne Petersen 5e4249eb8b llvm: Fix natural int width specifications for loongarch in DataLayoutBuilder. 2024-10-16 01:10:36 +02:00
Alex Rønne Petersen 958f57d65d llvm: Enable native f16 lowering for riscv32. 2024-10-15 19:29:56 +02:00
Alex Rønne Petersen 3550cacd73 llvm: Fix compiler crash when lowering f16 for riscv32 ilp32. 2024-10-15 19:29:56 +02:00
Robin Voetter e2e79960d2 Merge pull request #21688 from Snektron/spirv-fix
spirv: fix some bitrot
2024-10-13 22:33:03 +02:00
David Rubin e131a2c8e2 implement packed struct equality (#21679) 2024-10-12 20:59:12 -07:00
Robin Voetter c1132edd53 spirv: don't generate OpUnreachable after noreturn call
It seems that these are now automatically added to AIR in Sema.
2024-10-13 01:57:35 +02:00
Robin Voetter 973f846251 spirv: implement repeat and dbg_arg_inline 2024-10-13 01:57:06 +02:00
Robin Voetter 3cd19b8884 spirv: don't try to lower types which have no runtime bits 2024-10-13 01:56:33 +02:00
Alex Rønne Petersen ece265b1c2 Merge pull request #21605 from alexrp/ohos-stuff
`std.Target`: Introduce `Abi.ohoseabi` to distinguish the soft float case.
2024-10-06 16:26:24 +02:00
Alex Rønne Petersen be5378b038 Merge pull request #21587 from alexrp/hexagon-porting
Some initial `hexagon-linux` port work
2024-10-06 13:35:56 +02:00
Alex Rønne Petersen 84e192c88b std.Target: Introduce Abi.ohoseabi to distinguish the soft float case.
For the same reason as #21504.
2024-10-05 15:13:37 +02:00
Alex Rønne Petersen d23db9427b Merge pull request #21574 from alexrp/llvm-sub-arch
`llvm`: Implement sub-architecture translation in `targetTriple()`.
2024-10-05 13:49:05 +02:00
David Rubin 043b1adb8d remove @fence (#21585)
closes #11650
2024-10-04 22:21:27 +00:00
Felix Queißner 7c74edec8d Adds new cpu architectures propeller1 and propeller2. (#21563)
* Adds new cpu architectures propeller1 and propeller2.

These cpu architectures allow targeting the Parallax Propeller 1 and Propeller 2, which are both very special microcontrollers with 512 registers and 8 cpu cores.

Resolves #21559

* Adds std.elf.EM.PROPELLER and std.elf.EM.PROPELLER2
* Fixes missing switch prongs in src/codegen/llvm.zig
* Fixes order in std.Target.Arch

---------

Co-authored-by: Felix "xq" Queißner <git@random-projects.net>
2024-10-04 13:53:28 -07:00
Alex Rønne Petersen eb363bf845 Merge pull request #21572 from alexrp/tests-llvm-targets
`test`: Rewrite the target triple list for `llvm_targets`.
2024-10-04 19:37:12 +02:00
Alex Rønne Petersen f31173d379 llvm: Disable f16 lowering for hexagon.
In theory, this should work for v68+. In practice, it runs into an LLVM
assertion when using a `freeze` instruction on `f16` values, similar to the
issue we had for LoongArch.
2024-10-03 09:53:59 +02:00
Alex Rønne Petersen b4ddff396d llvm: Fix C ABI integer promotion for s390x. 2024-10-03 06:19:23 +02:00
Alex Rønne Petersen 3f322c49bc std.Target: Remove Os.Tag.shadermodel.
This was a leftover from the Cpu.Arch.dxil removal.
2024-10-03 05:01:24 +02:00
Alex Rønne Petersen 85bf1e2b1f llvm: Implement sub-architecture translation in targetTriple(). 2024-10-03 02:39:12 +02:00
Alex Rønne Petersen e0ac776749 Merge pull request #21504 from alexrp/android-softfp
`std.Target`: Introduce `Abi.androideabi` to distinguish the soft float case.
2024-10-03 00:15:35 +02:00
Andrew Kelley 1b491e640d fixes and make sema report errors when std.builtin wrong
instead of panicking
2024-09-26 16:06:05 -07:00
Andrew Kelley b66cc5af41 reimplement integer overflow safety panic function calls
in the llvm backend.
2024-09-26 12:35:14 -07:00
Andrew Kelley 9ccf8d3332 fixes for this branch
I had to bring back some of the old API so that I could compile the new
compiler with an old compiler.
2024-09-26 12:35:14 -07:00
Alex Rønne Petersen ebbc50d8be std.Target: Introduce Abi.androideabi to distinguish the soft float case.
Abi.android on its own is not enough to know whether soft float or hard float
should be used. In the C world, androideabi is typically used for the soft float
case, so let's go with that.

Note that Android doesn't have a hard float ABI, so no androideabihf.

Closes #21488.
2024-09-24 09:23:24 +02:00
Alex Rønne Petersen d1901c744c std.Target: Remove Cpu.Arch.dxil and ObjectFormat.dxcontainer.
See: https://devblogs.microsoft.com/directx/directx-adopting-spir-v

Since we never hooked up the (experimental) DirectX LLVM backend, we've never
actually supported targeting DXIL in Zig. With Microsoft moving away from DXIL,
that seems very unlikely to change.
2024-09-23 17:17:25 -07:00
Alex Rønne Petersen 894b732630 Partially revert "LLVM: work around @floatFromInt bug"
This partially reverts commit ab4d6bf468.
2024-09-19 18:20:21 -07:00
Alex Rønne Petersen a4d0a01243 std.Target: Add bridgeos tag to Os. 2024-09-19 18:20:21 -07:00
Alex Rønne Petersen a27f4072ec llvm: Stop emitting shl/xor ops for constant packed structs.
This is no longer supported in LLVM 19; fall back to the generic code path.
2024-09-19 18:20:21 -07:00
Alex Rønne Petersen 973ebeb610 zig_llvm: Update to LLVM 19. 2024-09-19 18:20:20 -07:00
Linus Groh 8588964972 Replace deprecated default initializations with decl literals 2024-09-12 16:01:23 +01:00
Andrew Kelley 4fba7336a9 Merge pull request #21269 from alexrp/soft-float
Fix soft float support, split musl triples by float ABI, and enable CI
2024-09-11 17:41:55 -07:00
Alex Rønne Petersen 2fc1f9b971 llvm: Don't use the optimized jump table construction logic for wasm. 2024-09-10 16:09:43 -07:00
Alex Rønne Petersen 70c92331c7 llvm: Limit f16/f128 lowering on arm to fp_armv8 and soft float. 2024-09-10 08:53:30 +02:00
Alex Rønne Petersen 6836799935 llvm: Set use-soft-float and noimplicitfloat on functions for soft float.
Closes #10961.
2024-09-10 08:53:30 +02:00
Maciej 'vesim' Kuliński fb0028a0d7 mips: fix C ABI compatibility 2024-09-07 23:46:30 -07:00
Andrew Kelley 5f3d9e0b7a Merge pull request #21261 from alexrp/riscv32
More `riscv32-linux` port work
2024-09-06 17:43:10 -07:00
Alex Rønne Petersen 92517fbd62 llvm: Set float ABI based on std.Target.floatAbi(). 2024-09-06 20:11:47 +02:00
Alex Rønne Petersen ae10adb6ef llvm: Don't lower to f16 for riscv32.
This causes so many test failures that I doubt this has been tested at all.
2024-09-06 20:03:15 +02:00
Andrew Kelley 3929cac154 Merge pull request #21257 from mlugg/computed-goto-3
compiler: implement labeled switch/continue
2024-09-04 18:31:28 -07:00
mlugg 289c704b60 cbe: don't emit 'x = x' in switch dispatch loop 2024-09-01 20:31:01 +01:00
mlugg 5e12ca9fe3 compiler: implement labeled switch/continue 2024-09-01 18:30:31 +01:00
mlugg 5fb4a7df38 Air: add explicit repeat instruction to repeat loops
This commit introduces a new AIR instruction, `repeat`, which causes
control flow to move back to the start of a given AIR loop. `loop`
instructions will no longer automatically perform this operation after
control flow reaches the end of the body.

The motivation for making this change now was really just consistency
with the upcoming implementation of #8220: it wouldn't make sense to
have this feature work significantly differently. However, there were
already some TODOs kicking around which wanted this feature. It's useful
for two key reasons:

* It allows loops over AIR instruction bodies to loop precisely until
  they reach a `noreturn` instruction. This allows for tail calling a
  few things, and avoiding a range check on each iteration of a hot
  path, plus gives a nice assertion that validates AIR structure a
  little. This is a very minor benefit, which this commit does apply to
  the LLVM and C backends.

* It should allow for more compact ZIR and AIR to be emitted by having
  AstGen emit `repeat` instructions more often rather than having
  `continue` statements `break` to a `block` which is *followed* by a
  `repeat`. This is done in status quo because `repeat` instructions
  only ever cause the direct parent block to repeat. Now that AIR is
  more flexible, this flexibility can be pretty trivially extended to
  ZIR, and we can then emit better ZIR. This commit does not implement
  this.

Support for this feature is currently regressed on all self-hosted
native backends, including x86_64. This support will be added where
necessary before this branch is merged.
2024-09-01 18:30:31 +01:00