79 Commits

Author SHA1 Message Date
Alex Rønne Petersen ca0b3318a0 std.Target: update CPU and feature data to LLVM 22 2026-04-25 21:54:47 +02:00
Ryan Liptak 3252a05531 Prefer <err> => |e| return e over <err> => return <err>
Avoids the potential for a typo on the `return <err>` side of the prong
2026-04-20 18:03:14 -07:00
Nathan Bourgeois c824ce954e misc: Add allegrex CPU & features, run tool, update semver 2026-03-21 19:39:04 -04:00
Alex Rønne Petersen 65b0a2342b std.Target.x86: refresh from update_cpu_features.zig
Just to get rid of this ordering diff.
2025-11-13 22:29:28 +01:00
Alex Rønne Petersen 39e91deb77 std.Target: add CPU features and models for hppa 2025-11-13 22:29:12 +01:00
Alex Rønne Petersen 2b23f98d2c std.Target: add CPU features and models for alpha 2025-11-13 22:28:50 +01:00
Alex Rønne Petersen 2c470d24b3 std.Target: add Arch tag and info for kvx 2025-11-10 08:20:21 +01:00
Jacob Young 5b060ef9d4 Merge pull request #25558 from jacobly0/elfv2-load-obj
Elf2: start implementing input object loading
2025-10-30 12:09:13 -04:00
Alex Rønne Petersen 767f28d7a6 Merge pull request #25733 from GasInfinity-Forks/x86_16-cpu_context
* fix: add `i86` cpu in `update_cpu_features`
* feat: add `x86_16` debug `cpu_context`
2025-10-30 01:41:32 +01:00
Jacob Young 0834e696f7 Elf2: start implementing dynamic linking 2025-10-29 18:15:09 -04:00
Andrew Kelley a072d821be Merge pull request #25592 from ziglang/init-std.Io
std: Introduce `Io` Interface
2025-10-29 13:51:37 -07:00
GasInfinity fca748ffba fix: add i86 cpu in update_cpu_features 2025-10-29 14:34:58 +01:00
Alex Rønne Petersen a7119d4269 remove all IBM AIX and z/OS support
As with Solaris (dba1bf9353), we have no way to
actually audit contributions for these OSs. IBM also makes it even harder than
Oracle to actually obtain these OSs.

closes #23695
closes #23694
closes #3655
closes #23693
2025-10-29 14:25:51 +01:00
Andrew Kelley 066864a0bf std.zig.system: upgrade to std.Io.Reader 2025-10-29 06:20:48 -07:00
Alex Rønne Petersen 7881a60f1a std.Target.aarch64: updates for LLVM 21.1.5 2025-10-29 07:48:12 +01:00
Alex Rønne Petersen 06d9e3bc06 Merge pull request #25691 from GasInfinity-Forks/x86_16-gcc
feat: init x86_16 arch via CBE
2025-10-28 10:19:21 +01:00
Sean 35e1755c99 Fix stale reference bug in std.zig.system.resolveTargetQuery (#25713)
Co-authored-by: Alex Rønne Petersen <alex@alexrp.com>
2025-10-28 10:17:09 +01:00
GasInfinity 104c272ae5 feat: init x86_16 arch via CBE 2025-10-27 11:19:51 +01:00
Alex Rønne Petersen 5e9e1fb0c8 std.Target: adjustments to LoongArch CPU models
* Remove the generic model; we already have generic_la32 and generic_la64 and
  pick appropriately based on bitness.
* Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's
  actually pretty misleading and useless; it doesn't represent any real CPU and
  has less features than generic_la64.
* Add la64v1_0 and la64v1_1 models.
* Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to
  the baseline feature set.
2025-09-18 12:42:24 +02:00
Alex Rønne Petersen 978555eea4 std.Target.x86: purge avx10.n-256, rename avx10.n_512 to avx10.n, require evex512 for avx512f
Intel has abandoned AVX10.N/128,256; AVX10.N is now always 512-bit.
2025-08-30 06:36:41 +02:00
Alex Rønne Petersen 587eddda28 std.Target: update CPU features to LLVM 21 2025-08-30 06:36:41 +02:00
Andrew Kelley 749f10af49 std.ArrayList: make unmanaged the default 2025-08-11 15:52:49 -07:00
KNnut fcb088cb6a std.Target.Query: fix WindowsVersion format in zigTriple() 2025-08-05 06:08:42 +02:00
Andrew Kelley 0e37ff0d59 std.fmt: breaking API changes
added adapter to AnyWriter and GenericWriter to help bridge the gap
between old and new API

make std.testing.expectFmt work at compile-time

std.fmt no longer has a dependency on std.unicode. Formatted printing
was never properly unicode-aware. Now it no longer pretends to be.

Breakage/deprecations:
* std.fs.File.reader -> std.fs.File.deprecatedReader
* std.fs.File.writer -> std.fs.File.deprecatedWriter
* std.io.GenericReader -> std.io.Reader
* std.io.GenericWriter -> std.io.Writer
* std.io.AnyReader -> std.io.Reader
* std.io.AnyWriter -> std.io.Writer
* std.fmt.format -> std.fmt.deprecatedFormat
* std.fmt.fmtSliceEscapeLower -> std.ascii.hexEscape
* std.fmt.fmtSliceEscapeUpper -> std.ascii.hexEscape
* std.fmt.fmtSliceHexLower -> {x}
* std.fmt.fmtSliceHexUpper -> {X}
* std.fmt.fmtIntSizeDec -> {B}
* std.fmt.fmtIntSizeBin -> {Bi}
* std.fmt.fmtDuration -> {D}
* std.fmt.fmtDurationSigned -> {D}
* {} -> {f} when there is a format method
* format method signature
  - anytype -> *std.io.Writer
  - inferred error set -> error{WriteFailed}
  - options -> (deleted)
* std.fmt.Formatted
  - now takes context type explicitly
  - no fmt string
2025-07-07 22:43:51 -07:00
Ali Cheraghi 1df79ab895 remove spirv cpu arch 2025-06-23 06:03:03 +02:00
Jacob Young 917640810e Target: pass and use locals by pointer instead of by value
This struct is larger than 256 bytes and code that copies it
consistently shows up in profiles of the compiler.
2025-06-19 11:45:06 -04:00
Alex Rønne Petersen 9d534790eb std.Target: Introduce Cpu convenience functions for feature tests.
Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
Ali Cheraghi 4bf1e4d198 target: auto-generated spirv features 2025-05-21 15:26:18 +03:30
Ali Cheraghi 0901328f12 spirv: write error value in an storage buffer 2025-05-21 12:57:40 +03:30
Alex Rønne Petersen 4de368a1b6 std.Target: Update CPU models/features for LLVM 20.
Closes #21818.
2025-04-04 06:08:09 +02:00
Ali Cheraghi ee06b2ce76 spirv: require int8/int16 capabilities 2025-03-18 07:05:50 +03:30
Ali Cheraghi 50539a2447 spirv/target: arbitrary_precision_integers feature support 2025-03-17 21:56:17 +03:30
Ali Cheraghi 78ad866dd1 target: split addresses and physical_storage_buffer features 2025-03-17 21:56:17 +03:30
Alex Rønne Petersen 9840157c18 std.Target.Query: Don't append glibc version in zigTriple() if ABI isn't GNU. 2025-03-09 19:50:13 +01:00
Ali Cheraghi a0eec9ce9e spirv: replace some unreachables with compile errors 2025-02-24 19:12:33 +01:00
Ali Cheraghi d5e1cb3ea2 spirv: ziggify and remove unknown spirv features
`OpCapability` and `OpExtension` now can also be emitted from inline assembly
2025-02-18 18:08:47 +03:30
Ali Cheraghi 1b0c7f51ef target: update spirv features 2025-02-18 18:07:48 +03:30
Alex Rønne Petersen 481b7bf3f0 std.Target: Remove functions that just wrap component functions.
Functions like isMinGW() and isGnuLibC() have a good reason to exist: They look
at multiple components of the target. But functions like isWasm(), isDarwin(),
isGnu(), etc only exist to save 4-8 characters. I don't think this is a good
enough reason to keep them, especially given that:

* It's not immediately obvious to a reader whether target.isDarwin() means the
  same thing as target.os.tag.isDarwin() precisely because isMinGW() and similar
  functions *do* look at multiple components.
* It's not clear where we would draw the line. The logical conclusion before
  this commit would be to also wrap Arch.isX86(), Os.Tag.isSolarish(),
  Abi.isOpenHarmony(), etc... this obviously quickly gets out of hand.
* It's nice to just have a single correct way of doing something.
2025-02-17 19:18:19 +01:00
Alex Rønne Petersen 2fe32ef847 std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead. 2025-02-17 19:17:55 +01:00
Alex Rønne Petersen ea1502974d wasm: Add a nontrapping_bulk_memory_len0 feature.
This will mainly be used when targeting our wasm2c implementation which has no
problem with zero-length bulk memory operations, as a non-standard extension.
2025-01-22 20:56:28 +01:00
Alex Rønne Petersen 280ced66eb std.Target: Define and use lime1 as the baseline CPU model for WebAssembly.
See: https://github.com/WebAssembly/tool-conventions/pull/235

This is not *quite* using the same features as the spec'd lime1 model because
LLVM 19 doesn't have the level of feature granularity that we need for that.
This will be fixed once we upgrade to LLVM 20.

Part of #21818.
2025-01-22 03:01:05 +01:00
Jacob Young ac1a975f9b x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
mlugg da1ffae7d2 std: fix undefined value in Target.Query
This is an RLS footgun.

Resolves: #21834
2025-01-05 16:26:21 +00:00
Alex Rønne Petersen 8594f179f9 Merge pull request #22067 from alexrp/pie-tests
Add PIC/PIE tests and fix some bugs + some improvements to the test harness
2024-11-28 14:07:28 +01:00
David Rubin f36f7d54a7 refactor update_cpu_features.zig
Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
2024-11-25 01:11:15 -08:00
David Rubin 9e17e097e5 make crc32 a featdep of sse4.2
To my knowledge there isn't an implementation of `sse4.2` that doesn't have `crc32`.
The Clang driver also sets `crc32` to be implicitly enabled when an explicit `-crc32`
wasn't provided. This matches that behaviour.

We need this behaviour to compile libraries like `rocksdb` which currently guard against
`crc32` intrinsics by checking for `sse4.2`.
2024-11-25 01:11:15 -08:00
Alex Rønne Petersen 24ecf45569 std.Target: Add Os.HurdVersionRange for Os.Tag.hurd.
This is necessary since isGnuLibC() is true for hurd, so we need to be able to
represent a glibc version for it.

Also add an Os.TaggedVersionRange.gnuLibCVersion() convenience function.
2024-11-24 22:11:16 +01:00
Daniel Hooper ed04acf90d Provide a detailed message for invalid arch in target triple (#21921) 2024-11-06 03:38:01 +00:00
Alex Rønne Petersen baf60426d4 std.Target: Rename amdgpu module to amdgcn.
This was an inconsistency left over from c825b567b2.
2024-11-02 10:44:14 +01:00
Alex Rønne Petersen fccf15fc9f std.Target: Remove armv7k/armv7s.
Like d1d95294fd, this is more Apple nonsense where
they abused the arch component of the triple to encode what's really an ABI.

Handling this correctly in Zig's target triple model would take quite a bit of
work. Fortunately, the last Armv7-based Apple Watch was released in 2017 and
these targets are now considered legacy. By the time Zig hits 1.0, they will be
a distant memory. So just remove them.
2024-11-02 10:25:40 +01:00