Commit Graph

166 Commits

Author SHA1 Message Date
Ali Cheraghi aec0f9b3e7 test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Jacob Young fa9b0fa6d3 x86_64: rewrite most of the remaining float ops 2025-02-06 16:14:53 -05:00
Jacob Young c3d33440f0 x86_64: pass more behavior tests 2025-01-16 20:47:30 -05:00
Jacob Young e5d5a8bc4e x86_64: implement switch jump tables 2025-01-16 20:42:08 -05:00
Jacob Young ac1a975f9b x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
Alex Rønne Petersen 52e9fd7c3c test: Disable vector behavior tests affected by #22060 for thumbeb too. 2025-01-06 16:20:27 +01:00
Alex Rønne Petersen 1e61399537 test: Disable some vector behavior tests on armeb.
https://github.com/ziglang/zig/issues/22060
2024-12-13 03:13:14 +01:00
Alex Rønne Petersen 2958a90515 test: Disable some vector behavior tests on aarch64_be.
See: https://github.com/ziglang/zig/issues/21893
2024-11-04 08:29:42 +01:00
Alex Rønne Petersen c9e67e71c1 std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().
The old isARM() function was a portability trap. With the name it had, it seemed
like the obviously correct function to use, but it didn't include Thumb. In the
vast majority of cases where someone wants to ask "is the target Arm?", Thumb
*should* be included.

There are exactly 3 cases in the codebase where we do actually need to exclude
Thumb, although one of those is in Aro and mirrors a check in Clang that is
itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-11-03 09:29:30 +01:00
Alex Rønne Petersen f8719c4197 test: Re-enable store vector with memset for LLVM.
Closes #16177.
2024-09-19 18:20:21 -07:00
Alex Rønne Petersen 5cb9668632 test: Re-enable a bunch of behavior tests with LLVM.
Closes #10627.
Closes #12013.
Closes #18034.
2024-09-12 07:28:37 +02:00
Andrew Kelley 4fba7336a9 Merge pull request #21269 from alexrp/soft-float
Fix soft float support, split musl triples by float ABI, and enable CI
2024-09-11 17:41:55 -07:00
Alex Rønne Petersen 5285f41267 test: Disable store vector with memset on soft float arm.
https://github.com/ziglang/zig/issues/16177
2024-09-10 08:53:30 +02:00
Alex Rønne Petersen ccf852c31e test: Re-enable vector reduce operation for most LLVM targets.
mips64 failure is tracked in #21091.

Closes #7138.
2024-09-07 02:47:57 +02:00
Alex Rønne Petersen 5c128a8990 test: Re-enable vector shift operators for all LLVM targets.
Closes #4951.
2024-09-07 02:47:57 +02:00
Alex Rønne Petersen 40ee682517 test: Disable store vector with memset on powerpc64.
This will be re-enabled with LLVM 19.
2024-09-05 01:15:33 +02:00
mlugg 0fe3fd01dd std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
Alex Rønne Petersen ecbc701376 test: Disable vector reduce operation on mips64.
https://github.com/ziglang/zig/issues/21091
2024-08-18 07:27:23 +02:00
Alex Rønne Petersen 19a91084c2 test: Partially disable vector float operators on mips.
https://github.com/ziglang/zig/issues/21051
2024-08-12 13:34:19 +02:00
Alex Rønne Petersen d1d95294fd std.Target.Cpu.Arch: Remove the aarch64_32 tag.
This is a misfeature that we inherited from LLVM:

* https://reviews.llvm.org/D61259
* https://reviews.llvm.org/D61939

(`aarch64_32` and `arm64_32` are equivalent.)

I truly have no idea why this triple passed review in LLVM. It is, to date, the
*only* tag in the architecture component that is not, in fact, an architecture.
In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32).

The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes,
that triple is exactly what you think; it has no ABI component. They really,
seriously did this.

Since only Apple could come up with silliness like this, it should come as no
surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for
AArch64 was developed, and support was added to LLVM:

* https://reviews.llvm.org/D94143
* https://reviews.llvm.org/D104931

Here, sanity seems to have prevailed, and a triple using this ABI looks like
`aarch64-linux-gnu_ilp32` as you would expect.

As can be seen from the diffs in this commit, there was plenty of confusion
throughout the Zig codebase about what exactly `aarch64_32` was. So let's just
remove it. In its place, we'll use `aarch64-watchos-ilp32`,
`aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately
when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already
have `gnuilp32`).
2024-07-28 19:44:52 -07:00
David Rubin 81ca3a1d59 riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin cde6956b21 riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin 9766b68c47 riscv: un-cache the avl and vtype when returning from a function call
the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function.
the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something
needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-26 04:05:38 -07:00
Julian Vesper 3344ed8b8f aarch64: reenable tests that are no longer regressed
Closes #12012
2024-07-25 20:23:23 +03:00
Jacob Young 40bab4df69 behavior: disable test that triggers an llvm assertion
Tracked by #20680
2024-07-19 04:35:11 -04:00
David Rubin 5a4fe39fbb riscv: disable failing tests 2024-07-14 23:04:06 -07:00
David Rubin 5a2c547fc1 riscv: vectors part 3 2024-07-14 23:02:35 -07:00
David Rubin 7a02878f4e riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin 4fd8900337 riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin 031d8248e0 riscv: first sign of floats! 2024-06-13 02:21:38 -07:00
Robin Voetter a3b1ba82f5 spirv: new vectorization helper
The old vectorization helper (WipElementWise) was clunky and a bit
annoying to use, and it wasn't really flexible enough.

This introduces a new vectorization helper, which uses Temporary and
Operation types to deduce a Vectorization to perform the operation
in a reasonably efficient manner. It removes the outer loop
required by WipElementWise so that implementations of AIR instructions
are cleaner. This helps with sanity when we start to introduce support
for composite integers.

airShift, convertToDirect, convertToIndirect, and normalize are initially
implemented using this new method.
2024-06-10 20:32:49 +02:00
Robin Voetter b9d738a5cf spirv: disable tests that fail on pocl
Besides the Intel OpenCL CPU runtime, we can now run the
behavior tests using the Portable Computing Language. This
implementation is open-source, so it will be easier for us
to patch in updated versions of spirv-llvm-translator that
have bug fixes etc.
2024-06-10 20:32:34 +02:00
David Rubin a30af172e8 riscv: math progress 2024-05-11 02:17:24 -07:00
David Rubin d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
Jacob Young f1c0f42cdd cbe: fix optional codegen
Also reduce ctype pool string memory usage, remove self assignments, and
enable more warnings.
2024-04-13 01:35:20 -04:00
Robin Voetter ac16545895 spirv: enable passing tests 2024-04-06 13:52:48 +02:00
Ali Chraghi 436f53f55d spirv: implement @mulWithOverflow 2024-04-06 09:01:46 +03:30
Jacob Young 5a41704f7e cbe: rewrite CType
Closes #14904
2024-03-30 20:50:48 -04:00
Robin Voetter 2f9e37ade0 spirv: enable passing tests 2024-03-18 19:13:51 +01:00
Meghan Denny 4b1edad6e2 test: reenable some behavior vector tests 2024-03-15 16:42:10 +02:00
Jacob Young 2fdc9e6ae8 x86_64: implement @shuffle 2024-02-25 11:22:10 +01:00
Jacob Young a9f738e56b x86_64: implement c abi for bool vectors 2024-02-12 05:25:07 +01:00
Ali Chraghi 37b0aa600a spirv: make rusticl the primary testing implementation 2024-02-09 09:27:08 +03:30
Jakub Konka 52066bf8e4 x86_64+macho: pass more behavior tests 2024-02-06 19:01:17 +01:00
Robin Voetter 2511106150 spirv: air vector_store_element 2024-02-04 19:09:34 +01:00
Robin Voetter 9fbba0e01a spirv: update tests 2024-02-04 19:09:33 +01:00
Robin Voetter 1d548aa2aa spirv: air splat 2024-02-04 19:09:33 +01:00
Robin Voetter 631d1b63a8 spirv: fix shuffle properly 2024-02-04 19:09:32 +01:00
Robin Voetter b67d983abd spirv: vectorize add/sub overflow 2024-02-04 19:09:27 +01:00
Robin Voetter 761594e226 spirv: reduce, reduce_optimized 2024-02-04 19:09:27 +01:00