Mirrors/zig
1
0
Fork 0
mirror of https://codeberg.org/ziglang/zig.git synced 2026-05-31 21:35:57 +03:00
Code Issues Packages Projects Releases Wiki Activity

std.Target: update CPU and feature data to LLVM 22

Browse Source
This commit is contained in:
Alex Rønne Petersen
2026-01-17 06:54:56 +01:00
parent c855c61432
commit ca0b3318a0
22 changed files with 2008 additions and 395 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/codegen/llvm.zig
+1
View File
@@ -162,6 +162,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
.{ .v9_4a, "v9.4a" },
.{ .v9_5a, "v9.5a" },
.{ .v9_6a, "v9.6a" },
.{ .v9_7a, "v9.7a" },
}),
.powerpc => subArchName(target, .powerpc, .{
.{ .spe, "spe" },
src/codegen/llvm/FuncGen.zig
+4 -4
View File
@@ -6630,11 +6630,11 @@ const ParamTypeIterator = struct {
} else if (isByRef(ty, zcu)) {
return .byref;
} else if (target.cpu.arch.isX86() and
!target.cpu.has(.x86, .evex512) and
!target.cpu.has(.x86, .avx512f) and
ty.totalVectorBits(zcu) >= 512)
{
// As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
// "512-bit vector arguments require 'evex512' for AVX512"
// "512-bit vector arguments require 'avx512f' for AVX512"
return .byref;
} else {
return .byval;
@@ -6902,11 +6902,11 @@ fn returnTypeByRef(zcu: *Zcu, target: *const std.Target, ty: Type) bool {
if (isByRef(ty, zcu)) {
return true;
} else if (target.cpu.arch.isX86() and
!target.cpu.has(.x86, .evex512) and
!target.cpu.has(.x86, .avx512f) and
ty.totalVectorBits(zcu) >= 512)
{
// As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
// "512-bit vector arguments require 'evex512' for AVX512"
// "512-bit vector arguments require 'avx512f' for AVX512"
return true;
} else {
return false;