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Merge pull request #21587 from alexrp/hexagon-porting

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Some initial `hexagon-linux` port work
This commit is contained in:
Alex Rønne Petersen
2024-10-06 13:35:56 +02:00
committed by GitHub
parent 008bb1f120 45644b7e15
commit be5378b038
12 changed files with 281 additions and 11 deletions
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lib/std/atomic.zig
+4 -2
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@@ -433,18 +433,20 @@ pub const cache_line = switch (builtin.cpu.arch) {
.powerpc64le,
=> 128,
// https://github.com/llvm/llvm-project/blob/e379094328e49731a606304f7e3559d4f1fa96f9/clang/lib/Basic/Targets/Hexagon.h#L145-L151
.hexagon,
=> if (std.Target.hexagon.featureSetHas(builtin.target.cpu.features, .v73)) 64 else 32,
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/hexagon/include/asm/cache.h#L13
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
.arm,
.armeb,
.thumb,
.thumbeb,
.hexagon,
.mips,
.mipsel,
.mips64,