allow in-memory coercion of differently-named floats with same bits

For example, this allows passing a `*c_longdouble` where a `*f80` is
expected, provided that `c_longdouble` maps to `f80` for this target.

src/Sema.zig

@@ -18673,6 +18673,15 @@ fn coerceInMemoryAllowed(
         }
     }
 
+    // Differently-named floats with the same number of bits.
+    if (dest_ty.zigTypeTag() == .Float and src_ty.zigTypeTag() == .Float) {
+        const dest_bits = dest_ty.floatBits(target);
+        const src_bits = src_ty.floatBits(target);
+        if (dest_bits == src_bits) {
+            return .ok;
+        }
+    }
+
     // Pointers / Pointer-like Optionals
     var dest_buf: Type.Payload.ElemType = undefined;
     var src_buf: Type.Payload.ElemType = undefined;

src/stage1/ir.cpp

@@ -4480,6 +4480,12 @@ static ConstCastOnly types_match_const_cast_only(IrAnalyze *ira, ZigType *wanted
         return result;
     }
 
+    if (wanted_type->id == ZigTypeIdFloat && actual_type->id == ZigTypeIdFloat) {
+        if (wanted_type->data.floating.bit_count == actual_type->data.floating.bit_count) {
+            return result;
+        }
+    }
+
     if (wanted_type->id == ZigTypeIdVector && actual_type->id == ZigTypeIdVector) {
         if (actual_type->data.vector.len != wanted_type->data.vector.len) {
             result.id = ConstCastResultIdVectorLength;