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test: re-enable a bunch of vector behavior tests on hexagon

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Alex Rønne Petersen
2025-08-03 15:21:46 +02:00
parent 0683e1564c
commit 2cb412ff1b
2 changed files with 6 additions and 6 deletions
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test/behavior/vector.zig
+5 -1
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@@ -639,6 +639,7 @@ test "vector division operators" {
try comptime S.doTheTest();
if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060
if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
try S.doTheTest();
}
@@ -767,8 +768,9 @@ test "vector shift operators" {
}
};
try S.doTheTest();
try comptime S.doTheTest();
if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
try S.doTheTest();
}
test "vector reduce operation" {
@@ -1271,6 +1273,7 @@ test "byte vector initialized in inline function" {
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and comptime builtin.cpu.has(.x86, .avx512f)) {
// TODO https://github.com/ziglang/zig/issues/13279
@@ -1337,6 +1340,7 @@ test "@intCast to u0" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
var zeros = @Vector(2, u32){ 0, 0 };
_ = &zeros;