rust/compiler/rustc_codegen_llvm at d0442e2800d356ae282ddcdbe0eff8798fe648b6 - rust

mirror of https://github.com/rust-lang/rust.git synced 2026-04-27 18:57:42 +03:00

Files

T

Jonathan Brouwer 3fb712c80a Rollup merge of #154719 - androm3da:hexagon-inline-asm-register-classes, r=JohnTitor

Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes

Add three new register classes for the Hexagon inline assembly backend:

* `reg_pair`: GPR double registers (r1:0 through r27:26)
* `vreg`: HVX vector registers (v0-v31)
* `qreg`: HVX predicate registers (q0-q3), clobber-only for now

2026-04-08 23:04:34 +02:00

src

Rollup merge of #154719 - androm3da:hexagon-inline-asm-register-classes, r=JohnTitor

2026-04-08 23:04:34 +02:00

Cargo.toml

Remove last remnants of rustc_query_system.

2026-02-16 22:56:47 +11:00

README.md

mv compiler to compiler/

2020-08-30 18:45:07 +03:00

README.md

The codegen crate contains the code to convert from MIR into LLVM IR, and then from LLVM IR into machine code. In general it contains code that runs towards the end of the compilation process.

For more information about how codegen works, see the rustc dev guide.