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Jonathan Brouwer
3fb712c80a
Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes Add three new register classes for the Hexagon inline assembly backend: * `reg_pair`: GPR double registers (r1:0 through r27:26) * `vreg`: HVX vector registers (v0-v31) * `qreg`: HVX predicate registers (q0-q3), clobber-only for now
The codegen crate contains the code to convert from MIR into LLVM IR,
and then from LLVM IR into machine code. In general it contains code
that runs towards the end of the compilation process.
For more information about how codegen works, see the rustc dev guide.