mirror of
https://github.com/rust-lang/rust.git
synced 2026-04-30 06:43:20 +03:00
Matthias Krüger
c0bedb9e5e
Retroactively feature gate `ConstArgKind::Path` This puts the lowering introduced by #125915 under a feature gate until we fix the regressions introduced by it. Alternative to whole sale reverting the PR since it didn't seem like a very clean revert and I think this is generally a step in the right direction and don't want to get stuck landing and reverting the PR over and over :) cc #129137 ``@camelid,`` tests taken from there. beta is branching soon so I think it makes sense to not try and rush that fix through since it wont have much time to bake and if it has issues we can't simply revert it on beta. Fixes #128016
482 lines
22 KiB
Rust
482 lines
22 KiB
Rust
use std::collections::hash_map::Entry;
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use std::fmt::Write;
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use rustc_ast::ptr::P;
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use rustc_ast::*;
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use rustc_data_structures::fx::{FxHashMap, FxHashSet, FxIndexMap};
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use rustc_hir as hir;
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use rustc_hir::def::{DefKind, Res};
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use rustc_session::parse::feature_err;
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use rustc_span::symbol::kw;
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use rustc_span::{sym, Span};
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use rustc_target::asm;
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use super::errors::{
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AbiSpecifiedMultipleTimes, AttSyntaxOnlyX86, ClobberAbiNotSupported,
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InlineAsmUnsupportedTarget, InvalidAbiClobberAbi, InvalidAsmTemplateModifierConst,
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InvalidAsmTemplateModifierLabel, InvalidAsmTemplateModifierRegClass,
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InvalidAsmTemplateModifierRegClassSub, InvalidAsmTemplateModifierSym, InvalidRegister,
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InvalidRegisterClass, RegisterClassOnlyClobber, RegisterConflict,
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};
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use super::LoweringContext;
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use crate::{
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fluent_generated as fluent, ImplTraitContext, ImplTraitPosition, ParamMode,
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ResolverAstLoweringExt,
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};
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impl<'a, 'hir> LoweringContext<'a, 'hir> {
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pub(crate) fn lower_inline_asm(
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&mut self,
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sp: Span,
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asm: &InlineAsm,
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) -> &'hir hir::InlineAsm<'hir> {
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// Rustdoc needs to support asm! from foreign architectures: don't try
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// lowering the register constraints in this case.
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let asm_arch =
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if self.tcx.sess.opts.actually_rustdoc { None } else { self.tcx.sess.asm_arch };
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if asm_arch.is_none() && !self.tcx.sess.opts.actually_rustdoc {
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self.dcx().emit_err(InlineAsmUnsupportedTarget { span: sp });
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}
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if let Some(asm_arch) = asm_arch {
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// Inline assembly is currently only stable for these architectures.
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let is_stable = matches!(
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asm_arch,
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asm::InlineAsmArch::X86
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| asm::InlineAsmArch::X86_64
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| asm::InlineAsmArch::Arm
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| asm::InlineAsmArch::AArch64
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| asm::InlineAsmArch::RiscV32
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| asm::InlineAsmArch::RiscV64
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| asm::InlineAsmArch::LoongArch64
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);
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if !is_stable && !self.tcx.features().asm_experimental_arch {
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feature_err(
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&self.tcx.sess,
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sym::asm_experimental_arch,
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sp,
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fluent::ast_lowering_unstable_inline_assembly,
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)
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.emit();
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}
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}
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if asm.options.contains(InlineAsmOptions::ATT_SYNTAX)
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&& !matches!(asm_arch, Some(asm::InlineAsmArch::X86 | asm::InlineAsmArch::X86_64))
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&& !self.tcx.sess.opts.actually_rustdoc
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{
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self.dcx().emit_err(AttSyntaxOnlyX86 { span: sp });
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}
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if asm.options.contains(InlineAsmOptions::MAY_UNWIND) && !self.tcx.features().asm_unwind {
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feature_err(
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&self.tcx.sess,
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sym::asm_unwind,
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sp,
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fluent::ast_lowering_unstable_may_unwind,
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)
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.emit();
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}
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let mut clobber_abis = FxIndexMap::default();
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if let Some(asm_arch) = asm_arch {
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for (abi_name, abi_span) in &asm.clobber_abis {
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match asm::InlineAsmClobberAbi::parse(asm_arch, &self.tcx.sess.target, *abi_name) {
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Ok(abi) => {
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// If the abi was already in the list, emit an error
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match clobber_abis.get(&abi) {
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Some((prev_name, prev_sp)) => {
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// Multiple different abi names may actually be the same ABI
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// If the specified ABIs are not the same name, alert the user that they resolve to the same ABI
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let source_map = self.tcx.sess.source_map();
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let equivalent = source_map.span_to_snippet(*prev_sp)
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!= source_map.span_to_snippet(*abi_span);
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self.dcx().emit_err(AbiSpecifiedMultipleTimes {
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abi_span: *abi_span,
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prev_name: *prev_name,
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prev_span: *prev_sp,
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equivalent,
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});
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}
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None => {
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clobber_abis.insert(abi, (*abi_name, *abi_span));
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}
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}
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}
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Err(&[]) => {
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self.dcx().emit_err(ClobberAbiNotSupported { abi_span: *abi_span });
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}
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Err(supported_abis) => {
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let mut abis = format!("`{}`", supported_abis[0]);
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for m in &supported_abis[1..] {
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let _ = write!(abis, ", `{m}`");
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}
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self.dcx().emit_err(InvalidAbiClobberAbi {
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abi_span: *abi_span,
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supported_abis: abis,
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});
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}
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}
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}
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}
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// Lower operands to HIR. We use dummy register classes if an error
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// occurs during lowering because we still need to be able to produce a
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// valid HIR.
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let sess = self.tcx.sess;
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let mut operands: Vec<_> = asm
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.operands
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.iter()
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.map(|(op, op_sp)| {
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let lower_reg = |®: &_| match reg {
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InlineAsmRegOrRegClass::Reg(reg) => {
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asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
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asm::InlineAsmReg::parse(asm_arch, reg).unwrap_or_else(|error| {
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self.dcx().emit_err(InvalidRegister {
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op_span: *op_sp,
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reg,
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error,
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});
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asm::InlineAsmReg::Err
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})
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} else {
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asm::InlineAsmReg::Err
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})
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}
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InlineAsmRegOrRegClass::RegClass(reg_class) => {
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asm::InlineAsmRegOrRegClass::RegClass(if let Some(asm_arch) = asm_arch {
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asm::InlineAsmRegClass::parse(asm_arch, reg_class).unwrap_or_else(
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|error| {
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self.dcx().emit_err(InvalidRegisterClass {
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op_span: *op_sp,
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reg_class,
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error,
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});
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asm::InlineAsmRegClass::Err
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},
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)
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} else {
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asm::InlineAsmRegClass::Err
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})
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}
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};
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let op = match op {
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InlineAsmOperand::In { reg, expr } => hir::InlineAsmOperand::In {
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reg: lower_reg(reg),
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expr: self.lower_expr(expr),
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},
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InlineAsmOperand::Out { reg, late, expr } => hir::InlineAsmOperand::Out {
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reg: lower_reg(reg),
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late: *late,
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expr: expr.as_ref().map(|expr| self.lower_expr(expr)),
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},
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InlineAsmOperand::InOut { reg, late, expr } => hir::InlineAsmOperand::InOut {
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reg: lower_reg(reg),
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late: *late,
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expr: self.lower_expr(expr),
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},
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InlineAsmOperand::SplitInOut { reg, late, in_expr, out_expr } => {
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hir::InlineAsmOperand::SplitInOut {
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reg: lower_reg(reg),
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late: *late,
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in_expr: self.lower_expr(in_expr),
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out_expr: out_expr.as_ref().map(|expr| self.lower_expr(expr)),
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}
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}
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InlineAsmOperand::Const { anon_const } => hir::InlineAsmOperand::Const {
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anon_const: self.lower_anon_const_to_anon_const(anon_const),
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},
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InlineAsmOperand::Sym { sym } => {
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let static_def_id = self
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.resolver
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.get_partial_res(sym.id)
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.and_then(|res| res.full_res())
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.and_then(|res| match res {
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Res::Def(DefKind::Static { .. }, def_id) => Some(def_id),
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_ => None,
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});
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if let Some(def_id) = static_def_id {
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let path = self.lower_qpath(
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sym.id,
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&sym.qself,
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&sym.path,
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ParamMode::Optional,
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ImplTraitContext::Disallowed(ImplTraitPosition::Path),
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None,
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);
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hir::InlineAsmOperand::SymStatic { path, def_id }
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} else {
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// Replace the InlineAsmSym AST node with an
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// Expr using the name node id.
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let expr = Expr {
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id: sym.id,
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kind: ExprKind::Path(sym.qself.clone(), sym.path.clone()),
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span: *op_sp,
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attrs: AttrVec::new(),
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tokens: None,
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};
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// Wrap the expression in an AnonConst.
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let parent_def_id = self.current_def_id_parent;
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let node_id = self.next_node_id();
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// HACK(min_generic_const_args): see lower_anon_const
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if !self.tcx.features().const_arg_path
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|| !expr.is_potential_trivial_const_arg()
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{
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self.create_def(
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parent_def_id,
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node_id,
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kw::Empty,
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DefKind::AnonConst,
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*op_sp,
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);
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}
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let anon_const = AnonConst { id: node_id, value: P(expr) };
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hir::InlineAsmOperand::SymFn {
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anon_const: self.lower_anon_const_to_anon_const(&anon_const),
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}
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}
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}
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InlineAsmOperand::Label { block } => {
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if !self.tcx.features().asm_goto {
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feature_err(
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sess,
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sym::asm_goto,
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*op_sp,
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fluent::ast_lowering_unstable_inline_assembly_label_operands,
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)
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.emit();
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}
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hir::InlineAsmOperand::Label { block: self.lower_block(block, false) }
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}
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};
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(op, self.lower_span(*op_sp))
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})
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.collect();
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// Validate template modifiers against the register classes for the operands
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for p in &asm.template {
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if let InlineAsmTemplatePiece::Placeholder {
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operand_idx,
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modifier: Some(modifier),
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span: placeholder_span,
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} = *p
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{
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let op_sp = asm.operands[operand_idx].1;
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match &operands[operand_idx].0 {
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hir::InlineAsmOperand::In { reg, .. }
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| hir::InlineAsmOperand::Out { reg, .. }
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| hir::InlineAsmOperand::InOut { reg, .. }
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| hir::InlineAsmOperand::SplitInOut { reg, .. } => {
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let class = reg.reg_class();
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if class == asm::InlineAsmRegClass::Err {
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continue;
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}
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let valid_modifiers = class.valid_modifiers(asm_arch.unwrap());
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if !valid_modifiers.contains(&modifier) {
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let sub = if !valid_modifiers.is_empty() {
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let mut mods = format!("`{}`", valid_modifiers[0]);
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for m in &valid_modifiers[1..] {
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let _ = write!(mods, ", `{m}`");
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}
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InvalidAsmTemplateModifierRegClassSub::SupportModifier {
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class_name: class.name(),
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modifiers: mods,
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}
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} else {
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InvalidAsmTemplateModifierRegClassSub::DoesNotSupportModifier {
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class_name: class.name(),
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}
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};
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self.dcx().emit_err(InvalidAsmTemplateModifierRegClass {
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placeholder_span,
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op_span: op_sp,
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sub,
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});
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}
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}
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hir::InlineAsmOperand::Const { .. } => {
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self.dcx().emit_err(InvalidAsmTemplateModifierConst {
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placeholder_span,
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op_span: op_sp,
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});
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}
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hir::InlineAsmOperand::SymFn { .. }
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| hir::InlineAsmOperand::SymStatic { .. } => {
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self.dcx().emit_err(InvalidAsmTemplateModifierSym {
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placeholder_span,
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op_span: op_sp,
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});
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}
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hir::InlineAsmOperand::Label { .. } => {
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self.dcx().emit_err(InvalidAsmTemplateModifierLabel {
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placeholder_span,
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op_span: op_sp,
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});
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}
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}
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}
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}
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let mut used_input_regs = FxHashMap::default();
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let mut used_output_regs = FxHashMap::default();
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for (idx, &(ref op, op_sp)) in operands.iter().enumerate() {
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if let Some(reg) = op.reg() {
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let reg_class = reg.reg_class();
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if reg_class == asm::InlineAsmRegClass::Err {
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continue;
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}
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// Some register classes can only be used as clobbers. This
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// means that we disallow passing a value in/out of the asm and
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// require that the operand name an explicit register, not a
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// register class.
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if reg_class.is_clobber_only(asm_arch.unwrap()) && !op.is_clobber() {
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self.dcx().emit_err(RegisterClassOnlyClobber {
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op_span: op_sp,
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reg_class_name: reg_class.name(),
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});
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continue;
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}
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// Check for conflicts between explicit register operands.
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if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
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let (input, output) = match op {
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hir::InlineAsmOperand::In { .. } => (true, false),
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// Late output do not conflict with inputs, but normal outputs do
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hir::InlineAsmOperand::Out { late, .. } => (!late, true),
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hir::InlineAsmOperand::InOut { .. }
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| hir::InlineAsmOperand::SplitInOut { .. } => (true, true),
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hir::InlineAsmOperand::Const { .. }
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| hir::InlineAsmOperand::SymFn { .. }
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| hir::InlineAsmOperand::SymStatic { .. }
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| hir::InlineAsmOperand::Label { .. } => {
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unreachable!("{op:?} is not a register operand");
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}
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};
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// Flag to output the error only once per operand
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let mut skip = false;
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let mut check = |used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
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input,
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r: asm::InlineAsmReg| {
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match used_regs.entry(r) {
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Entry::Occupied(o) => {
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if skip {
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return;
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}
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skip = true;
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let idx2 = *o.get();
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let (ref op2, op_sp2) = operands[idx2];
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let in_out = match (op, op2) {
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(
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hir::InlineAsmOperand::In { .. },
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hir::InlineAsmOperand::Out { late, .. },
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)
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| (
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hir::InlineAsmOperand::Out { late, .. },
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hir::InlineAsmOperand::In { .. },
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) => {
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assert!(!*late);
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let out_op_sp = if input { op_sp2 } else { op_sp };
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Some(out_op_sp)
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}
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_ => None,
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};
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let reg_str = |idx| -> &str {
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// HIR asm doesn't preserve the original alias string of the explicit register,
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// so we have to retrieve it from AST
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let (op, _): &(InlineAsmOperand, Span) = &asm.operands[idx];
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if let Some(ast::InlineAsmRegOrRegClass::Reg(reg_sym)) =
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op.reg()
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{
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reg_sym.as_str()
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} else {
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unreachable!("{op:?} is not a register operand");
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}
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};
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self.dcx().emit_err(RegisterConflict {
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op_span1: op_sp,
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op_span2: op_sp2,
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reg1_name: reg_str(idx),
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reg2_name: reg_str(idx2),
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in_out,
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});
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}
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Entry::Vacant(v) => {
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if r == reg {
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v.insert(idx);
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}
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}
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}
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};
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let mut overlapping_with = vec![];
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reg.overlapping_regs(|r| {
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overlapping_with.push(r);
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});
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for r in overlapping_with {
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if input {
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check(&mut used_input_regs, true, r);
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}
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if output {
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check(&mut used_output_regs, false, r);
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}
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}
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}
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}
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}
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// If a clobber_abi is specified, add the necessary clobbers to the
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// operands list.
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let mut clobbered = FxHashSet::default();
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for (abi, (_, abi_span)) in clobber_abis {
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for &clobber in abi.clobbered_regs() {
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// Don't emit a clobber for a register already clobbered
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if clobbered.contains(&clobber) {
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continue;
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}
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let mut overlapping_with = vec![];
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clobber.overlapping_regs(|reg| {
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overlapping_with.push(reg);
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});
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let output_used =
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overlapping_with.iter().any(|reg| used_output_regs.contains_key(®));
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if !output_used {
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operands.push((
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hir::InlineAsmOperand::Out {
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reg: asm::InlineAsmRegOrRegClass::Reg(clobber),
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late: true,
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expr: None,
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},
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self.lower_span(abi_span),
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));
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clobbered.insert(clobber);
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}
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}
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}
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let operands = self.arena.alloc_from_iter(operands);
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let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
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let template_strs = self.arena.alloc_from_iter(
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asm.template_strs
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.iter()
|
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.map(|(sym, snippet, span)| (*sym, *snippet, self.lower_span(*span))),
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);
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let line_spans =
|
|
self.arena.alloc_from_iter(asm.line_spans.iter().map(|span| self.lower_span(*span)));
|
|
let hir_asm =
|
|
hir::InlineAsm { template, template_strs, operands, options: asm.options, line_spans };
|
|
self.arena.alloc(hir_asm)
|
|
}
|
|
}
|