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Jed Brown
6dbac3f09e
Add target features for sm_* and ptx*, both of which form a partial order, but cannot be combined to a single partial order. These mirror the LLVM target features, but we do not provide LLVM target processors (which imply both an sm_* and ptx* feature). Add some documentation for the nvptx target.
35 lines
1019 B
Rust
35 lines
1019 B
Rust
//@ only-x86_64
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//
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// gate-test-sse4a_target_feature
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// gate-test-powerpc_target_feature
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// gate-test-tbm_target_feature
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// gate-test-arm_target_feature
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// gate-test-hexagon_target_feature
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// gate-test-mips_target_feature
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// gate-test-nvptx_target_feature
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// gate-test-wasm_target_feature
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// gate-test-adx_target_feature
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// gate-test-cmpxchg16b_target_feature
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// gate-test-movbe_target_feature
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// gate-test-rtm_target_feature
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// gate-test-f16c_target_feature
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// gate-test-riscv_target_feature
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// gate-test-ermsb_target_feature
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// gate-test-bpf_target_feature
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// gate-test-aarch64_ver_target_feature
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// gate-test-aarch64_unstable_target_feature
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// gate-test-csky_target_feature
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// gate-test-loongarch_target_feature
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// gate-test-lahfsahf_target_feature
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// gate-test-prfchw_target_feature
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// gate-test-s390x_target_feature
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// gate-test-sparc_target_feature
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// gate-test-x87_target_feature
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// gate-test-m68k_target_feature
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#[target_feature(enable = "x87")]
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//~^ ERROR: currently unstable
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unsafe fn foo() {}
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fn main() {}
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