Brian Cain aa9da4b859 Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes ...

Add new Hexagon inline asm register classes:
- reg_pair: GPR double registers (r1:0 through r27:26) for i64/f64 types
- vreg: HVX vector registers (v0-v31) for mode-dependent vector types
- vreg_pair: HVX vector pair registers (v1:0 through v31:30) for vector pairs
- qreg: HVX predicate registers (q0-q3), clobber-only

Key implementation details:
- GPR pairs use LLVM's 'd' register naming (d0-d13) for constraints
- HVX vector pairs use LLVM's 'w' register naming (w0-w15) for constraints
- Register overlap tracking for GPR pair<->single and HVX pair<->single conflicts
- HVX vector types are mode-dependent (64B vs 128B HVX length)

Note: vreg_quad (HVX vector quads) is not supported as LLVM's Hexagon
backend does not support vector quad types in inline asm constraints.

2026-04-07 09:27:32 -07:00

..

bad-reg.rs

Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes

2026-04-07 09:27:32 -07:00

bad-reg.stderr

Hexagon inline asm: add reg_pair, vreg, vreg_pair, and qreg register classes

2026-04-07 09:27:32 -07:00